Trench gate metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The present application relates to a trench-gate metal-oxide-semiconductor field-effect transistor and a method for fabricating the same, comprising: a first-conductivity-type drift region; a second-conductivity-type body region formed within the drift region; a first-conductivity-type source region formed within the body region, the source region having a trench extending into the drift region; a first conductive structure and a second conductive structure filled within the trench, the first conductive structure having a bottom depth greater than the second conductive structure, and a portion of the first conductive structure whose depth exceeds the second conductive structure's bottom depth being defined as a field plate adjustment structure; a first doped region of the second conductivity type formed within the drift region and in contact with the body region, the first doped region having a bottom depth greater than the top depth of the field plate adjustment structure; the source region and the body region being connected to a source electrode; and the second conductive structure being connected to a gate electrode. Forming the first doped region and the field plate adjustment structure enhances depletion in the drift region and improves the device's withstand voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a trench gate metal oxide semiconductor field effect transistor and a preparation method thereof. Background Art

[0002] In a metal oxide semiconductor field effect transistor (MOS) (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), a conduction channel is formed between the source and drain. The existence of the conduction channel gives the MOS FET a certain on-resistance. The larger the on-resistance, the greater the power consumption. Therefore, the on-resistance needs to be minimized. Currently, MOS FETs with a trench gate structure are commonly used. By forming a trench gate structure, the conduction channel is changed from horizontal to vertical, which greatly increases the cell density and reduces the on-resistance. However, based on the trench gate MOS FET, if the on-resistance is to be further reduced, the doping concentration of the drift region needs to be increased. However, increasing the doping concentration will reduce the voltage withstand capability of the device. Therefore, due to the limitation of the voltage withstand capability, it becomes difficult to further reduce the on-resistance of the trench gate MOS FET. Summary of the Invention

[0003] Based on this, it is necessary to propose a new metal oxide semiconductor field effect transistor and its preparation method to address the technical problem that the current trench gate metal oxide semiconductor field effect transistor is difficult to further reduce the on-resistance.

[0004] A trench gate metal oxide semiconductor field effect transistor, comprising:

[0005] a drift region having a first conductivity type and formed on a semiconductor substrate;

[0006] a body region having a second conductivity type and formed on an upper surface layer of the drift region;

[0007] a source region having a first conductivity type and formed on an upper surface layer of the body region;

[0008] a trench, sequentially penetrating the source region and the body region and extending into the drift region;

[0009] a filling structure comprising a first conductive structure and a second conductive structure filled in the trench and isolated from each other, and an oxide layer formed between the first conductive structure and the inner wall of the trench and between the second conductive structure and the inner wall of the trench, wherein the bottom depth of the first conductive structure exceeds the bottom depth of the second conductive structure, and a portion of the first conductive structure having a depth exceeding the bottom depth of the second conductive structure is defined as a field plate adjustment structure;

[0010] a first doped region having a second conductivity type, formed in the drift region and in contact with a lower surface of the body region, the first doped region being spaced apart from the trench, and a bottom depth of the first doped region exceeding a top depth of the field plate adjustment structure;

[0011] a source lead-out structure connected to the source region and the body region; and

[0012] The gate lead-out structure is connected to the second conductive structure.

[0013] In one embodiment, the sidewall of the first doped region includes a first portion extending downward from the bottom of the body region and parallel to the trench sidewall, and a second portion continuing to extend downward from the first portion and gradually tilting toward the interior of the first doped region, and the interface between the first portion and the second portion passes through the field plate adjustment structure.

[0014] In one embodiment, the metal oxide semiconductor field effect transistor has a plurality of the first doping regions and is provided with a plurality of the trenches, each trench is filled with the filling structure, and the first doping regions and the trenches are alternately arranged.

[0015] In one embodiment, the cross section of the trench is in the shape of an elongated strip, and a plurality of the first doping regions are arranged side by side and spaced apart along the length direction of the trench between adjacent trenches.

[0016] In one embodiment, it further includes:

[0017] an interlayer dielectric layer formed on the top surfaces of the source region and the trench;

[0018] The source lead-out structure penetrates the interlayer dielectric layer and the source region and extends into the body region to be connected to the source region and the body region respectively;

[0019] The gate lead structure penetrates the interlayer dielectric layer and is connected to the second conductive structure.

[0020] In one embodiment, a second doped region is formed in the body region, the second doped region has a second conductivity type and the doping concentration of the second doped region is higher than the doping concentration of the body region, the second doped region is located below the source region and is spaced apart from the trench, and the source lead-out structure penetrates the source region and extends into the second doped region.

[0021] The above-mentioned metal oxide semiconductor field effect transistor has a trench in the cell region, and a second conductive structure and an oxide layer are formed in the trench. The second conductive structure is a gate conductive structure, and the oxide layer between the second conductive structure and the inner wall of the trench is a gate oxide layer. The second conductive structure is connected to the gate via a gate lead structure, thereby forming a trench gate structure. This trench gate structure forms a longitudinal conductive channel in the body region. In addition to the second conductive structure, the trench is also filled with a first conductive structure isolated from the second conductive structure. The depth of the first conductive structure is greater than that of the second conductive structure. The portion of the first conductive structure that exceeds the depth of the bottom of the second conductive structure is a field plate adjustment structure, which is equivalent to forming an internal field plate in the cell region to adjust the electric field in the drift region. At the same time, a first doped region is also formed in the cell region. The first doped region is connected to the body region and has a source potential. The conductivity type of the first doped region is opposite to that of the drift region. The bottom depth of the first doped region exceeds the top depth of the field plate adjustment structure, so that the depletion region formed by the first doped region and the internal field plate are at the same height. Under the combined action of the first doped region and the internal field plate, the depletion of the drift region can be enhanced, thereby increasing the breakdown voltage of the drift region. Therefore, under conditions of equal breakdown voltage, the drift region of the trench-gate metal oxide semiconductor field effect transistor in this application can increase the doping concentration, thereby reducing the on-resistance. That is, under conditions of equal breakdown voltage, the trench-gate metal oxide semiconductor field effect transistor in this application has a lower on-resistance.

[0022] A method for preparing a trench gate metal oxide semiconductor field effect transistor, comprising:

[0023] Providing a semiconductor substrate and forming a drift region having a first conductivity type on the semiconductor substrate;

[0024] A trench is formed in the drift region, an oxide layer is formed on an inner wall of the trench, and a first conductive structure and a second conductive structure isolated from each other are filled in the trench, wherein the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure, and a portion of the first conductive structure whose depth exceeds the bottom depth of the second conductive structure is defined as a field plate adjustment structure;

[0025] Doping the upper surface layer of the drift region to form a body region of the second conductivity type in contact with the sidewall of the trench, wherein the depth of the body region is less than the depth of the trench; doping the upper surface layer of the body region to form a source region of the first conductivity type in contact with the sidewall of the trench;

[0026] forming a first doped region of the second conductivity type in the drift region, wherein the first doped region is in contact with the body region, the first doped region is spaced apart from the trench, and a bottom depth of the first doped region exceeds a top depth of the field plate adjustment structure; and

[0027] A source lead-out structure connected to the source region and the body region is formed, and a gate lead-out structure connected to the second conductive structure is formed.

[0028] In one embodiment, after the step of doping the upper surface layer of the body region to form a first conductivity type source region in contact with the sidewall of the trench, the method further includes:

[0029] forming an interlayer dielectric layer on the source region and the trench;

[0030] etching the interlayer dielectric layer, the source region, and the body region in sequence to form a source contact hole penetrating the dielectric layer and the source region and extending to the body region;

[0031] The forming of the first doped region in the drift region in contact with the lower surface of the body region comprises: injecting second conductive type impurities into the drift region through the source contact hole to form the first doped region in the drift region in contact with the lower surface of the body region;

[0032] The forming of the source lead-out structure connected to the source region, the body region and the first conductive structure includes: filling the source contact hole with a conductive material to form the source lead-out structure.

[0033] In one embodiment, forming a first doped region having a second conductivity type in the drift region includes:

[0034] epitaxially growing a first epitaxial layer on the semiconductor substrate;

[0035] doping the first epitaxial layer to form a first doped region having a second conductivity type;

[0036] A second epitaxial layer is continuously grown on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

[0037] In one embodiment, forming a first doped region having a second conductivity type in the drift region includes:

[0038] epitaxially growing a first epitaxial layer on the semiconductor substrate;

[0039] Opening a shallow trench on the first epitaxial layer, and epitaxially growing a first doped region of the second conductivity type in the shallow trench;

[0040] A second epitaxial layer is continuously grown on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

[0041] The above-mentioned trench-gate MOSFET fabrication method provides a first conductive structure at the bottom of the trench gate, which is equivalent to providing an internal field plate in the drift region for regulating the electric field in the drift region. Furthermore, a first doped region is provided in the drift region. The first doped region has an opposite conductivity type to the drift region and is connected to the source via the body region. The combined action of the first doped region and the field plate structure at the bottom of the trench gate enhances depletion of the drift region, thereby improving the device's withstand voltage. Therefore, under conditions of equivalent breakdown voltage, the trench-gate MOSFET formed by the fabrication method of the present application can have a higher doping concentration in its drift region, resulting in a lower on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A partial side cross-sectional view of a cell region of a trench-gate metal oxide semiconductor field effect transistor in one embodiment of the present application;

[0043] Figure 2 A partial side cross-sectional view of a trench-gate metal oxide semiconductor field effect transistor cell region in another embodiment of the present application;

[0044] Figure 3a In one embodiment of the present application, a trench gate metal oxide semiconductor field effect transistor is provided. Figure 1 Cross-section along section line A-A';

[0045] Figure 3b In another embodiment of the present application, a trench gate metal oxide semiconductor field effect transistor is provided. Figure 1 Cross-section along section line A-A';

[0046] Figure 4a This is a schematic diagram of the structure in the groove in one embodiment of the present application;

[0047] Figure 4b This is a schematic diagram of the structure in the groove in another embodiment of the present application;

[0048] Figure 5 This is a flow chart of the steps of a method for preparing a trench gate metal oxide semiconductor field effect transistor in one embodiment of the present application;

[0049] Figure 6a to Figure 6h This is a structural cross-sectional view corresponding to relevant steps of a method for preparing a trench-gate metal oxide semiconductor field effect transistor in one embodiment of the present application;

[0050] Figure 7a to Figure 7c This is a structural cross-sectional view corresponding to the steps of forming the first doped region in one embodiment of the present application.

[0051] Description of labels

[0052] 100 drift region; 101 first epitaxial layer; 102 second epitaxial layer; 110 body region; 111 source region; 112 second doped region; 120 oxide layer; 130 first conductive structure; 140 second conductive structure; 150 isolation structure; 160 second doped region; 200 interlayer dielectric layer; 310 source lead structure. DETAILED DESCRIPTION

[0053] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0055] Combine Figure 1 As shown, the trench-gate MOSFET includes a drift region 100 formed on a semiconductor substrate. Specifically, the drift region 100 can be formed by epitaxial growth of the semiconductor substrate. A body region 110 is formed on the surface of the drift region 100, and an active region 111 is formed on the surface of the body region 110.

[0056] The source region 111 is provided with a trench that penetrates the source region 111 and the body region 110 and extends into the drift region 100, i.e., the bottom of the trench is located within the drift region 100. The trench is filled with a first conductive structure 130 and a second conductive structure 140 that are isolated from each other. An oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench, and between the second conductive structure 140 and the inner wall of the trench. The oxide layer 120 located between the first conductive structure 130 and the inner wall of the trench is a gate oxide layer, and the oxide layer located between the second conductive structure 140 and the inner wall of the trench is an isolation oxide layer. The oxide layer 120 filled in the trench and the isolated first conductive structure 130 and second conductive structure 140 together constitute a filling structure. In the same trench, the depth of the first conductive structure 130 is greater than the depth of the second conductive structure 140, that is, the distance between the first conductive structure 130 and the bottom of the trench is less than the distance between the second conductive structure 140 and the bottom of the trench. The portion of the first conductive structure 130 whose depth exceeds the bottom depth of the second conductive structure 140 is defined as the field plate adjustment structure, that is, the portion of the first conductive structure located below the second conductive structure 140 is the field plate adjustment structure.

[0057] A first doped region 160 is also formed in the drift region 100. The top of the first doped region 160 is connected to the body region 110, and the first doped region 160 is spaced apart from the trench. The bottom depth of the first doped region 160 exceeds the top depth of the above-mentioned field plate adjustment structure, that is, the first doped region 160 and the lateral projection of the field plate adjustment structure have an overlapping area.

[0058] The trench-gate MOSFET further includes a source lead-out structure 310 and a gate lead-out structure (not shown). The source lead-out structure 310 and the gate lead-out structure can be metal pillars, specifically tungsten. The source lead-out structure 310 is connected to the source region 111 and the body region 110, and the gate lead-out structure is connected to the second conductive structure 140 in the trench.

[0059] The drift region 100 and source region 111 have a first conductivity type, and the body region 110 and first doped region 160 have a second conductivity type. The first conductivity type is N-type and the second conductivity type is P-type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type. It is understood that the front surface of the trench-gate MOSFET should also have a mutually isolated source metal layer and gate metal layer, the source lead-out structure 310 is connected to the source metal layer, the gate lead-out structure is connected to the gate metal layer, and a drain metal layer is also formed on the back surface of the trench-gate MOSFET.

[0060] In the trench-gate MOSFET, the top source region 111 is connected to the source metal layer via a source lead-out structure 310. The bottom drift region 100 serves as a drain region and is connected to the drain metal layer. The body region 110 in the middle forms a channel region. A trench penetrates the body region 110 and extends into the drift region 100. The trench contains an oxide layer 120 and a second conductive structure 140, which is connected to the gate metal layer via a gate lead-out structure. In other words, the trench, the gate oxide layer, and the second conductive structure 140 within it constitute a trench gate structure, thereby forming a trench-gate MOSFET. This trench gate structure allows for the formation of a longitudinal conductive channel within the body region 110.

[0061] Furthermore, a first conductive structure 130 is formed within the bottom of the trench. The portion of the first conductive structure located below the second conductive structure 140 serves as a field plate adjustment structure. This field plate adjustment structure and the isolation oxide layer in contact with it form an inner field plate, which regulates the electric field distribution within the drift region 100, causing the drift region in contact with the inner field plate to form a depletion region, thereby enhancing depletion in the drift region 100. Furthermore, a first doped region 160 is formed within the drift region 100. The first doped region 160 has a source potential and a conductivity type opposite to that of the drift region 100. The first doped region 160 and the drift region 100 form an inverse PN junction, further enhancing depletion in the drift region 100. Furthermore, in the present application, the bottom depth of the first doped region 160 exceeds the top depth of the field plate adjustment structure, allowing the depletion region formed by the first doped region 160 and the depletion region formed by the inner field plate to be laterally aligned, further increasing the withstand voltage of the drift region 100. Compared to conventional trench-gate MOSFETs, the trench-gate MOSFET in this application has a higher breakdown voltage. That is, while maintaining the same breakdown voltage, the drift region 100 of the trench-gate MOSFET in this application can have a higher doping concentration. Consequently, the trench-gate MOSFET in this application also has a lower on-resistance. Furthermore, within the trench, the first conductive structure 130 connected to the source metal layer is closer to the trench bottom than the second conductive structure 140 connected to the gate. This reduces the parasitic capacitance between the gate and drain, resulting in better device characteristics.

[0062] In one embodiment, if Figure 2 As shown, the sidewall of the first doped region 160 includes a first portion 161 extending downward from the bottom of the body region 110 and a first portion 162 extending downward from the first portion. The first portion 161 is parallel to the trench sidewall, and the longitudinal cross-section of the first portion 161 is rectangular. The distance between the first portion 161 and the trench sidewall is equal at all locations. The second portion 162 gradually tilts from top to bottom toward the interior of the first doped region 160. The longitudinal cross-section of the second portion 162 is an inverted trapezoid or an inverted triangle, and the distance between the second portion 162 and the trench sidewall gradually increases from top to bottom. At the same time, the interface between the first portion 161 and the second portion 162 ( Figure 2The dotted line (shown as a dashed line) passes through the field plate adjustment structure, that is, through the first conductive structure 130 in the trench, but not through the second conductive structure 140. In the present application, the first doped region 160 must be spaced apart from the trench, that is, the first doped region 160 must be spaced apart from the trench gate to allow current to flow between the drain and the source. In a metal oxide semiconductor field effect transistor, because the body region 110 only forms a narrow channel region near the trench sidewalls for current to pass, the current density near the trench in the drift region 100 is also the highest. The farther away from the trench, the lower the current density. The first doped region 160 can be located in an area with low current density to reduce its blocking effect on current flow. In other words, increasing the distance between the first doped region 160 and the trench is beneficial for reducing the on-resistance of the VDMOS. However, the greater the distance between the first doped region 160 and the field plate adjustment structure, the larger the distance between adjacent depletion layers, thereby weakening the withstand voltage capability. In this embodiment, the shape of the first doped region 160 is further improved, so that the distance between the upper sidewall of the first doped region 160 and the field plate adjustment structure is relatively small, forming a densely distributed depletion layer, while the lower sidewall gradually slopes inward to increase the distance between the first doped region and the trench, thereby reducing the area of the first doped region 160. This ensures the withstand voltage capability while reducing the device on-resistance. Furthermore, the depletion layer formed by the first doped region 160 and the depletion layer formed by the internal field plate extend outward and connect to each other, thus achieving even better withstand voltage performance.

[0063] In one embodiment, if Figure 1 As shown, the MOSFET has multiple first doped regions 160 and multiple trenches, each of which is filled with the aforementioned filling structure. The first doped regions 160 are alternately spaced with the trenches. In this embodiment, multiple trenches are provided to form a multiple trench gate structure, which can increase current density. A first doped region is provided between each trench. The first doped region and the field plate within the trench increase the distribution density of the depletion region, thereby further improving the withstand voltage capability.

[0064] Further, such as Figure 3a One embodiment is shown along Figure 1 A cross-sectional view taken along section line AA' shows a long, strip-shaped trench cross section with multiple first doped regions 160 spaced side by side along the trench length between adjacent trenches. In this embodiment, the first doped regions 160 between adjacent trenches are segmented to reduce the space occupied by the first doped regions 160, thereby reducing the on-resistance of the device. In one embodiment, the depletion regions formed by adjacent first doped regions 160 extend in all directions and interconnect, thereby reducing the on-resistance while increasing the device's withstand voltage.

[0065] In another embodiment, Figure 3b Another embodiment is shown along Figure 1 A cross-sectional view taken along section line AA' shows a trench with an elongated cross-section. A first doped region 160 is located between adjacent trenches, and the first doped region 160 is also elongated. In this embodiment, the elongated first doped region 160 is provided between adjacent trench gate structures to enhance the depletion capability of the first doped region 160 in the drift region 100, thereby increasing the device's withstand voltage.

[0066] In one embodiment, if Figure 1 As shown, an interlayer dielectric layer 200 is also formed on the source region 111 and the trench. The interlayer dielectric layer 200 can specifically be silicon oxide. The source lead structure 310 penetrates the interlayer dielectric layer 200 and the source region 111 and extends into the body region 110 to connect with the source region 111 and the body region 110. The gate lead structure is formed directly above the trench, penetrates the interlayer dielectric layer 200 and connects to the second conductive structure 140 in the trench. Furthermore, the gate lead structure and the source lead structure are staggered to facilitate connection with the gate metal layer and the source metal layer, respectively. The first conductive structure 130 can be a floating structure without charge, forming a floating internal field plate, or it can be electrically connected to the source to form a charged internal field plate.

[0067] In one embodiment, when preparing the source lead-out structure 310, a source contact hole needs to be opened. In the actual process, the first doped region 160 is formed by injecting doping ions into the drift region through the source contact hole. Therefore, the first doped region 160 is specifically formed in the orthographic projection area of the source lead-out structure 310, or covers the orthographic projection area of the source lead-out structure 310 and spreads evenly around from the orthographic projection area.

[0068] In one embodiment, if Figure 1 As shown, a second doping region 112 is also formed in the body region 110. The second doping region 112 has a second conductivity type, and the doping concentration of the second doping region 112 is higher than the doping concentration of the body region 110. The second doping region 112 is specifically located below the source region 111 and is spaced apart from the trench. The source lead-out structure 310 penetrates the source region 111 and extends into the second doping region 112. The source lead-out structure 310 is connected to the source region 111, and its bottom is surrounded by the second doping region 112, thereby reducing the contact resistance between the source lead-out structure 310 and the body region 110.

[0069] The distribution of the first conductive structure 130 and the second conductive structure 140 in the groove 120 can be designed in various ways. Figure 1As shown, in the trench, the first conductive structure 130 is distributed at the bottom of the trench, the second conductive structure 140 is distributed at the top of the trench, and the first conductive structure 130 and the second conductive structure 140 are isolated by an isolation structure 150, wherein an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench. Specifically, the isolation structure 150 is silicon oxide. In this embodiment, the first conductive structure 130 at the bottom of the trench can not only adjust the electric field in the drift region and enhance the depletion of the drift region, but also reduce the parasitic capacitance between the gate and the drain, thereby improving device performance. Further, as Figure 1 As shown, in the trench, the top surface of the first conductive structure 130 and the bottom surface of the second conductive structure 140 are approximately flat surfaces. Figure 4a As shown, in the trench, the middle portion of the top surface of the first conductive structure 130 is convex outward, and the middle portion of the bottom surface of the second conductive structure 140 is concave inward to adapt to the convexity of the first conductive structure 130 .

[0070] In one embodiment, if Figure 4b As shown, within the trench, a first conductive structure 130 extends from the top to the bottom of the trench, and an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench. A second conductive structure 140 is formed within the oxide layer 120 on both sides of the first conductive structure 130. The first conductive structure 130 and the second conductive structure 140 are isolated by the oxide layer 120, and the depth of the first conductive structure 130 extending toward the bottom of the trench is greater than the depth of the second conductive structure 140 extending toward the bottom of the trench. In this embodiment, the second conductive structure 140 is disposed within the oxide layer 120 to increase the thickness of the oxide layer 120, thereby enhancing the withstand voltage of the device.

[0071] The present application also relates to a method for preparing a trench gate metal oxide semiconductor field effect transistor, such as Figure 5 As shown, the preparation method comprises the following steps:

[0072] Step S510: providing a semiconductor substrate and forming a drift region having a first conductivity type on the semiconductor substrate.

[0073] Step S520: opening a trench on the drift region, forming an oxide layer on the inner wall of the trench, and filling the trench with a first conductive structure and a second conductive structure isolated from each other, wherein the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure, and defining a portion of the first conductive structure whose depth exceeds the bottom depth of the second conductive structure as a field plate adjustment structure.

[0074] like Figure 6aAs shown, the drift region 100 having the first conductivity type is formed by doping the semiconductor substrate. Specifically, the epitaxial layer on the semiconductor substrate is doped to form the drift region 100 on the epitaxial layer.

[0075] Through photolithography and etching processes, a trench is formed in the drift region 100, and a filling structure is filled in the trench. Since the structures of the first conductive structure 130 and the second conductive structure 140 in the trench can have various forms, the steps of forming the first conductive structure 130 and the second conductive structure 140 in the trench can also be implemented in various ways. In one specific embodiment, step S520 may include the following steps:

[0076] Step S521: opening a trench on the drift region, and forming an oxide layer on the inner wall of the trench.

[0077] like Figure 6a As shown, an oxide layer 120 is formed on the inner wall of the trench. Specifically, the oxide layer 120 can be formed by thermal oxidation.

[0078] Step S522: filling the trench with a first conductive structure.

[0079] Step S523: etching the first conductive structure and the oxide layer at the top of the trench, and retaining the first conductive structure and the oxide layer at the bottom of the trench.

[0080] like Figure 6b As shown, the first conductive structure 130 is filled into the trench, which can be formed by a deposition process. The first conductive structure and the oxide layer at the top of the trench are etched, leaving the first conductive structure 130 at the bottom of the trench and the oxide layer 120 between the first conductive structure 130 and the trench sidewall.

[0081] Step S524 : forming an isolation structure in the trench, wherein the isolation structure covers the first conductive structure at the bottom of the trench but does not completely fill the trench.

[0082] like Figure 6c As shown, a layer of isolation structure 150 is deposited in the trench through a deposition process. The isolation structure 150 may be specifically silicon oxide. The isolation structure 150 covers the first conductive structure 130 and does not fill the trench.

[0083] Step S525: forming an oxide layer on the sidewall of the trench above the isolation structure and filling the trench with a second conductive structure.

[0084] like Figure 6dAs shown, an oxide layer is formed on the trench sidewalls above the isolation structure 150, and a second conductive structure 140 is filled in the trench. The second conductive structure 140 is isolated from the inner wall of the trench by the oxide layer 120, and the second conductive structure 140 is isolated from the first conductive structure 130 by the isolation structure 150. In the filling structure formed by steps S521 to S525 above, the first conductive structure 130 at the bottom of the trench serves as the field plate adjustment structure.

[0085] Step S530: doping the upper surface layer of the drift region to form a body region with a second conductivity type in contact with the side wall of the trench, wherein the depth of the body region is less than the depth of the trench; doping the upper surface layer of the body region to form a source region with a first conductivity type in contact with the side wall of the trench.

[0086] like Figure 6e As shown, the upper surface layer of the drift region 100 is doped to form a body region 110 of the second conductivity type in contact with the sidewalls of the trench. The depth of the body region 110 is less than the depth of the trench, that is, the bottom of the trench is still located in the drift region 100. The upper surface layer of the body region 110 is doped to form a source region 111 of the first conductivity type in contact with the sidewalls of the trench.

[0087] Step S540: forming a first doped region with a second conductivity type in the drift region, wherein the first doped region is connected to the body region, the first doped region is spaced apart from the trench, and the bottom depth of the first doped region exceeds the top depth of the field plate adjustment structure.

[0088] like Figure 6e and 6f As shown, in one embodiment, between step S530 and step S540, the process further includes forming an interlayer dielectric layer 200 on the source region 111 and the trench, and sequentially etching the interlayer dielectric layer 200, the source region 111, and the body region 110 on both sides of the trench to form a source contact hole. The source contact hole is spaced apart from the trench. In step S540, dopant ions of the second conductivity type are implanted into the drift region through the source contact hole to form a first doped region 160 in the drift region that contacts the body region 110. At this time, the projected area of the first doped region 160 is the same as the projected area of the source contact hole. In one embodiment, after the dopant ions of the second conductivity type are implanted through the source contact hole to form the first doped region 160 in the drift region 100, dopant ions of the second conductivity type are further implanted through the source contact hole to form a second doped region 112 on the surface of the body region.

[0089] Step S550: forming a source lead-out structure connected to the source region and the body region, and forming a gate lead-out structure connected to the second conductive structure.

[0090] like Figure 6h As shown, a source lead-out structure 310 connected to the source region 111 and the body region 110 is formed, and a gate lead-out structure (not shown) connected to the second conductive structure 140 is formed. In one embodiment, when a source contact hole is formed before step S550, the source lead-out structure 310 is formed by filling the source contact hole with a conductive material in step S550. In one embodiment, when the second doped region 112 is formed in the body region 110 through the source contact hole, the source lead-out structure 310 is formed by filling the source contact hole with a conductive material. The bottom of the source lead-out structure 310 is surrounded by the second doped region 112, which can reduce the contact resistance between the source lead-out structure 310 and the body region.

[0091] In the above embodiment, the first doped region 160 is formed in the drift region 100 by an implantation process at the source contact hole. In other embodiments, the drift region 100 is grown by an epitaxial growth process. The first doped region 160 is formed during the epitaxial growth process. Specifically, there are two methods:

[0092] First way:

[0093] epitaxially growing a first epitaxial layer on the semiconductor substrate;

[0094] doping the first epitaxial layer to form a first doped region having a second conductivity type;

[0095] A second epitaxial layer is continuously grown on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

[0096] like Figure 7a to Figure 7c As shown, a first epitaxial layer 101 is first epitaxially grown on a semiconductor substrate, and then a specific area of the first epitaxial layer 101 is doped with a second conductive type to form a first doped region 160 with a second conductive type. The second epitaxial layer 102 is further epitaxially grown on the first epitaxial layer 101 and the first doped region 160. The first epitaxial layer 101 and the second epitaxial layer 102 form the desired drift region 110. At this time, the first doped region 160 is formed inside the drift region 110.

[0097] Second way:

[0098] epitaxially growing a first epitaxial layer on the semiconductor substrate;

[0099] Opening a shallow trench on the first epitaxial layer, and epitaxially growing a first doped region of the second conductivity type in the shallow trench;

[0100] A second epitaxial layer is continuously grown on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

[0101] The difference between the second method and the first method is the different methods for forming the first doped region 160 in the first epitaxial layer 101. In the first method, the first doped region 160 is formed by directly doping a specific region of the first epitaxial layer 101, while in the second method, a shallow trench is first formed in the specific region, and then the first doped region 160 of the second conductivity type is epitaxially grown in the shallow trench. It should be noted that all of the above methods can form the first doped region, and the method can be flexibly selected according to specific conditions.

[0102] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A trench gate metal oxide semiconductor field effect transistor, characterized in that: include: a drift region having a first conductivity type and formed on a semiconductor substrate; a body region having a second conductivity type and formed on an upper surface layer of the drift region; a source region having a first conductivity type and formed on an upper surface layer of the body region; a trench, sequentially penetrating the source region and the body region and extending into the drift region; a filling structure comprising a first conductive structure and a second conductive structure filled in the trench and isolated from each other, and an oxide layer formed between the first conductive structure and the inner wall of the trench and between the second conductive structure and the inner wall of the trench, wherein the bottom depth of the first conductive structure exceeds the bottom depth of the second conductive structure, and a portion of the first conductive structure having a depth exceeding the bottom depth of the second conductive structure is defined as a field plate adjustment structure; a first doped region having a second conductivity type, formed in the drift region and in contact with a lower surface of the body region, the first doped region being spaced apart from the trench, and a bottom depth of the first doped region exceeding a top depth of the field plate adjustment structure; a source lead-out structure connected to the source region and the body region; as well as a gate lead-out structure connected to the second conductive structure; The sidewall of the first doped region includes a first portion extending downward from the bottom of the body region and parallel to the trench sidewall, and a second portion continuing to extend downward from the first portion and gradually tilting toward the interior of the first doped region. The longitudinal cross-section of the second portion is an inverted trapezoid or an inverted triangle, and the interface between the first portion and the second portion passes through the field plate adjustment structure.

2. The metal oxide semiconductor field effect transistor according to claim 1, wherein: The metal oxide semiconductor field effect transistor has a plurality of the first doping regions and is provided with a plurality of the trenches. Each trench is filled with the filling structure. The first doping regions and the trenches are alternately arranged along the trench width direction.

3. The metal oxide semiconductor field effect transistor according to claim 2, wherein: The cross section of the trench is in the shape of an elongated strip, and a plurality of the first doping regions are arranged side by side and spaced apart along the length direction of the trench between adjacent trenches.

4. The metal oxide semiconductor field effect transistor according to claim 1, wherein: Also includes: an interlayer dielectric layer formed on the top surfaces of the source region and the trench; The source lead-out structure penetrates the interlayer dielectric layer and the source region and extends into the body region to be connected to the source region and the body region respectively; The gate lead structure penetrates the interlayer dielectric layer and is connected to the second conductive structure.

5. The metal oxide semiconductor field effect transistor according to claim 1, wherein: A second doping region is formed in the body region, wherein the second doping region has a second conductivity type and a doping concentration of the second doping region is higher than that of the body region. The second doping region is located below the source region and is spaced apart from the trench. The source lead-out structure penetrates the source region and extends into the second doping region.

6. A method for preparing a trench gate metal oxide semiconductor field effect transistor, characterized in that: include: Providing a semiconductor substrate and forming a drift region having a first conductivity type on the semiconductor substrate; A trench is formed in the drift region, an oxide layer is formed on an inner wall of the trench, and a first conductive structure and a second conductive structure isolated from each other are filled in the trench, wherein the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure, and a portion of the first conductive structure whose depth exceeds the bottom depth of the second conductive structure is defined as a field plate adjustment structure; Doping the upper surface layer of the drift region to form a body region of the second conductivity type in contact with the sidewall of the trench, wherein the depth of the body region is less than the depth of the trench; doping the upper surface layer of the body region to form a source region of the first conductivity type in contact with the sidewall of the trench; A first doped region of a second conductivity type is formed in the drift region, the first doped region being in contact with a lower surface of the body region, the first doped region being spaced apart from the trench, the bottom depth of the first doped region exceeding the top depth of the field plate adjustment structure, the sidewall of the first doped region comprising a first portion extending downward from the bottom of the body region and parallel to the trench sidewall, and a second portion extending downward from the first portion and gradually tilting toward the interior of the first doped region, the longitudinal cross-section of the second portion being an inverted trapezoid or an inverted triangle, and the interface between the first portion and the second portion passing through the field plate adjustment structure; as well as A source lead-out structure connected to the source region and the body region is formed, and a gate lead-out structure connected to the second conductive structure is formed.

7. The preparation method according to claim 6, wherein After the step of doping the upper surface layer of the body region to form a first conductivity type source region in contact with the sidewall of the trench, the method further includes: forming an interlayer dielectric layer on the source region and the trench; etching the interlayer dielectric layer, the source region, and the body region in sequence to form a source contact hole penetrating the dielectric layer and the source region and extending to the body region; The forming of the first doped region in the drift region in contact with the lower surface of the body region comprises: injecting dopant ions of the second conductivity type into the drift region through the source contact hole to form the first doped region in contact with the lower surface of the body region in the drift region; The forming of the source lead-out structure connected to the source region and the body region includes: filling the source contact hole with a conductive material to form the source lead-out structure.

8. The preparation method according to claim 6, wherein forming a first doped region having a second conductivity type in the drift region, comprising: epitaxially growing a first epitaxial layer on the semiconductor substrate; doping the first epitaxial layer to form a first doped region having a second conductivity type; A second epitaxial layer is continuously grown on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

9. The preparation method according to claim 6, wherein forming a first doped region having a second conductivity type in the drift region, comprising: epitaxially growing a first epitaxial layer on the semiconductor substrate; Opening a shallow trench on the first epitaxial layer, and epitaxially growing a first doped region of the second conductivity type in the shallow trench; A second epitaxial layer is continuously grown on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

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