A gate-controlled avalanche fast-closing IGBT and its symmetrical structure

Abstract

The present invention discloses a gate-controlled avalanche fast closure IGBT, which comprises, from bottom to top, a collector metal, a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, an emitter metal, and a gate metal. The third epitaxial layer comprises a first doped region, a second doped region, and a third doped region. The first doped region originates from the upper surface of the third epitaxial layer and extends downward to the lower surface of the third epitaxial layer. The second doped region originates from the upper left corner of the third epitaxial layer and extends downward to the lower right into the third epitaxial layer, with a certain distance from the first doped region. The third doped region is located within the second doped region and has a certain distance from the left and right sides of the second doped region. The emitter metal is located above a portion of the second doped region and a portion of the third doped region. The gate metal is located above the third epitaxial layer between the second doped region and the first doped region. In a pulsed power system, the avalanche closure IGBT provided by the present invention can significantly shorten the pulse front compared to traditional IGBTs, thereby improving pulse source performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gate-controlled avalanche fast-closing IGBT and a symmetrical structure thereof. Background Art

[0002] With the advancement of technological research, pulsed power technology has gradually emerged in industrial production. Currently, pulsed power is widely used in a wide range of fields, including environmental protection, aerospace, biomedicine, resource extraction, military industry, and national defense. Pulsed power switches are the core of pulsed power technology. With the deepening of semiconductor theoretical research and the maturity of semiconductor manufacturing processes, semiconductor switches have occupied a key position in pulsed power switching. Semiconductor switches used in pulsed power technology are called semiconductor pulsed power devices.

[0003] Traditional semiconductor pulse power devices primarily include GTOs (Gate-Turn-Off Thyristors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors). Among them, IGBTs, as a mainstream high-power device, have been widely used in various fields.

[0004] The basic structure of traditional IGBT is as follows Figure 1 As shown, applying a voltage to the gate forms an inversion layer beneath it, which acts as a conductive channel to turn the device on. However, conventional IGBTs have a slow turn-on speed, and the collector current gradually increases as the inversion layer forms beneath the gate, limiting the rate of collector current rise. Applying such conventional IGBTs to pulsed power systems results in excessively long pulse leading edges, affecting the performance of the pulse source. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a gate-controlled avalanche fast closing IGBT and its symmetrical structure. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a gate-controlled avalanche fast closing IGBT, which comprises, from bottom to top, a collector metal, a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, an emitter metal, and a gate metal; wherein,

[0007] The third epitaxial layer is provided with a first doping region, a second doping region and a third doping region;

[0008] The first doped region starts from the upper surface of the third epitaxial layer and extends downward to the lower surface of the third epitaxial layer;

[0009] The second doped region starts at the upper left corner of the third epitaxial layer and extends downward to the lower right into the third epitaxial layer, and is spaced apart from the first doped region. Meanwhile, a portion of the third epitaxial layer without additional doping forms a first drift region.

[0010] The third doping region starts from the upper surface of the second doping region and extends downward into the second doping region, and has a certain distance from the left and right sides of the second doping region;

[0011] The emitter metal is located above a portion of the second doping region and a portion of the third doping region;

[0012] The gate metal is located above the third epitaxial layer between the second doping region and the first doping region, and a gate electrode and a gate dielectric layer are further provided between the gate metal and the third epitaxial layer.

[0013] In one embodiment of the present invention, the first epitaxial layer and the second epitaxial layer have the same doping type; the third epitaxial layer has the same doping type as the substrate and is heterotype doped with the second epitaxial layer.

[0014] In one embodiment of the present invention, the first doping region, the second doping region and the third epitaxial layer have the same doping type; and the third doping region and the second epitaxial layer have the same doping type.

[0015] In one embodiment of the present invention, both the first doping region and the third doping region are heavily doped regions.

[0016] In one embodiment of the present invention, the second epitaxial layer and the third epitaxial layer are lightly doped regions.

[0017] In one embodiment of the present invention, the gate is made of polysilicon.

[0018] In one embodiment of the present invention, the substrate is N+ doped, the first epitaxial layer is P doped, the second epitaxial layer is P- doped, the third epitaxial layer is N- doped, the first doped region is N+ doped, the second doped region is N doped, and the third doped region is P+ doped.

[0019] In the second aspect, the present invention also provides a symmetrical structure of a gate-controlled avalanche fast closure IGBT, comprising a gate-controlled avalanche fast closure IGBT provided by the above embodiment in which two first doping regions are adjacent and symmetrically arranged; wherein a gate dielectric layer, a gate electrode and a gate metal are sequentially arranged above the first doping regions.

[0020] Beneficial effects of the present invention:

[0021] The gate-controlled avalanche fast closure IGBT provided by the present invention forms a depletion region under the gate dielectric when subjected to forward pressure. When it gradually changes from a depletion state to an accumulation state, the device is in a cut-off state, and the collector current is reverse leakage with a very low value. When the device undergoes a reversible avalanche, a large amount of plasma formed instantly enables the device to be turned on quickly, and the collector current will rise rapidly. The collector current of a traditional IGBT will gradually increase with the formation of an inversion channel under the gate. This makes the collector current of the gate-controlled avalanche fast closure IGBT of the present invention rise much faster than that of a traditional IGBT. Replacing the traditional IGBT in a pulse power system with this device can significantly shorten the pulse front and improve the performance of the pulse source.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the basic structure of a traditional IGBT;

[0024] Figure 2 This is a schematic structural diagram of a gate-controlled avalanche fast-closing IGBT provided by an embodiment of the present invention;

[0025] Figure 3 1 is a schematic structural diagram of a gate-controlled avalanche fast closure IGBT with an N+ substrate provided by an embodiment of the present invention;

[0026] Figure 4 It is a schematic diagram of the symmetrical structure of a gate-controlled avalanche fast-closing IGBT provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0028] Example 1

[0029] See Figure 2 , Figure 2 : is a schematic structural diagram of a gate-controlled avalanche fast closure IGBT provided by an embodiment of the present invention, which includes, from top to bottom, a collector metal 1, a substrate 2, a first epitaxial layer 3, a second epitaxial layer 4, a third epitaxial layer 5, an emitter metal 6, and a gate metal 7; wherein,

[0030] The third epitaxial layer 5 is provided with a first doping region 51, a second doping region 52 and a third doping region 53;

[0031] The first doped region 51 starts from the upper surface of the third epitaxial layer 5 and extends downward to the lower surface of the third epitaxial layer 5;

[0032] The second doped region 52 starts from the upper left corner of the third epitaxial layer 5 and extends downward to the lower right into the third epitaxial layer 5 , and is spaced apart from the first doped region 51 . Meanwhile, a first drift region 54 is formed in a portion of the third epitaxial layer 5 that is not additionally doped.

[0033] The third doping region 53 starts from the upper surface of the second doping region 52 and extends downward into the second doping region 52 , and has a certain distance from the left and right sides of the second doping region 52 ;

[0034] The emitter metal 6 is located above a portion of the second doping region 52 and a portion of the third doping region 53;

[0035] The gate metal 7 is located above the third epitaxial layer 5 between the second doping region 52 and the first doping region 51 , and a gate 8 and a gate dielectric layer 9 are further provided between the gate metal 7 and the third epitaxial layer 5 .

[0036] Specifically, the first epitaxial layer 3 serves as the cutoff region of the device, and the second epitaxial layer 4 serves as the second drift region of the device; the first doping region 51 and the second doping region 52 are located inside the third epitaxial layer 5, so that the portion of the third epitaxial layer 5 without additional doping becomes the first drift region 54 of the device; the third doping region 53 is located in the second doping region 52, so that the rest of the second doping region 52 becomes the base region of the device.

[0037] Furthermore, the first epitaxial layer 3 and the second epitaxial layer 4 have the same doping type; the third epitaxial layer 5 has the same doping type as the substrate 2 and is heterotype-doped with the second epitaxial layer 4. The first doping region 51, the second doping region 52, and the third epitaxial layer 5 have the same doping type; and the third doping region 53 has the same doping type as the second epitaxial layer 4.

[0038] Furthermore, the first doping region 51 and the third doping region 53 are both heavily doped regions. The second epitaxial layer 4 and the third epitaxial layer 5 are lightly doped regions.

[0039] Generally, the substrate can be either N-type or P-type doped. Given that N-type substrates are predominant in practical applications, this embodiment preferably utilizes an N+ substrate to implement the device structure. The N+ substrate is made of a semiconductor material such as silicon or silicon carbide, and an ohmic contact is formed at the interface between the collector metal 1 and the substrate 2. The first epitaxial layer 3 is lightly P-type doped, the second epitaxial layer 4 is P-doped, and the third epitaxial layer 5 is N-doped. In this embodiment, the three epitaxial layers can be formed by homoepitaxial growth on the substrate.

[0040] Furthermore, the first doping region 51 is N+ doped, the second doping region 52 is N-type doped, and the third doping region 53 is P+ doped. The emitter metal 6 forms an ohmic contact with the interface between the second doping region 53 and the third doping region 53. The gate 8 is formed of polysilicon material.

[0041] It should be noted that the doping concentrations of the second epitaxial layer 4, the third epitaxial layer 5, the first doping region 51 and the second doping region 52 in the gate-controlled fast ionization transistor provided in this embodiment can be appropriately adjusted according to the device withstand voltage and the required turn-on gate voltage, and this embodiment does not make specific limitations.

[0042] The principle of the gate-controlled avalanche fast closure IGBT provided by this embodiment is described below by taking a gate-controlled avalanche fast closure IGBT with an N+ substrate as an example.

[0043] See Figure 3 , Figure 3 This is a schematic diagram of the structure of a gate-controlled avalanche fast closure IGBT with an N+ substrate provided by an embodiment of the present invention. The P-type first epitaxial layer 3, serving as the device's cutoff region, can be referred to as the P-type cutoff region, and the P- second epitaxial layer 4, serving as the device's second drift region, can also be referred to as the P- second drift region. The N+ first doped region 51, serving as the device's trigger region, is referred to as the N+ trigger region. The first drift region formed by the N+ first doped region 51 and the N-type second doped region 52 in the third epitaxial layer 5 is referred to as the N- first drift region. The portion of the N-type second doped region 52, excluding the P+ third doped region 53, is referred to as the N-type base region.

[0044] This gate-controlled avalanche fast-closing IGBT has three stable operating modes: reverse cutoff, forward cutoff, and forward closing. In general applications, it can switch between forward cutoff and forward closing. The specific operating process is described below with the collector metal grounded.

[0045] Process 1: No voltage is applied to the gate metal or it is grounded, a positive voltage is applied to the emitter metal, and the device is biased to a state close to static breakdown. This state can be called a critical breakdown state. The applied voltage is mainly borne by the N-type base region, the N-first drift region and the P-second drift region. At this time, the N-first drift region is in a depleted pressure state and the device is in a forward cutoff state.

[0046] Process 2: A positive voltage is applied to the gate metal, causing the N- first drift region beneath the gate dielectric layer to enter an accumulation state. The electrons used for accumulation here primarily come from the left-side N-type base region and the right-side N+ trigger region, due to their majority electrons and high doping concentrations, which have not been fully depleted. Once in the accumulation state, the voltage between the collector and emitter metals is directed to the region between the N+ trigger region and the P- second drift region. The applied voltage exceeds the maximum voltage that this region can withstand, causing reversible avalanche breakdown, generating plasma. Under the influence of the electric field, electrons in the plasma migrate toward the anode and holes toward the cathode, promoting the diffusion of holes from the P+ region into the N-type base region and electrons from the N+ substrate into the P-type cutoff region. Due to the latch-up effect, the device remains on, entering the forward closed state.

[0047] Process three: The gate metal stops applying positive voltage or directly applies negative voltage, and the N-first drift region under the gate dielectric layer returns to the depletion state from the accumulation state. The source of plasma generation is cut off. Since the N-type base region and the P+ region are short-circuited by the collector metal, the diffusion of holes in the P+ region to the N-type base region is weakened, the latch-up effect is suppressed, and the device will return to the forward cut-off state.

[0048] The gate-controlled avalanche fast-closing IGBT provided in this embodiment forms a depletion region beneath the gate dielectric when subjected to forward pressure. As this region gradually transitions from a depletion state to an accumulation state, the device is in the cutoff state, and the collector current exhibits reverse leakage and is very low. When the device undergoes a reversible avalanche, the large amount of plasma formed instantaneously enables the device to quickly conduct, causing the collector current to rise rapidly. In contrast, the collector current of a conventional IGBT gradually increases with the formation of an inversion channel beneath the gate. This results in a collector current rise rate much higher than that of a conventional IGBT in the gate-controlled avalanche fast-closing IGBT provided in this embodiment. Replacing conventional IGBTs in pulsed power systems with this device can significantly shorten the pulse front edge and improve pulse source performance.

[0049] Example 2

[0050] Based on the above embodiment 1, this embodiment provides a symmetrical structure of a gate-controlled avalanche fast closing IGBT. Figure 4 , Figure 4 This is a schematic diagram of the symmetrical structure of a gate-controlled avalanche fast closure IGBT provided by an embodiment of the present invention, which includes the gate-controlled avalanche fast closure IGBT provided by the above-mentioned embodiment 1 in which two first doping regions 51 are adjacent and symmetrically arranged; wherein a gate dielectric layer 9, a gate electrode 8 and a gate metal 7 are sequentially provided above the first doping regions 51.

[0051] It can be seen that the symmetrical structure of the gate-controlled avalanche fast closing IGBT provided in this embodiment is symmetrically formed by the gate-controlled avalanche fast closing IGBT provided in the above-mentioned embodiment 1, and a MOS structure is also formed above the first doping region. Therefore, this embodiment also has the advantages of the above-mentioned embodiment 1. Its specific working principle can be found in the above-mentioned embodiment 1 and will not be described in detail here.

[0052] Based on the above-mentioned embodiment 1, this embodiment enables both sides to be turned on or off simultaneously through a gate control, thereby increasing the current density during conduction and improving the chip utilization efficiency without bringing additional process complexity.

[0053] It should be noted that, in this embodiment, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0054] In addition, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact via another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or diagonally above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or diagonally below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0055] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0056] The above description further details the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be construed as being limited to these descriptions. A person skilled in the art would be able to make several simple deductions or substitutions without departing from the spirit of the present invention, and all of these should be considered to fall within the scope of protection of the present invention.

Claims

1. A gate-controlled avalanche fast closing IGBT, characterized in that: The structure includes, from bottom to top, a collector metal (1), a substrate (2), a first epitaxial layer (3), a second epitaxial layer (4), a third epitaxial layer (5), an emitter metal (6), and a gate metal (7); wherein, A first doping region (51), a second doping region (52) and a third doping region (53) are provided inside the third epitaxial layer (5); The first doping region (51) starts from the upper surface of the third epitaxial layer (5) and extends downward to the lower surface of the third epitaxial layer (5); The second doping region (52) starts at the upper left corner of the third epitaxial layer (5) and extends downward to the lower right into the interior of the third epitaxial layer (5), and is spaced apart from the first doping region (51). Meanwhile, a portion of the third epitaxial layer (5) without additional doping forms a first drift region (54); The third doping region (53) starts from the upper surface of the second doping region (52) and extends downward into the second doping region (52), and has a certain distance from the left and right sides of the second doping region (52); The emitter metal (6) is located above a portion of the second doping region (52) and a portion of the third doping region (53); The gate metal (7) is located above the third epitaxial layer (5) between the second doping region (52) and the first doping region (51), and a gate electrode (8) and a gate dielectric layer (9) are further provided between the gate metal (7) and the third epitaxial layer (5); The first epitaxial layer (3) and the second epitaxial layer (4) have the same doping type; the third epitaxial layer (5) has the same doping type as the substrate (2) and is heterotype doped with the second epitaxial layer (4); The first doping region (51), the second doping region (52) and the third epitaxial layer (5) have the same doping type; the third doping region (53) and the second epitaxial layer (4) have the same doping type; The first doping region (51) and the third doping region (53) are both heavily doped regions.

2. The gate-controlled avalanche fast closing IGBT according to claim 1, characterized in that: The second epitaxial layer (4) and the third epitaxial layer (5) are lightly doped regions.

3. The gate-controlled avalanche fast closing IGBT according to claim 1, characterized in that: The gate (8) is made of polysilicon.

4. The gate-controlled avalanche fast closing IGBT according to claim 1, characterized in that: The substrate (2) is N+ doped, the first epitaxial layer (3) is P doped, the second epitaxial layer (4) is P- doped, the third epitaxial layer (5) is N- doped, the first doping region (51) is N+ doped, the second doping region (52) is N doped, and the third doping region (53) is P+ doped.

5. A gate-controlled avalanche fast closing IGBT symmetrical structure, characterized in that: A gate-controlled avalanche fast closure IGBT according to any one of claims 1 to 4, comprising two first doping regions (51) adjacently and symmetrically arranged; wherein a gate dielectric layer (9), a gate electrode (8) and a gate metal (7) are sequentially arranged above the first doping regions (51).

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