FPGA-based LZSS bridge data compression parallel method, system, medium and device

Abstract

The invention discloses a parallel method, system, medium and device for LZSS bridge data compression based on FPGA, wherein the LZSS compression algorithm is input into a data acquisition subsystem and a monitoring center; the data acquisition subsystem reads N sensor data; and sends the N sensor data to N on-chip processing units for compression processing to obtain compressed data, and then outputs the compressed data to an off-chip DRAM through an on-chip buffer area, and provides an off-chip DRAM to transmit the compressed data to a monitoring center; the monitoring center reads the received N compressed data to the off-chip DRAM of the FPGA, and the FPGA cache reads the N compressed data in the off-chip DRAM and hands them over to N on-chip processing units for decompression processing to obtain N decompressed data; the N decompressed data are passed through the on-chip buffer area and then output to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism. The problem of long data compression time and low transmission efficiency is solved.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to a parallel method, system, medium and device for LZSS bridge data compression based on FPGA. Background Art

[0002] At present, many bridges built in the 1950s and 1960s are still in operation. Affected by the environment and the aging of the bridges themselves, various safety hazards of these "old bridges" that have been in operation for more than half a century have gradually been exposed. In order to ensure the normal operation of my country's highway and railway lines, it is very necessary to grasp the health status of bridges in a timely manner.

[0003] In recent years, with the rapid development of computer technology, sensor technology and communication technology, people have gradually designed and continuously improved bridge structure health monitoring systems, such as Figure 1 The figure shows the schematic diagram of the current mainstream bridge structure health monitoring system. The system deploys various sensors for monitoring different positions, types and monitoring items of the bridge to the corresponding positions of the bridge, and collects various real-time field data of the bridge through the data collector located at the bridge site. Then, the collected data is transmitted to the back-end data monitoring center through the public network via the data transmission subsystem. Finally, the health status, reliability, bearing capacity and durability of the bridge are evaluated by analyzing these data. The current advanced detection system can also predict the situation that will occur based on these data, report safety hazards in a timely manner, and prevent them before they happen.

[0004] Since the bridge monitoring system works 24 / 7, the long-term operation of a large number of sensors will generate massive amounts of data. Since the data acquisition subsystem is usually far away from the monitoring center and many bridges are located in complex terrain and cannot be reached by wired networks, a large amount of data to be transmitted from the data collector at the bridge site to the data monitoring center requires the use of a speed-limited wireless network, which will take a lot of time, thereby reducing transmission efficiency, throughput, and increasing transmission costs, which will have a negative impact on the entire bridge detection system. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a parallel method, system, medium and device for LZSS bridge data compression based on FPGA in view of the deficiencies in the above-mentioned prior art, so as to improve the transmission efficiency and increase the transmission throughput by reducing the amount of transmitted data.

[0006] The present invention adopts the following technical solutions:

[0007] The parallel method of LZSS bridge data compression based on FPGA includes the following steps:

[0008] S1. Using HLSC / C++ to implement the LZSS compression algorithm, a LZSS compression algorithm that can be burned into the processor is obtained;

[0009] S2. Use Vivado HLS to input the LZSS compression algorithm obtained in step S1 into the data acquisition subsystem and the monitoring center to obtain a data acquisition subsystem and a monitoring center with compression and decompression capabilities;

[0010] S3, inputting N sets of sensor data into the data acquisition subsystem obtained in step S2;

[0011] S4, the data acquisition subsystem reads the N copies of sensor data in step S3; and sends the N copies of sensor data to N on-chip processing units for compression processing to obtain compressed data, and then outputs the compressed data to the off-chip DRAM through the on-chip buffer area, and provides the off-chip DRAM to transmit the compressed data to the monitoring center;

[0012] S5, when all the N compressed data in step S4 are transmitted to the monitoring center; the monitoring center reads the received N compressed data into the off-chip DRAM, and the processor cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data;

[0013] S6. After the decompression processing in step S5, the N decompressed data are passed through the on-chip buffer area and then output to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism.

[0014] Specifically, in step S1, in the LZSS compression algorithm, a minimum matching length M is set, and when more than or equal to M characters are matched during the iteration process, B and L are output, otherwise the first character of the forward buffer is output and one character is moved forward.

[0015] Furthermore, the LZSS compression algorithm is burned into the FPGA.

[0016] Furthermore, the minimum matching length M is 2.

[0017] Furthermore, the LZSS compression algorithm is specifically as follows:

[0018] The input string is AAAABBBAAAA, and no string matching the dictionary is found in the forward buffer. B is output, the sliding window becomes AAAB, and the forward buffer becomes BBAAAA.

[0019] Only B matching the dictionary is found in the buffer, and the length of B is less than the minimum matching length. B is output, the sliding window becomes AABB, and the forward buffer becomes BAAAA;

[0020] The string BAA matching the dictionary is found in the buffer, and 2,3 is output, which means to go back 2 characters, copy 3 characters, the sliding window becomes BBAA, and the forward buffer becomes AA;

[0021] The string AA that matches the dictionary is found in the buffer, and 1,2 is output, which means moving back one character, copying two characters, and the buffer becomes empty. The final compression result is AAAABB(2,3)(1,2).

[0022] Specifically, in step S4, the compressed data in the off-chip DRAM is transmitted from the data acquisition subsystem to the monitoring center via the public network of the data transmission subsystem.

[0023] Specifically, in step S4, N on-chip processing units execute the compression process in parallel.

[0024] Another technical solution of the present invention is a FPGA-based LZSS bridge data compression parallel system, comprising:

[0025] The algorithm module uses HLSC / C++ to implement the LZSS compression algorithm to obtain the LZSS compression algorithm that can be burned into the FPGA;

[0026] The input module uses Vivado HLS to input the LZSS compression algorithm obtained by the algorithm module into the data acquisition subsystem and the monitoring center, thereby obtaining a data acquisition subsystem and a monitoring center with compression and decompression capabilities;

[0027] Input module, inputs N copies of sensor data into the data acquisition subsystem obtained by the input module;

[0028] Compression module, the data acquisition subsystem reads N copies of sensor data from the input module; and sends the N copies of sensor data to N on-chip processing units for compression processing to obtain compressed data, and then outputs the compressed data to the off-chip DRAM through the on-chip buffer area, and provides the off-chip DRAM to transmit the compressed data to the monitoring center;

[0029] Decompression module: When all N compressed data of the compression module are transmitted to the monitoring center, the monitoring center reads the received N compressed data into the off-chip DRAM of the FPGA, and the FPGA cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data.

[0030] The parallel module passes the N decompressed data after decompression by the decompression module through the on-chip cache area and then outputs them to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism.

[0031] Another technical solution of the present invention is a computer-readable storage medium storing one or more programs, wherein the one or more programs include instructions, and when the instructions are executed by a computing device, the computing device executes any one of the FPGA-based LZSS bridge data compression parallel methods.

[0032] Another technical solution of the present invention is a computing device, comprising:

[0033] One or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing any one of the methods in the FPGA-based LZSS bridge data compression parallel method.

[0034] Compared with the prior art, the present invention has at least the following beneficial effects:

[0035] The present invention discloses an FPGA-based LZSS bridge data compression parallel method. In a bridge structure health monitoring system, the inherent parallelism of FPGA is utilized so that a data acquisition subsystem can compress multiple copies of sensor data transmitted by sensors at the same time. Similarly, a monitoring center can decompress multiple copies of compressed data transmitted by the data acquisition subsystem at the same time, thereby greatly improving the transmission and communication efficiency of the entire system.

[0036] Furthermore, a minimum matching length M is set in the LZSS compression algorithm. When M characters or more are matched during the iteration process, (B, L) is output. Otherwise, the first character of the forward buffer is output and one character is moved forward. In this way, when there is a matching string between the forward buffer and the sliding window, no matter how long the matching string is, it can be represented by only two characters, namely (B, L), thus achieving the purpose of compression.

[0037] Furthermore, FPGA contains a large number of logic operation units, which can process a large amount of data at the same time. When analyzing the LZSS data compression process, a large number of logic and operations are performed to compare whether the data matches when performing dictionary matching. FPGA is good at performing logical operations. Therefore, using FPGA for data compression is very feasible and efficient.

[0038] Furthermore, the minimum match length M is set to 2. This is because if M=1, it means that the minimum match length is 1, that is, as long as there is a character in the forward buffer that matches a character in the sliding window, two characters (B, L) will be output, and the number of characters output is greater than the number of original characters, which has a negative impact on the final compression effect. If the minimum match length is set to be greater than 2, the compressible character string may be missed, which has a negative impact on the final compression effect. Therefore, it is more reasonable to set the minimum match length M to 2.

[0039] Furthermore, the specific steps of the LZSS compression algorithm describe a detailed process of the LZSS compression algorithm, through which the input data is compressed.

[0040] Furthermore, the compressed data in the off-chip DRAM is transmitted from the data acquisition subsystem to the monitoring center via the public network of the data transmission subsystem. This process transmits the compressed data to the monitoring center so that the monitoring center can decompress the compressed data and restore the previous data, thereby enabling the monitoring center to process and analyze the data.

[0041] Furthermore, N on-chip processing units perform compression in parallel, so that N copies of data can be processed at the same time instead of one copy of data, and the compression efficiency will be improved by nearly N times. Compression processing is an important part of data transmission. A significant increase in compression rate will greatly improve transmission efficiency.

[0042] In summary, the present invention solves the problem of long data compression time and low transmission efficiency.

[0043] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a schematic diagram of the bridge structure health monitoring system;

[0045] Figure 2 This is the bridge temperature data graph;

[0046] Figure 3 The basic structure diagram of CPU and FPGA, where (a) is CPU and (b) is FPGA;

[0047] Figure 4 This is a graph of partial temperature data of the bridge on a certain day;

[0048] Figure 5 This is a diagram of the FPGA-based LZSS bridge data compression parallel computing architecture. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] In the description of the present invention, it should be understood that the terms “include” and “comprises” indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0051] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0052] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0053] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0054] The present invention provides a parallel method for LZSS bridge data compression based on FPGA, comprising the following steps:

[0055] S1. Use HLSC / C++ to implement the LZSS compression algorithm and obtain the LZSS compression algorithm that can be burned into FPGA;

[0056] FPGA is used as the processor chip of the system; it is a programmable gate array. FPGA has been widely used in various fields where science and technology has spread due to its flexible design, short cycle, low cost, rich logic resources, high parallelism, strong reconfigurability and other advantages. Traditional bridge data acquisition subsystems mostly use CPU as computing power to compress sensor data. Its basic structure is as follows Figure 3As shown in (a), the FPGA contains a large number of configurable logic units (CLBs) and some IO modules (IOBs). Its basic structure is as follows Figure 3 As shown in (b), CLB is the basic computing unit for processing data in FPGA. Each CLB can execute different data at the same time. Therefore, FPGA has extremely high flexibility and parallelism. The IOB module is used to communicate with external devices. Since the CPU processor adopts the von Neumann structure, the calculation process is serial and the parallelism is poor.

[0057] Analyze the characteristics of the bridge data acquisition subsystem receiving data from the sensor subsystem, such as Figure 4 As shown in the figure, part of the temperature data generated by a bridge in a certain day. WD represents temperature, the number after WD represents the sensor number, and the number after the underline represents the time when the temperature data is generated. It can be seen that there will be a lot of data from the sensor subsystem at the same time.

[0058] The efficiency of using CPU for compression will be reduced, while FPGA contains a large number of logic operation units, which can process a large amount of data at the same time. In addition, when analyzing the LZSS data compression process, a large number of logic and operations will be performed to compare whether the data matches when performing dictionary matching. FPGA is good at logical operations. Therefore, using FPGA for data compression is very feasible and efficient. The FPGA-based LZSS compression parallel method can improve the computing efficiency of the data acquisition subsystem and reduce the bandwidth used for transmitting data.

[0059] See also Figure 2 , compress and pre-process the data collected by the data collection center, Figure 2 This is part of the temperature data of the Sutong Bridge on January 12, 2018. It is not difficult to find that the data structure is monotonous and the repetition rate is extremely high, so it is necessary and effective to use data compression technology to pre-process the data.

[0060] The LZSS algorithm is a dictionary-based compression algorithm, which is an enhancement and improvement of the LZ77 algorithm. The LZ77 algorithm maintains a forward buffer and a sliding window. For example, the forward buffer contains the character sequence (A, B, C), then the phrases in the buffer are {(A), (A, B), (A, B, C)}, and the sliding window contains the phrase (A, B, C), then the phrases in the dictionary are {(A), (A, B), (A, B, C), (B, C), (B), (C)}; then the data in the forward buffer is compared with the phrases in the dictionary, and if there is a match, the offset B and the match length L are output; the LZSS algorithm improves the phenomenon that LZ77 may output a null pointer and characters that may match in the next iteration although they do not match in this iteration. The LZSS algorithm sets the minimum match length M. If there are more than or equal to M characters matched during the iteration, (B, L) is output, otherwise the first character in the forward buffer is output and one character is moved forward.

[0061] by Figure 2 Taking the second column of the bridge temperature data shown in the figure as an example (this column is the most difficult column to process in the temperature data shown in the figure because it contains different data), the specific process of the LZSS algorithm is shown in Table 1, where A represents the data 0.587800 and B represents the data 0.551769.

[0062] In the first step, the input string is AAAABBBAAAA. No matching string is found in the forward buffer and the dictionary, so B is output, the sliding window becomes AAAB, and the forward buffer becomes BBAAAA.

[0063] In the second step, since only B matching the dictionary is found in the buffer and its length is less than the minimum matching length, B is directly output, the sliding window becomes AABB, and the forward buffer becomes BAAAA;

[0064] In the third step, the string BAA matching the dictionary is found in the buffer, so (2,3) is output, which means backing up 2 characters, copying 3 characters, the sliding window becomes BBAA, and the forward buffer becomes AA;

[0065] In the fourth step, the string AA that matches the dictionary is found in the buffer, so (1,2) is output, which means going back one character and copying two characters. At this point, the buffer becomes empty, and the final compression result is AAAABB(2,3)(1,2).

[0066] Table 1 LZSS algorithm flow

[0067]

[0068]

[0069] S2. Use Vivado HLS to input the LZSS compression algorithm that can be burned into the FPGA in step S1 into the data acquisition subsystem and the monitoring center to obtain a data acquisition subsystem and a monitoring center with compression and decompression capabilities;

[0070] S3, reading N copies of the sensor data transmitted from the sensor subsystem into the off-chip DRAM of the FPGA in the data acquisition subsystem in step S2;

[0071] S4, the controller in the data acquisition subsystem controls the on-chip cache to read the sensor data in the off-chip DRAM of the FPGA in step S3 or step S6, sends the N copies of sensor data in the cache to the N on-chip processing units for compression processing to obtain compressed data, and then passes the compressed data after compression processing through the on-chip cache area and is output by the controller to the off-chip DRAM, and the compressed data in the off-chip DRAM is transmitted from the data acquisition subsystem to the monitoring center through the public network of the data transmission subsystem;

[0072] S5, read the next N compressed data into the off-chip DRAM of the data acquisition subsystem FPGA, repeat the above steps until all the sensor data transmitted from the sensor subsystem are processed and transmitted to the monitoring center, and the monitoring center receives the compressed data transmitted to the monitoring center in step S5 after entering the LZSS compression algorithm, reads the received N compressed data into the off-chip DRAM of the FPGA of the monitoring center, and the FPGA cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data;

[0073] S6. After the decompression processing in step S5, the N decompressed data are passed through the on-chip cache area and then output to the off-chip DRAM by the controller. The above operation is repeated until all the received compressed data are processed. At this point, data compression parallelism is achieved, that is, N data can be processed simultaneously at the same time relying on the parallelism of FPGA.

[0074] See also Figure 5 The FPGA-based LZSS bridge data compression parallel computing architecture is as follows:

[0075] First, the above LZSS algorithm is designed using Vivado HLS and burned into the FPGA chip according to the FPGA chip model. Assume that N data are received from the bridge at the same time and input into the off-chip DRAM of the FPGA. Then the controller transfers the input data from the off-chip DRAM to the on-chip cache of the FPGA. After the transmission is completed, the on-chip processing unit (Processingunit) is divided into N small on-chip processing units according to the number of input data N, realizing N-way parallel execution.

[0076] The data acquisition subsystem includes an algorithm module, an entry module, an input module, a compression module and a parallel module. The monitoring center includes an algorithm module, an entry module, an input module, a decompression module and a parallel module. The algorithm module enters the entry module, the data enters the input module, and then is processed in the compression or decompression module. At the same time, the data processed at the previous moment enters the parallel module.

[0077] In another embodiment of the present invention, a FPGA-based LZSS bridge data compression parallel system is provided, which can be used to implement the above-mentioned FPGA-based LZSS bridge data compression parallel method. Specifically, the FPGA-based LZSS bridge data compression parallel system includes an algorithm module, an entry module, an input module, a compression module, a decompression module and a parallel module.

[0078] Among them, the algorithm module uses HLSC / C++ to implement the LZSS compression algorithm to obtain the LZSS compression algorithm that can be burned into FPGA;

[0079] The input module uses Vivado HLS to input the LZSS compression algorithm obtained by the algorithm module into the data acquisition subsystem and the monitoring center, thereby obtaining a data acquisition subsystem and a monitoring center with compression and decompression capabilities;

[0080] Input module, inputs N copies of sensor data into the data acquisition subsystem obtained by the input module;

[0081] Compression module, the data acquisition subsystem reads N copies of sensor data from the input module; and sends the N copies of sensor data to N on-chip processing units for compression processing to obtain compressed data, and then outputs the compressed data to the off-chip DRAM through the on-chip buffer area, and provides the off-chip DRAM to transmit the compressed data to the monitoring center;

[0082] Decompression module: When all N compressed data of the compression module are transmitted to the monitoring center, the monitoring center reads the received N compressed data into the off-chip DRAM of the FPGA, and the FPGA cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data.

[0083] The parallel module passes the N decompressed data after decompression by the decompression module through the on-chip cache area and then outputs them to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism.

[0084] In another embodiment of the present invention, a terminal device is provided, the terminal device includes a processor and a memory, the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., which is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, and is specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding function; the processor described in the embodiment of the present invention can be used for the operation of the LZSS bridge data compression parallel method based on FPGA, including:

[0085] The LZSS compression algorithm is implemented by HLSC / C++ to obtain the LZSS compression algorithm that can be burned into the FPGA; the LZSS compression algorithm is entered into the data acquisition subsystem and the monitoring center by using VivadoHLS, and the data acquisition subsystem and the monitoring center with compression and decompression capabilities are obtained; N sensor data are input into the data acquisition subsystem; the data acquisition subsystem reads the N sensor data; and the N sensor data are sent to the N on-chip processing units for compression processing to obtain compressed data, and then the compressed data is output to the off-chip DRAM through the on-chip buffer area, and the off-chip DRAM is provided to transmit the compressed data to the monitoring center; when all the N compressed data are transmitted to the monitoring center; the monitoring center reads the received N compressed data into the off-chip DRAM of the FPGA, and the FPGA cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data; the N decompressed data are passed through the on-chip buffer area and then output to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism.

[0086] In another embodiment of the present invention, the present invention further provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a terminal device for storing programs and data. It can be understood that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and the extended storage medium supported by the terminal device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory, or a non-volatile memory (non-volatile memory), such as at least one disk storage.

[0087] The processor may load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the FPGA-based LZSS bridge data compression parallel method in the above embodiment; the processor may load and execute the following steps:

[0088] The LZSS compression algorithm is implemented by HLSC / C++ to obtain the LZSS compression algorithm that can be burned into the FPGA; the LZSS compression algorithm is entered into the data acquisition subsystem and the monitoring center by using VivadoHLS, and the data acquisition subsystem and the monitoring center with compression and decompression capabilities are obtained; N sensor data are input into the data acquisition subsystem; the data acquisition subsystem reads the N sensor data; and the N sensor data are sent to the N on-chip processing units for compression processing to obtain compressed data, and then the compressed data is output to the off-chip DRAM through the on-chip buffer area, and the off-chip DRAM is provided to transmit the compressed data to the monitoring center; when all the N compressed data are transmitted to the monitoring center; the monitoring center reads the received N compressed data into the off-chip DRAM of the FPGA, and the FPGA cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data; the N decompressed data are passed through the on-chip buffer area and then output to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism.

[0089] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0090] The pseudo code of the method of the present invention is as follows:

[0091]

[0092]

[0093] Wherein, step 1 burns the LZSS compression algorithm into the FPGA;

[0094] Steps 2 to 12 complete the data reading, data compression, and data writing operations in the data acquisition subsystem. Due to the parallelism of FPGA, the compression process can be executed in parallel, shortening the compression time.

[0095] Step 13 transmits the compressed data from the data acquisition subsystem to the monitoring center.

[0096] Steps 14 to 24 complete the data reading, data decompression, and data writing operations of the monitoring center. Similarly, the decompression process can be executed in parallel.

[0097] Step 25 transfers the data to other subsystems for processing.

[0098] In summary, the present invention provides an FPGA-based LZSS bridge data compression parallel method and system. Aiming at the problem that a large amount of data to be transmitted on the bridge will be transmitted from the data acquisition center to the data monitoring center, which will reduce transmission efficiency, reduce throughput, and increase transmission costs, the present invention proposes an FPGA-based LZSS bridge data compression parallel method, formulates a computing architecture for parallel computing using this method, and solves the problems of long data compression time and low transmission efficiency.

[0099] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0100] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0101] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0103] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. The parallel method of LZSS bridge data compression based on FPGA is characterized by: The following steps are involved: S1. Use HLSC / C++ to implement the LZSS compression algorithm to obtain the LZSS compression algorithm that can be burned into the processor. In the LZSS compression algorithm, the minimum matching length M is set. When there are characters greater than or equal to M matched during the iteration process, B, L are output. Otherwise, the first character of the forward buffer is output and one character is moved forward. The specific LZSS compression algorithm is: The input string is AAAABBBAAAA, and no string matching the dictionary is found in the forward buffer. B is output, the sliding window becomes AAAB, and the forward buffer becomes BBAAAA. Only B matching the dictionary is found in the buffer, and the length of B is less than the minimum matching length. B is output, the sliding window becomes AABB, and the forward buffer becomes BAAAA; The string BAA matching the dictionary is found in the buffer, and 2,3 is output, which means to go back 2 characters, copy 3 characters, the sliding window becomes BBAA, and the forward buffer becomes AA; The string AA matching the dictionary is found in the buffer, and 1,2 is output, which means moving back one character, copying two characters, and the buffer becomes empty. The final compression result is AAAABB(2,3)(1,2); S2. Use Vivado HLS to input the LZSS compression algorithm obtained in step S1 into the data acquisition subsystem and the monitoring center to obtain a data acquisition subsystem and a monitoring center with compression and decompression capabilities; S3, inputting N sets of sensor data into the data acquisition subsystem obtained in step S2; S4, the data acquisition subsystem reads N sets of sensor data from step S3; The N sensor data are sent to N on-chip processing units for compression processing to obtain compressed data, and then the compressed data is output to the off-chip DRAM through the on-chip buffer area, and the off-chip DRAM is provided to transmit the compressed data to the monitoring center; S5, when all the N compressed data in step S4 are transmitted to the monitoring center; the monitoring center reads the received N compressed data into the off-chip DRAM, and the processor cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data; S6. After the decompression processing in step S5, the N decompressed data are passed through the on-chip buffer area and then output to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism.

2. The FPGA-based LZSS bridge data compression parallel method according to claim 1 is characterized in that: In step S1, the LZSS compression algorithm is burned into the FPGA.

3. The FPGA-based LZSS bridge data compression parallel method according to claim 1 is characterized in that: In step S1, the minimum matching length M is 2.

4. The FPGA-based LZSS bridge data compression parallel method according to claim 1 is characterized in that: In step S4, the compressed data in the off-chip DRAM is transmitted from the data acquisition subsystem to the monitoring center via the public network of the data transmission subsystem.

5. The FPGA-based LZSS bridge data compression parallel method according to claim 1 is characterized in that: In step S4, N on-chip processing units execute the compression process in parallel.

6. An FPGA-based LZSS bridge data compression parallel system, characterized in that: include: The algorithm module uses HLSC / C++ to implement the LZSS compression algorithm to obtain the LZSS compression algorithm that can be burned into the FPGA. In the LZSS compression algorithm, the minimum matching length M is set. When there are characters greater than or equal to M matched during the iteration process, B, L are output. Otherwise, the first character of the forward buffer is output and one character is moved forward. The specific LZSS compression algorithm is: The input string is AAAABBBAAAA, and no string matching the dictionary is found in the forward buffer. B is output, the sliding window becomes AAAB, and the forward buffer becomes BBAAAA. Only B matching the dictionary is found in the buffer, and the length of B is less than the minimum matching length. B is output, the sliding window becomes AABB, and the forward buffer becomes BAAAA; The string BAA matching the dictionary is found in the buffer, and 2,3 is output, which means to go back 2 characters, copy 3 characters, the sliding window becomes BBAA, and the forward buffer becomes AA; The string AA matching the dictionary is found in the buffer, and 1,2 is output, which means moving back one character, copying two characters, and the buffer becomes empty. The final compression result is AAAABB(2,3)(1,2); The input module uses Vivado HLS to input the LZSS compression algorithm obtained by the algorithm module into the data acquisition subsystem and the monitoring center, thereby obtaining a data acquisition subsystem and a monitoring center with compression and decompression capabilities; Input module, inputs N copies of sensor data into the data acquisition subsystem obtained by the input module; Compression module, the data acquisition subsystem reads N copies of sensor data from the input module; The N sensor data are sent to N on-chip processing units for compression processing to obtain compressed data, and then the compressed data is output to the off-chip DRAM through the on-chip buffer area, and the off-chip DRAM is provided to transmit the compressed data to the monitoring center; Decompression module: When all N compressed data of the compression module are transmitted to the monitoring center, the monitoring center reads the received N compressed data into the off-chip DRAM of the FPGA, and the FPGA cache reads the N compressed data in the off-chip DRAM and hands them over to the N on-chip processing units for decompression processing to obtain N decompressed data. The parallel module passes the N decompressed data after decompression by the decompression module through the on-chip cache area and then outputs them to the off-chip DRAM until all the received compressed data are processed, thereby realizing data compression parallelism.

7. A computer-readable storage medium storing one or more programs, characterized in that: The one or more programs include instructions which, when executed by a computing device, cause the computing device to perform any one of the methods according to claims 1 to 5 .

8. A computing device, characterized in that include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing any one of the methods according to claims 1 to 5.

Images