Manufacturing method

Abstract

A manufacturing method comprises: forming a mask (10) of amorphous material on a crystalline surface of a substrate (2), the mask having an opening pattern, the opening pattern defining an area of ​​an active region, one or more components of one or more active devices are to be formed in the area of ​​the active region, the mask also defining an inactive region, the active device is not formed in the inactive region; and forming a deposited material (4) through the mask by an epitaxial growth process. Thus, the deposited material is formed in the openings of the active region. The opening pattern through the mask also includes one or more storage regions (8) formed in the inactive region, each of the storage regions being connected to at least one of the regions in the active region through the opening pattern in the mask, and the deposited material is formed in the storage region as part of the epitaxial growth.

Description

Background Art

[0001] Topological quantum computing is based on the phenomenon that in regions where semiconductors are coupled to superconductors, non-Abelian anyons in the form of "Majorana zero modes" (MZMs) can form. A non-Abelian anyon is a quasiparticle, meaning not a particle itself but an excitation in an electron liquid that behaves at least partially like a particle. An MZM is a specific bound state of such a quasiparticle. Under certain conditions, these states can form near the semiconductor-superconductor interface in a nanowire formed by a section of semiconductor coated with a superconductor. When an MZM is induced in a nanowire, it is said to be in a "topological state." To produce this, a magnetic field, usually applied externally, is required, and the nanowire needs to be cooled to a temperature that induces superconducting behavior in the superconducting material. It can also involve gating a portion of the nanowire with an electrostatic potential.

[0002] By forming a network of such nanowires and inducing topological states in portions of the network, it is possible to create quantum bits (qubits) that can be manipulated for the purposes of quantum computing. A quantum bit, or qubit, is an element on which a measurement with two possible outcomes can be performed, but which at any given time (when not being measured) can actually be in a quantum superposition of two states corresponding to different outcomes.

[0003] Structures of semiconductors such as nanowire networks can be formed on substrates by epitaxy. Epitaxy is a known deposition technique that involves growing one crystalline material on another crystalline material (in this case, a semiconductor). The first material acts as a seed crystal for the growth of a second material on the first material. The growth is performed selectively, for example by forming a patterned mask on a layer of the first material (e.g., a semiconductor substrate) and growing the deposited material (e.g., another semiconductor) in the exposed areas left by the mask. In this case, the process may also be referred to as selective area growth (SAG). Example techniques for epitaxial deposition itself include, for example, electron beam physical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition, and molecular beam epitaxy.

[0004] In addition to nanowires, epitaxy can also be used to grow other structures for quantum computing devices, spintronic devices, and classical electronic devices. Summary of the invention

[0005] One problem with epitaxial growth processes such as SAG is that they have a tendency to form growth irregularities. It would be desirable to control the formation of such growth irregularities, thereby increasing the yield of the manufacturing process.

[0006] The inventors have identified the following. The probability per unit area of ​​a growth irregularity first forming at any location within a continuous portion of an opening in a mask is approximately equal. However, once a growth irregularity forms at one point within the continuous portion, another irregularity tends not to form within the same portion. The reason for this is believed to be that the irregularity forms near the starting point of the first growth.

[0007] In order to exploit this phenomenon, the present invention provides a manufacturing method that includes one or more artificial "storage areas" in a portion of the mask covering the non-active area (i.e., the area where no active devices are formed). The storage area is connected to the opening pattern via the openings in the mask, and the opening pattern defines one or more components of one or more devices in the active area. This increases the chance that growth will start outside the active area, and therefore growth irregularities will form outside the active area. Preferably, the total area of ​​the (multiple) storage areas is larger than the total area of ​​the openings in the active area to which the (multiple) storage areas are connected. Therefore, there is a higher chance that growth will originate from one of the storage areas, and therefore growth irregularities will form in one of the storage areas. The larger the storage area, the greater the chance.

[0008] In an example application, the component(s) defined in the active region may include the semiconductor core(s) of one or more nanowires of a quantum device.

[0009] In embodiments, the material in the storage region may also be used for another purpose that is less sensitive to the presence of growth irregularities, such as forming a classical electrical contact with the nanowires. Alternatively, the storage region may have no other function than being a container for growth irregularities.

[0010] This summary is provided to introduce a set of concepts in a simplified form, which will be further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is also not limited to implementations that solve any or all of the disadvantages noted herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To assist in understanding the embodiments of the present disclosure and to show how these embodiments may be implemented, reference is made, by way of example only, to the accompanying drawings, in which:

[0012] Figure 1 (i) to (iii) schematically illustrate a method of depositing a material,

[0013] Figure 2 is a schematic side view of a nanowire,

[0014] Figure 3(a)-Figure 3(b) is a top-down image of an example structure formed by epitaxial growth, and

[0015] Figure 4(a)-Figure 4(b) Here are some further top-down images of the structure formed by epitaxial growth. DETAILED DESCRIPTION

[0016] In the case of epitaxial techniques such as selective area growth (SAG) by molecular beam epitaxy (MBE), there are specific growth modes that present challenges with growth non-uniformities that occur randomly inside the mask openings. For typical device sizes, each device will have only one confined non-uniform region. If the non-uniform region occurs in the so-called active region of the device, the non-uniform region may have an adverse effect on the device performance. To alleviate this problem, the present invention discloses modifying the mask design by adding storage regions to the non-active portion of the device to reduce the probability of growth non-uniformity within the active region of the device. Growth non-uniformities are more likely to occur inside the storage regions rather than in the active region of the device (due to the larger area of ​​the storage regions). Therefore, the disclosed technology can improve the manufacturing yield of devices through epitaxial growth, such as significantly improving the yield of nanoscale devices and / or devices with complex shapes.

[0017] In addition, the storage regions can be shaped to provide additional functionality, such as forming electrical contacts or Landauer transport storage regions. Where the storage regions are used to form electrical contacts, an additional advantage of the storage regions is that they can reduce contact resistance with the deposited semiconductor due to the increased contact area.

[0018] Figure 1 The process of depositing a deposition material 4 on a substrate 2 is schematically shown. The process starts with a substrate 2 comprising at least one wafer. Although the term is not always used consistently in the art, for the purposes of the present invention, "wafer" herein refers to the base layer, while "substrate" refers to the wafer and any additional layers that may have been added to the wafer prior to that point in the manufacturing process. Thus, as Figure 1 The substrate 2 shown at the starting point of the method may comprise only a wafer, or a wafer plus one or more previously deposited layers formed on the wafer.

[0019] On another point of terminology, please note that "on", "top", etc., as used herein, do not necessarily mean relative to gravity, but are to be understood in the sense of the processing side, i.e., the side on which deposition is currently being performed (e.g., material may be deposited upwards, downwards, or sideways relative to gravity, or indeed at any angle). In the case of deposition through mask 10, the layer formed on substrate 2 means the layer between substrate 2 and the source of the deposited material. Terms such as "below", "bottom layer", or similar should also be interpreted interchangeably.

[0020] In step (i), the method starts with a substrate 2 comprising at least one wafer. Figure 1 Although not shown in FIG. 1 , it is also possible to form complex layers on or over the wafer, such as a pseudo-metamorphic buffer stack. Such stacks are well known in the art and include layers of different materials where the material properties gradually differ from those of the wafer to the material properties of the material to be grown on top of the wafer. This enables a better matching of the crystal properties.

[0021] In step (ii), a patterned mask 10 is formed on the top surface of the substrate 2. The mask comprises a pattern of openings, at least some of which are continuous with each other. These openings define different components or elements of the device to be manufactured.

[0022] The amorphous mask 10 may be patterned in any suitable manner. For example, in an embodiment, the mask material may initially be formed as a uniform, continuous layer over the entire top surface of the substrate 2 (e.g., by chemical deposition), and then subsequently patterned by selectively removing the mask material from the desired areas, such as by etching or photolithography. As another example, the mask material 10 may be selectively deposited on the substrate 2 using a template that prevents the mask material 10 from being deposited in the desired areas. As another alternative, the patterned mask 10 may be formed elsewhere and mechanically transferred to the substrate 2.

[0023] The mask 10 is formed of an amorphous material, i.e., without a regular crystalline structure. In an embodiment, preferably, it is also a dielectric or other insulator. For example, the mask material may be an oxide such as silicon oxide (SiOx). Amorphous materials cannot sustain epitaxial growth. That is, they inhibit growth in the region deposited on the substrate, while growth can proceed on the crystalline substrate 2 with the mask open.

[0024] At least the upper surface of the substrate 2 is formed of a crystalline material. For example, the substrate 2 may be a semiconductor, such as any III-V semiconductor, such as indium phosphide (InP), gallium antimonide (GaSb) or gallium arsenide (GaAs).

[0025] In step (iii), a deposition material 4 is deposited onto the upper surface of the substrate 2 through the mask 10 by an epitaxial growth technique. Thus, the deposition material 4 grows in the openings of the mask 10, on the exposed portions of the substrate 2. The deposition material 4 is also crystalline. For example, this can also be a semiconductor, for example any III-V semiconductor such as indium arsenide (InAs), gallium antimonide (GaSb) or gallium arsenide (GaAs). Preferably, it is a different material from the surface of the substrate 2 being processed.

[0026] The growth method is an epitaxial growth method such as selective area growth (SAG). Epitaxy refers to the technique of growing a second crystal on a first crystal using the first crystal as a seed crystal. SAG refers to the local growth of semiconductor in exposed areas of the substrate, and the growth conditions are selected (or "adjusted") to prevent such growth from occurring on the amorphous mask itself. For example, this can be based on chemical beam epitaxy (CBE), molecular beam epitaxy (MBE), or metal-organic chemical vapor deposition (MOCVD). In the context of semiconductors, SAG can refer to a type of epitaxial semiconductor growth (also known as selective area epitaxy) in which a patterned amorphous mask is used to define the intended structure of the semiconductor material to be grown (a form of lithography). In SAG, the process is adjusted so that semiconductor growth occurs only on areas of the substrate that are not covered by the amorphous mask 10, and not on the amorphous mask itself. This is different from other deposition processes, such as uniform deposition (epitaxial or otherwise) when no mask is used, in which the material is deposited uniformly across the surface regardless of its material composition. SAG can be performed in high vacuum or ultra-high vacuum and involves adjustments to achieve the desired selective growth.

[0027] In an embodiment, the growth method for depositing the deposition material 4 (e.g., semiconductor) in the openings of the mask 10 is a specific type of selective area growth called "metal seeding" SAG. In this specific method, in order to form a compound semiconductor such as indium antimonide InSb, the following sequence is used: 1) selectively depositing a first element of the alloy (e.g., In), and 2) supplying a second element of the alloy (e.g., Sb) to convert the deposited first element into a compound (e.g., InSb). Doing this in this non-concurrent manner allows different conditions to be used for each element, which otherwise would not be selectively deposited if performed concurrently. This enables alloy growth in which selective conditions do not overlap between elements. However, the disadvantage of this process is that it increases the likelihood of forming the above-mentioned irregularities. The present disclosure provides a way to solve this problem.

[0028] In an optional additional step (not shown), one or more uniform or patterned layers of additional materials such as conductive materials (e.g., superconducting materials) may be grown on at least a portion of the nanowire network. For example, a patterned layer of conductive or superconducting material may be grown using a particle beam. Here, a superconducting material refers to a material that exhibits superconducting properties under at least certain conditions. An example of such a material is aluminum (Al). Alternatively, the superconductor material 112 may be niobium (Nb), titanium nitride (TiN), or any other s-wave superconductor. In an embodiment, superconductor growth may also be performed by epitaxial growth or by another means.

[0029] like Figure 2As shown, in an example application, the described process can be used to form one or more semiconductor-superconductor nanowire structures. Figure 2 A side view of an example nanowire 3 is schematically shown, but it will be appreciated that a network of two or more such nanowires may be formed. The (or each) nanowire 3 comprises a semiconductor 4 (extending to) a length of at least partially coated with a coating of superconducting material 6. Figure 2 The semiconductor core 4 may be formed by the epitaxial growth technique disclosed herein. In an embodiment, the semiconductor 4 of the nanowire 3 may include InAs, InSb or GaAs, and the upper surface of the substrate 2 may include InP, GaSb or GaAs. The mask may include SiOx. The superconductor 6 may include Al, Nb or TiN. The superconductor 6 may be formed by the epitaxial growth technique disclosed herein or any known conventional deposition technique (such as conventional SAG or other epitaxial growth).

[0030] At least a portion of the superconductor layer 6 is deposited on top of the semiconductor 4 of the nanowire 3 , such that this portion of the superconductor 6 is in direct contact with the semiconductor 4 of the nanowire 3 .

[0031] In one possible technique, the angle of the beam depositing the superconducting material 6 can be substantially parallel to the z-direction (the direction perpendicular to the plane of the substrate) so that substantially all exposed surfaces of the amorphous mask 10 and the semiconductor material 4 are covered with superconductivity. However, as shown in the figure, in another example, the particle beam is incident at a non-zero angle of incidence relative to the z-direction. As a result of this non-zero deposition angle, the core of the semiconductor 4 of the nanowire 3 is only partially covered by the superconductor layer 6, so that one side thereof is not coated by the superconductor 6. This leaves a "side gate" region for gating the nanowire using an electrostatic potential. Alternatively, gating can be achieved by other means, such as leaving exposed windows in the horizontal pattern of the superconductor 6.

[0032] It should also be noted that the same material deposited in the same deposition step as that used for the superconductor 6 of the nanowire 3 may also optionally be used to form other elements, such as classical electrical contacts. And / or one or more further steps (not shown) may be used to form other elements, such as classical electrical contacts and vias for connecting the nanowire 3 to other parts of the overall device or to the outside world.

[0033] Each of the semiconductor and superconductor growth stages can be performed in a vacuum chamber, preferably in the same chamber or chambers connected by vacuum tunnels, without breaking the vacuum between stages. The stages can be performed under high vacuum or ultra-high vacuum conditions, which can be maintained between stages.

[0034] In an embodiment, the substrate 2, mask 10 and nanowire network 3 can all be combined in a final product, such as a quantum circuit or quantum computer, without transferring the nanowires 3 from the substrate 2 or removing the mask 10. Applications of the disclosed technology include topologically protected quantum computing circuits that include nanowire networks formed using such hybrid semiconductor and superconductor regions.

[0035] As described above, the nanowire 3 can be used to produce Majorana-based topological qubits, which exploit the formation of superconducting islands, some portions of which are topological (T) and some portions of which are non-topological (e.g., conventional s-waves (S)). The SAG technique can provide a high degree of control over the shape of the resulting device and is therefore useful in producing components for scalable topological quantum computing. In an example embodiment, one or more Majorana zero modes (MZMs) can be induced in at least one nanowire of the nanowire network by cooling the superconductor 6 to a superconducting temperature, applying a magnetic field to the device, and typically also gating the nanowire 3 using an electrostatic potential. This is known per se in the art.

[0036] However, the manufacture of such a device can be problematic. This is illustrated by way of example in Figures 3(a) and 3(b).

[0037] FIG. 3( a ) shows a top-down scanning electron microscope (SEM) image of an example nanowire network at a stage after deposition of semiconductor 4 into openings in mask 10 by SAG, but before coating with superconductor 6 .

[0038] As can be seen in the image, the SAG process has a tendency to form growth irregularities 9. Within a given continuous structure defined by the openings in the mask 10, the growth irregularities 9 can appear randomly anywhere within the entire area defined by the openings. If this irregularity 9 falls within the active functional area of ​​the device being fabricated, the device may not function properly or at all (for example, in this case, it will not be able to be used as a nanowire network to form an MZM and operate as a qubit). Other similar devices can be formed on the same substrate 2 (same chip) and still be used, but despite this, the damaged device will result in a reduced yield of useful devices on the chip. Another example image of a growth irregularity 9 is shown in Figure 3(b).

[0039] An image of an example structure designed to address this problem, according to an embodiment of the present disclosure, is shown in FIG. 4( a ).

[0040] Not all regions of the deposited semiconductor 4 play a role in generating quantum effects that are manipulated for quantum computing purposes, such as to form qubits. Regions where quantum effects occur have the highest requirements for crystal quality. These regions form the active regions 5 of the device. In other words, the quantum effects involved in quantum computing devices are typically confined to certain regions within the nanowire network, such as at specific junctions of the network. The active (or operating) region 5 of the nanowire network refers to any region where these effects are arranged to occur for the purpose of being used as a quantum computing device. Note that it is not necessary to use the entire body of the nanowire for an active device (where the active device includes (multiple) portions of the nanowire in which the MZM will be formed). Instead, the region surrounding the active region 5 of the device forms a non-active region 7. The non-active (non-operating) region 7 refers to a region where the effect is not expected to occur, or a region that is not arranged for quantum computing purposes. These regions may be completely inactive, or may include components for providing supporting functions, such as providing classical electrical contacts to the device.

[0041] In order to address the problem of growth irregularities 9, it is disclosed herein that one or more storage regions 8 are formed in a mask pattern in a non-active region 7 around the device being fabricated. When a deposition material 4 (in this case a semiconductor) is deposited through an opening in a mask 10 by an epitaxial growth method, it not only fills the area defining the device components in the active region 5 (in this case a network of nanowires), but also fills the area of ​​the one or more storage regions 8. As described above, the epitaxial growth method can be, for example, a selective area growth (SAG) process, such as metal seeding SAG. For each of the one or more storage regions 8, the opening defining that opening in the mask 10 is continuous with the (multiple) openings defining at least one component of the device in the active region 5. Preferably, the area of ​​the one or more storage regions 8 and the area of ​​the one or more components of the one or more devices in the active region 5 are all continuous with each other, i.e., form an overall continuous area defined by a set of continuous (i.e., connected) openings through the mask 10.

[0042] The disclosed structure has the effect of increasing the chance of growth irregularities 9 being formed in the non-active region 7 and reducing the chance of them being formed in the active region 5. In epitaxial growth methods such as metal seeding SAG or other SAG techniques, then within any given continuous portion formed in the opening of the mask 10, growth typically starts from a single starting point within that portion. In addition, the growth mechanism is such that the region from which growth originates is typically irregular and cannot be used for active quantum devices such as nanowires (or at least it will be detrimental to device performance). That is, growth irregularities 9 occur where growth begins. There is no way to control where growth starts per se. The starting point, and thus the growth irregularity 9, will appear at a random position within any given continuous extension formed in the opening of the mask 10, with an approximately uniform probability per unit area. However, once growth starts at that point, there will typically not be another growth irregularity 9 in the same continuous portion of the mask pattern. Therefore, by forming relatively large storage regions 8 in the non-active region 7, there is a relatively high chance that growth irregularities 9 will be formed in one of the storage regions rather than in the region of the device itself. Therefore, the chance of a device being damaged by growth irregularities 9 can be reduced, thereby improving the yield of devices on a given substrate 2.

[0043] The larger the storage area, the greater the chance that growth irregularities will form in the storage area rather than in the active part of the device. However, for another reason, in an embodiment, an upper limit can also be set on the size of the storage area. This is determined by the finite diffusion length of surface atoms. If the storage area is too large, and the growth originates from inside it, it is possible that no growth occurs in the active area of ​​the mask because it is too far away from the starting point of growth (the distance is greater than the diffusion length of the atoms). In general, this distance does not exceed tens of microns.

[0044] In the example shown in Figure 4A, the device includes a nanowire network defined by a set of openings in a mask 10, which openings take the form of a set of intersecting channels or grooves in the mask, defining areas where semiconductor 4 will be grown to form the cores of the nanowires 3. Therefore, the channels defining the nanowires are continuous with each other because they intersect each other. In addition, the mask 10 includes two storage areas 8, each storage area 8 is arranged at a respective end of one of the channels and is continuous with the respective end of the channel (i.e., the gap or hole through the mask 10 is uninterrupted between the storage area 8 and at least a corresponding one of the channels or other such openings defining at least one active component of the device (in this case, one of the channels defining a portion of the nanowire network)).

[0045] FIG4B shows another example. Here, only one storage region 8 is formed at the end of one channel or leg of the nanowire network. This can still reduce the chance of growth irregularities 9 falling outside the active region 5, at least to some extent. However, as a secondary effect, the inventors have empirically observed that an asymmetric set of storage regions (e.g., only one storage region) can lead to another form of (but less severe) irregularities in the structure of the formed shape. This is marked with reference numeral 11 in FIG4B. This form of irregularity is not necessarily fatal to the device, but may affect quality or reliability. Therefore, the asymmetric case, although not excluded, may not be as preferred as the symmetrical case shown in FIG4A.

[0046] In further embodiments, storage regions 8 may even be formed at the end of more than two legs of the nanowire network, or even on each leg. Thus, in the case of the nanowire network shown in Figures 4A and 4B, there may be up to 6 storage regions 8.

[0047] In some embodiments, storage area 8 may be a completely non-functional element, used only to curb the formation of growth irregularities 9. However, in alternative embodiments, one or more storage areas 8 may also be arranged to have one or more additional supporting functions. For example, the material formed in one or more storage areas 8 may be used to form electrical contacts between the nanowire network and one or more other components on the same chip and / or to the outside of the chip. If, as is conventionally the case, a metal contact is simply placed at the top of one leg of the nanowire network, the contact area will be very small. However, if a metal contact is formed with material 4 in one of the storage areas 8, it will have a much higher contact area. Due to the increased contact area, this will reduce the contact resistance between the metal contact and the semiconductor.

[0048] As another example, one or more storage regions 8 can be used to create Landauer transport storage regions. These storage regions are much larger than nanowires and can have a special tapered shape. This allows one to use simplified equations to describe their electrical behavior and to interpret electrical results more directly. Conductors in quantum systems are designed to have as little loss as possible. On the other hand, electrical contacts are required to bring the electron bath into thermal equilibrium so that the electrochemical potential becomes well-defined. This balance requires losses. Therefore, quantum conductors have opposite requirements compared to the electrical contacts required to measure quantum conductors. This conflict is resolved by the concept of a "Landauer storage region". For quantum conductors defined in SAG, a Landauer storage region can be achieved by smoothly widening the size from a narrow region to a quantum conductor with a size longer than the inelastic mean free path (which is tens of microns at low temperatures).

[0049] It should be understood that the above-described embodiments have been described by way of example only.

[0050] For example, the applicability of the disclosed techniques is not limited to forming nanowire networks for forming MZM-based quantum computing devices. More generally, the disclosed techniques may be used to reduce the chance of growth irregularities forming in the active region where any quantum or spintronic effects are to be used in other quantum computing or quantum sensing devices, or in spintronic devices such as spintronic sensing or storage devices; or even to reduce the chance of growth irregularities in the active region of one or more active components of one or more classical electronic devices to be formed. The disclosed techniques may be used in any SAG or other epitaxial growth process, any of which may suffer from problems with growth irregularities. The disclosed techniques may be used to deposit any material that is capable of being epitaxially deposited onto any crystalline surface that is subject to epitaxial growth by any amorphous mask that prevents or inhibits epitaxial growth.

[0051] Therefore, more generally, according to one aspect disclosed herein, a manufacturing method is provided, comprising providing: a substrate having a crystalline surface; a mask of amorphous material formed on the surface of the substrate, the mask having an opening pattern passing through the mask, the mask defining an area of ​​an active region, one or more components of one or more active devices being to be formed in the area of ​​the active region, the mask also defining a non-active region, the active device not being formed in the non-active region; and forming a deposited material through the mask through an epitaxial growth process, so that the deposited material is formed in the openings of the active region to form the one or more components of the one or more active devices; wherein the opening pattern through the mask also includes one or more storage regions formed in the non-active region, each of the one or more storage regions being connected to at least one region in the area of ​​the active region through the opening pattern in the mask, and as part of the epitaxial growth, the deposited material is formed in the one or more storage regions.

[0052] In an embodiment, the total area of ​​the active region may be less than the total area of ​​the one or more storage regions.

[0053] In an embodiment, the epitaxial growth process may include a selective area growth (SAG) process.

[0054] In an embodiment, the SAG process may include a metal seeding SAG process.

[0055] In an embodiment, the one or more devices may comprise one or more quantum devices arranged to use one or more quantum effects occurring in the active region in order to be operable as a quantum device.

[0056] In an embodiment, the one or more quantum devices may include one or more quantum computing devices arranged to use one or more quantum effects occurring in an active region in order to be operable as a quantum computing device. For example, in an embodiment, the one or more quantum devices may include one or more qubits.

[0057] In other examples, one or more devices may alternatively or additionally include one or more quantum sensing devices, one or more spin electronic devices, and / or one or more active classical electronic devices.

[0058] In an embodiment, the deposited material formed in at least one of the memory regions may be arranged to be in electrical contact with at least one of the active devices.

[0059] This provides an optional additional benefit in that it reduces contact resistance. Alternatively, the contacts may be formed directly with the active device(s), separate from the storage region. In this case no reduced resistivity of the contacts is obtained, but the storage region still benefits the yield of such devices.

[0060] In an embodiment, the deposited material may include a semiconductor. In some such embodiments, the deposited material may include a III-V semiconductor. For example, the deposited material may include InAs, InSb, or GaAs, or a combination thereof.

[0061] In an embodiment, the method may further include forming at least one additional conductive material on the deposited material after the epitaxial growth.

[0062] In embodiments, the additional material may include a metal. In some such embodiments, the additional material may include a superconducting material.

[0063] In an embodiment, at least one of the active devices takes the form of a quantum computing device, the quantum computing device comprising at least one nanowire for forming a Majorana zero mode MZM in the nanowire; the deposited material comprises a semiconductor, and one or more components are formed from the deposited material, the one or more components comprising a semiconductor core of at least one nanowire; and the method further comprises forming a coating of superconducting material on at least a portion of the semiconductor core.

[0064] In an embodiment, the superconducting material may include Al, Nb or TiN.

[0065] According to another aspect disclosed herein, a method of operating the at least one device is provided, comprising cooling the device to a temperature at which the superconducting material exhibits superconductivity, applying a magnetic field to the device, and gating at least one nanowire with an electrostatic potential to induce an MZM.

[0066] In an embodiment, at least one of the storage areas may be arranged to form a Landauer transport storage area when filled with deposition material.

[0067] In an embodiment, the substrate may include a semiconductor. In some such embodiments, the substrate may include a III-V semiconductor. For example, the substrate may include InP, GAS, or GaSb, or a combination thereof.

[0068] Alternatively, the substrate may include an insulator.

[0069] In an embodiment, the amorphous material of the mask may include a dielectric. For example, the dielectric may include SiOx.

[0070] According to another aspect disclosed herein, a device may be provided, comprising: a substrate having a crystalline surface; a mask of amorphous material formed on the surface of the substrate, the mask having an opening pattern passing through the mask, the mask defining an area of ​​an active region, one or more components of one or more active devices being to be formed in the area of ​​the active region, the mask also defining a non-active region, the active device not being formed in the non-active region; and a deposited material formed in the opening of the mask in the active region, thereby forming the one or more components of the one or more active devices; wherein the opening pattern passing through the mask also includes one or more storage regions formed in the non-active region, each of the one or more storage regions being connected to at least one of the regions in the active region through the opening pattern in the mask, and the deposited material is also formed in the one or more storage regions.

[0071] In embodiments, the device may also include features resulting from any of the manufacturing steps disclosed herein.

[0072] After the disclosure is given herein, other variations or use cases of the disclosed technology will be apparent to those skilled in the art. The scope of the disclosure is not limited by the described embodiments, but only by the appended claims.

Claims

1. A manufacturing method, include: providing a substrate having a crystalline surface; forming a mask of an amorphous material on the surface of the substrate, the mask having a pattern of openings therethrough, the mask defining an active region in which one or more components of one or more active devices are to be formed, and further defining an inactive region in which no active device is to be formed; as well as forming a deposited material through the mask by an epitaxial growth process so that the deposited material is formed in the opening of the active region to form the one or more components of the one or more active devices; The opening pattern through the mask also includes one or more storage areas formed in the non-active area, each of the one or more storage areas is connected to at least one of the areas in the active area through the opening pattern in the mask, and as part of the epitaxial growth, the deposited material is formed in the one or more storage areas. 2 . The method of claim 1 , wherein the epitaxial growth process comprises a selective area growth (SAG) process. The method of claim 2 , wherein the SAG process comprises a metal seeding SAG process.

4. A method according to any one of claims 1 to 3, wherein the one or more active devices comprise one or more quantum devices arranged to use one or more quantum effects occurring in the active region in order to be operable as a quantum device.

5. The method of any one of claims 1-3, wherein the deposited material formed in at least one of the storage areas is arranged to be in electrical contact with at least one of the active devices.

6. The method of any one of claims 1-3, wherein the deposited material comprises a semiconductor. The method of claim 6 , wherein the deposited material comprises a III-V semiconductor.

8. The method of any one of claims 1-3, further comprising forming at least one additional conductive material on the deposited material after the epitaxial growth.

9. The method of claim 8, wherein the at least one additional conductive material comprises a metal.

10. The method of claim 8, wherein the at least one additional electrically conductive material comprises a superconducting material.

11. A method according to any one of claims 1-3, wherein at least one of the active devices takes the form of a quantum computing device, the quantum computing device comprising at least one nanowire for forming a Majorana zero mode in the nanowire; the deposited material comprises a semiconductor, and the one or more components are formed from the deposited material, the one or more components comprising a semiconductor core of the at least one nanowire; and the method further comprises forming a coating of superconducting material on at least a portion of the semiconductor core.

12. The method of any one of claims 1-3, wherein the substrate comprises a semiconductor. The method of claim 12 , wherein the substrate comprises a III-V semiconductor.

14. The method of any one of claims 1-3, wherein the amorphous material of the mask comprises a dielectric.

15. A device, include: a substrate having a crystalline surface; a mask of an amorphous material formed on the surface of the substrate, the mask having a pattern of openings therethrough, the mask defining an active region in which one or more components of one or more active devices are to be formed, and further defining an inactive region in which no active device is to be formed; as well as depositing material formed in the openings of the mask in the active regions to form the one or more components of the one or more active devices; The opening pattern passing through the mask also includes one or more storage areas formed in the non-active area, each of the one or more storage areas is connected to at least one of the areas in the active area through the opening pattern in the mask, and the deposited material is also formed in the one or more storage areas.

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