Voltage regulator with multi-level multi-phase buck architecture

Abstract

Regulators having a multi-stage, multi-phase architecture are disclosed. The circuit includes a two-stage buck converter and an N-stage buck converter each coupled to an output node, where N is an integer value of three or greater. During operation, the two-stage buck converter provides one of two possible voltages to a first inductor. During operation, the N-stage buck converter provides one of N voltages to a second inductor. The first inductor and the second inductor each convert the received voltage to a current, which is provided to a common output node. A control circuit controls the activation of transistors in each of the two-stage buck converter and the N-stage buck converter in such a way that the voltage on the output node is maintained at a desired level.

Description

background Technical Field

[0002] This disclosure relates to electronic circuits, and more specifically to voltage regulator circuits. Background Technology

[0004] Voltage regulators are commonly used in various circuits to provide a desired voltage to a specific circuit. Therefore, a variety of voltage regulator circuits are available to meet diverse applications. Linear regulators are used in many different applications where the available supply voltage exceeds the suitable value for the circuit being powered. Another type of voltage regulator is the switching-mode regulator, more commonly called a switching power supply, or alternatively a DC-DC converter. Switching power supplies can be further subdivided into two categories: buck converters and boost converters. A buck converter gradually decreases the input voltage from its power supply to its load while gradually increasing the current. A boost converter gradually increases the input voltage from its power supply to its load while gradually decreasing the current.

[0005] A basic switching power supply consists of a switch, an energy storage element (such as an inductor), and a diode. Operation in a basic switching power supply includes an on state (when the switch is closed) and an off state (when the switch is open). During the on state, the energy storage element begins to store energy. For example, when the energy storage element is an inductor, the current increases, and in response, the inductor generates an opposite voltage across its terminals. During the off state, the switch is open, and the inductor becomes a current source. Over time, the changing voltage of the switching power supply is averaged to a substantially DC voltage. Summary of the Invention

[0006] A voltage regulator with a multi-stage, multi-phase architecture is disclosed. In one embodiment, the circuit includes a two-stage buck converter and an N-stage buck converter, each coupled to an output node, where N is an integer value of three or greater. During operation, the two-stage buck converter supplies one of two possible voltages to a first inductor. During operation, the N-stage buck converter supplies one of N voltages to a second inductor. The first and second inductors each convert the received voltage into a current, which is supplied to a common output node. Control circuitry controls the activation of transistors in each of the two-stage and N-stage buck converters in such a manner that the voltage at the output node is maintained at a desired level.

[0007] In various implementations, the circuit may include multiple instances of a two-stage buck converter, an N-stage buck converter, or both. Some implementations may also include one or more M-stage buck converters coupled to the output node, where M is an integer value of three or greater that is different from N. Attached Figure Description

[0008] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0009] Figure 1 This is a block diagram of one embodiment of a hybrid buck converter with two-stage buck converters and N-stage buck converters.

[0010] Figure 2 This is a schematic diagram of one implementation of a hybrid converter with a two-stage buck converter and an N-stage buck converter.

[0011] Figure 3 The operating timing diagrams of various implementation schemes of the buck converter are shown.

[0012] Figure 4 This is a block diagram of another implementation of the hybrid buck converter.

[0013] Figure 5 This is a block diagram of another implementation of the hybrid buck converter.

[0014] Figure 6 This is a flowchart illustrating the operation of one embodiment of a hybrid buck converter.

[0015] Figure 7 This is a block diagram of one implementation of an exemplary system.

[0016] While the embodiments disclosed herein are susceptible to various modifications and alternatives, specific embodiments of the invention are illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the scope of the claims to the specific forms disclosed. Rather, this application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure of this application as defined by the appended claims.

[0017] This disclosure includes references to “one implementation,” “a particular implementation,” “some implementations,” “various implementations,” or “implementation.” The phrases “in one implementation,” “in a particular implementation,” “in some implementations,” “in various implementations,” or “in an implementation” do not necessarily refer to the same implementation. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0018] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured to” perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured to” perform a task even if the structure is not currently being operated. “An integration distribution circuit configured to distribute integration to multiple processor cores” is intended to cover, for example, an integrated circuit having circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Therefore, an entity described or stated as “configured to” perform a task refers to a physical thing used to perform that task, such as a device, circuit, memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things.

[0019] The term “configured as” is not intended to mean “configurable as”. For example, an unprogrammed FPGA is not considered “configured as” to perform a particular function, although it may be “configurable as” to perform that function after programming.

[0020] The formulation structure in the appended claims is "configured" to perform one or more tasks explicitly intended for the claim elements. No Referring to 35 U.S.SC § 112(f). Therefore, none of the claims in this application are intended to be interpreted as having a device-plus-function element. If the applicant wishes to invoke 112(f) during the application process, it will use the structure "device for [performing a function]" to formulate the elements of the claims.

[0021] As used herein, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0022] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that other factors may influence or otherwise trigger the effect. That is, an effect may respond solely to these factors, or it may respond to the specified factors as well as other unspecified factors. Consider the phrase "execute A in response to B." This phrase specifies that B is the factor that triggers the performance of A. This phrase does not exclude the possibility that execution of A may also respond to certain other factors, such as C. This phrase is also intended to cover implementations where A is executed solely in response to B.

[0023] As used herein, the terms “first,” “second,” etc., serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise stated. For example, in a register file with eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, rather than, for example, only logical registers 0 and 1.

[0024] When used in the claims, the term "or" is used as an inclusive "or" rather than an exclusive "or". For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, and any combination thereof.

[0025] In the following description, numerous specific details are set forth to provide a thorough understanding of the described embodiments. However, those skilled in the art will recognize that aspects of the disclosed embodiments can be practiced without these specific details. In some instances, well-known circuits, structures, signals, computer program instructions, and techniques have not been shown in detail so as not to obscure the disclosed embodiments. Detailed Implementation

[0026] This disclosure relates to a hybrid buck converter comprising multiphase and multistage elements. A conventional multiphase buck converter is a two-stage buck converter that drives two different voltage levels in an inductor depending on the state of the switches therein. Multiple instances of two-stage buck converters can be implemented in the same regulator to form a multiphase buck converter. These converters can provide flat efficiency across the entire current range of the converter. Multistage buck converters with three or more output levels may be more efficient at low currents. Various embodiments of a hybrid regulator having both a two-stage buck converter and an N-stage buck converter (where N is an integer value of three or greater) are disclosed herein. Embodiments in which N-stage and M-stage (where M is an integer value of three or greater and not equal to N) combined with the two-stage disclosure are also possible and contemplated.

[0027] Figure 1This is a block diagram of one embodiment of a hybrid voltage regulator including a two-stage buck converter and an N-stage buck converter. In the illustrated embodiment, regulator 100 includes a two-stage buck converter 102 and an N-stage buck converter 104 (where N is an integer value of three or greater) each coupled to an output node, at which the output voltage Vout is delivered. Both the two-stage buck converter 102 and the N-stage buck converter 104 are coupled to receive a supply voltage Vdd and are also coupled to a ground node (which may also be referred to as Vss). Regulator 100 also includes a control circuit 106 coupled to control the switching operation of each of the buck converters in the illustrated embodiment. A feedback circuit 108 is coupled between the output voltage node and the control circuit 106 and is configured to generate a feedback signal Vfb. Regulator 100 also includes a capacitor VC coupled between the output node and ground. The voltage generated by regulator 100 is provided to a load circuit 121, which can be virtually any type of circuit that can be powered by the regulated supply voltage.

[0028] The two-stage buck converter 102 in the illustrated embodiment is configured to generate one of two different voltages based on the state of the switches therein and supply these voltages to inductors. The inductors integrate the voltages into a current supplied to the output node. An N-stage buck converter 104 generates one of N (e.g., three) different voltages and supplies these voltages to the corresponding inductors therein. Similar to the two-stage buck converter 102, the inductors therein convert these voltages into corresponding currents supplied to the output node. These currents are summed at the output node and then converted back to voltage through a capacitor VC.

[0029] Feedback circuit 108 is configured to convert the output voltage Vout into a feedback signal Vfb. Various circuit topologies can be used to implement feedback circuit 108. An exemplary topology includes a resistor divider and an error amplifier. The error amplifier can receive a voltage from the resistor divider at one input and a reference voltage at the other input. The reference voltage can correspond to the desired output voltage Vout. The error amplifier can output a feedback signal Vfb, which can indicate the difference between the desired output voltage and the actual output voltage.

[0030] The control circuit 106 in the illustrated embodiment can control the switching of individual transistors in the two-stage buck converter 102 and the N-stage buck converter 104 based on received feedback signals. More specifically, the duty cycle of the on / off time of each transistor can be controlled in this way to adjust the output voltage Vout and maintain it at a desired value. The switching of transistors in each buck converter can be synchronized by a clock signal Clk provided to the control circuit 106. The control circuit 106 can be implemented using various types of circuitry, including (but not limited to) sequential logic circuits, combinational logic circuits, analog circuits, and mixed-signal circuits.

[0031] Figure 2 This is a schematic diagram of one embodiment of a hybrid converter having a two-stage buck converter and an N-stage buck converter. In the illustrated embodiment, the N-stage buck converter is a three-stage buck converter 204, but this disclosure is not limited to this order of magnitude.

[0032] The two-stage buck converter 102 in the illustrated embodiment includes a pull-up transistor P1 and a pull-down transistor N1. The pull-up transistor P1 includes a drain terminal coupled to node lx1 and a source terminal coupled to the voltage supply node Vdd. The pull-down transistor N1 includes a drain terminal coupled to node lx1 and a source terminal coupled to ground (or Vss). The gate terminal of P1 (node ​​pg) is coupled to the output of optional buffer B1, while the gate terminal (ng) of N1 is coupled to the output of another optional buffer B3. Both buffers B2 and B3 are coupled to the output of another optional buffer B1, which has inputs coupled to other circuitry within control circuitry 106. The inductor L1 of the two-stage buck converter 102 is coupled to node lx1 at one terminal and to the output node Vout at the other terminal.

[0033] The three-stage buck converter 204 in the illustrated embodiment includes a pull-up stack with transistors P2 and P3 and a pull-down stack with transistors N2 and N3. The drain terminal of P3 is coupled to node lx2, while the source terminals of P3 and P2 are coupled to each other. The source terminal of P2 is coupled to the supply voltage node Vdd. Regarding the pull-down stack, the drain terminal of N2 is coupled to node lx2, while the source terminal of N2 is coupled to the drain terminal of N3. The source terminal of N3 is coupled to ground or Vss. Inductor L2 has a first terminal coupled to node lx2 and a second terminal coupled to the output node Vout. The three-stage buck converter 204 also includes a capacitor Cfly coupled between the source terminals of P3 and N2.

[0034] During the operation of the two-stage buck converter 102, only one of transistors, P1 or P2, is active at any given time. When a high input is applied to buffer B1 (and thus propagates to the gate terminals of P1 and N1), transistor N1 is active, while P1 is inactive. When N1 is active, the voltage at node lx1 is pulled low to ground / Vss. Energy stored in inductor L1 can be discharged to ground / Vss through N1. Simultaneously, an opposite voltage is generated across inductor L1. When a low input is applied to buffer B1, transistor P1 is activated, while transistor N1 is turned off. When P1 is active, node lx1 is pulled high toward Vdd. Inductor L1 discharges current to the output node, and an opposite voltage is generated between them.

[0035] The control circuit 106 can adjust the current supplied by the two-stage buck converter 102 to the output node by adjusting its duty cycle (e.g., by changing the amount of time each transistor is active within a given cycle). This may result in a corresponding adjustment of the voltage on the output node Vout.

[0036] The three-stage buck converter 204 in the illustrated embodiment can output one of three different voltages—zero volts, Vdd, and a third voltage—based on the voltage across capacitor Cfly. When both transistors N2 and N3 in the pull-down stack are active, the voltage at node lx2 can be pulled down toward ground / Vss. When both transistors P2 and P3 in the pull-up stack are active, the voltage at node lx2 can be pulled toward Vdd. When the transistors of the three-stage buck converter are switching with a 50% duty cycle, the third voltage at lx2 (the voltage across Cfly) is Vdd / 2. This third voltage can be adjusted by changing the duty cycle of the transistors in the three-stage buck converter 204, as will be discussed in further detail below. As with the embodiment discussed above, the current flowing into lx2 can vary with the voltage at the node at any given time. Similarly, inductor L2 can release current in one direction or the other, depending on the switching state of the transistors, where the opposite voltage is generated.

[0037] The currents generated by the two-stage buck converter 102 and the three-stage buck converter 204 are summed at the output node Vout. Due to the presence of capacitor VC, the current and therefore the voltage at this node can be averaged to the DC voltage supplied to the load circuit 121.

[0038] Figure 3 The timing diagrams above illustrate the operation of the buck converter implementation scheme. The topmost timing diagram shows the timing of an implementation scheme of a two-stage buck converter operating at 50% duty cycle. The bottom two timing diagrams show the operation of an implementation scheme of a three-stage buck converter, with duty cycles less than 50% and greater than 50%.

[0039] In the two-stage step-down example at the top of the diagram, nodes pg and ng correspond to... Figure 2 The gate terminals of transistors P1 and N1 in an embodiment of the two-stage buck converter 102 are shown. The voltage on node lx1 resulting from these switching states is also shown. When both pg and ng are low, transistor P1 is active and N1 is inactive. Therefore, the voltage on lx1 is pulled up towards Vdd. When both pg and ng are high, transistor P1 is turned off and transistor N1 is turned on. Therefore, the voltage on lx1 is pulled down towards ground / Vss.

[0040] Regarding the illustrations for a three-stage buck converter, it should be noted that the pulse widths depicted are not necessarily drawn to scale. However, the states shown are those experienced by the circuit at their respective labeled duty cycles.

[0041] The three states corresponding to the output of the three-stage buck converter 204 are as follows. The first state, SA, corresponds to node lx2 equal to Vdd - VCfly (VCfly is the voltage across capacitor Cfly), where current flows from Vdd through Cfly and L2 to the output node Vout. The SB state corresponds to lx2 equal to Vss, where the current path is from Vss through L2 to Vout. The SC state corresponds to the voltage across lx2 equal to the voltage across Cfly, where the current path is from Vss through Cfly and L2 to Vout. The SD state corresponds to the voltage across lx2 equal to Vdd, where the current path is from Vdd through L2 to Vout. The states can also be described according to a specific transistor configuration (on / off). For example, the SB state corresponds to transistors N2 and N3 being on, and P2 and P3 being off (and therefore, the pull-down path is fully activated). Similarly, the SD state corresponds to transistors N2 and N3 being off, while P2 and P3 are both on (and therefore, the pull-up path is fully activated). These transistor configurations are described in the timing diagram along with their respective states.

[0042] In the timing diagram corresponding to a duty cycle of less than 50%, the voltage at node lx2 varies between a low Vss and Vdd-VCfly, where VCfly is the third voltage level less than Vdd / 2 in this case. The SA state occurs when both transistors P2 and N2 are on, while P3 and N3 are off. The next state SB occurs when P2 and P3 are off, while both N2 and N3 are on. The SC state subsequently occurs when P2 and N2 are off, while P3 and N3 are on. The final state in the cycle is SB. The cycle can then be repeated as operations continue.

[0043] In a timing diagram corresponding to a duty cycle greater than 50%, the cycle is as follows. The first state generated in the cycle is the SD cycle, which occurs when P2 and P3 are on and N2 and N3 are off. The next state is the SA state, where P2 and N2 are on and P3 and N3 are off. The SA state is followed by the SD state. The final state in this sequence is the SC state, which occurs when transistors P2 and N2 are off and P3 and N3 are on.

[0044] Figure 4 This is a block diagram of another embodiment of a voltage regulator having multiple instances of both two-stage buck converters and N-stage buck converters. In the illustrated embodiment, voltage regulator 400 includes two instances of a two-stage buck converter 102 and two instances of an N-stage buck converter 104. Generally, the voltage regulator according to this disclosure can be implemented with any number of two-stage buck converters 102 and any number of N-stage buck converters. Furthermore, the control circuit 106 in such embodiments can independently control the switching sequence of each of the buck converters, which can switch independently of each other. Thus, the two-stage buck converters can be switches that use different duty cycles relative to each other. Similarly, the two N-stage buck converters 104 can switch relative to each other with different duty cycles. Depending on the description of the specific embodiment using voltage regulator 400, any number of two-stage buck converters 102 and any number of N-stage buck converters can be implemented in various embodiments.

[0045] Figure 5 This is another embodiment of the voltage regulator. In this particular embodiment, in addition to multiple two-stage buck converters 102, an N-stage buck converter 104 and an M-stage buck converter 504 are also included. In this example, M is also an integer of three or greater, and is also different from N. For example, N can be equal to three, and M can be equal to five, and therefore the corresponding embodiment would include both a three-stage buck converter and a five-stage buck converter, as well as the two-stage buck converter 102 shown herein. Furthermore, embodiments including multiple instances of the N-stage buck converter 104, the M-stage buck converter 504, or both (in addition to the two-stage buck converter 102) are also possible and contemplated.

[0046] Figure 6 This is a flowchart illustrating the operation of one embodiment of a hybrid buck converter. As described above, and... Figures 1 to 5 Various embodiments of the voltage regulator shown are used to perform method 600. Embodiments of the voltage regulator not explicitly discussed in this disclosure may fall within the scope of this disclosure.

[0047] Method 600 includes providing a first current at the output node, wherein the first current is generated by alternately generating one of two voltage levels through a first two-stage buck converter and converting the two voltage levels into the first current using a first inductor (box 605). The method also includes providing a second current at the output node, wherein the second current is generated by generating one of N voltage levels in a predefined order through a first N-stage buck converter and converting the N voltage levels into the second current using a second inductor, where N is an integer value of at least three (box 610). During the execution of the method, control circuitry controls the corresponding duty cycle of the transistors in each of the first two-stage buck converter and the first N-stage buck converter based on a desired voltage and a feedback signal based on the voltage present at the output node (box 615).

[0048] In various embodiments, the method includes the control circuitry altering the duty cycle of activation of each transistor in the first two-stage buck converter and the first N-stage buck controller. In some embodiments, a plurality of two-stage buck converters, including the first two-stage buck converter, provide corresponding currents at the output node. The following embodiments are also possible and contemplated, including a plurality of N-stage buck converters of the first N-stage buck converter providing corresponding currents at the output node, and those having at least one M-stage buck converter providing corresponding currents at the output node, where M is an integer value of three or greater, and where M is not equal to N.

[0049] Next turn Figure 7 The diagram illustrates a block diagram of one embodiment of system 150. In the illustrated embodiment, system 150 includes at least one instance of integrated circuit 10 coupled to external memory 158. The integrated circuit 10 may include a memory controller coupled to external memory 158. The integrated circuit 10 is coupled to one or more peripheral devices 154 and external memory 158. A power supply 156 is also provided to supply a supply voltage to the integrated circuit 10 and to supply one or more supply voltages to memory 158 and / or peripheral devices 154. In some embodiments, more than one instance of integrated circuit 10 may be included (and more than one external memory 158 may also be included).

[0050] Depending on the type of system 150, peripheral device 154 may include any desired circuitry. For example, in one embodiment, system 150 may be a mobile device (e.g., a personal digital assistant (PDA), smartphone, etc.), and peripheral device 154 may include devices for various types of wireless communications, such as WiFi, Bluetooth, cellular, GPS, etc. Peripheral device 154 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 154 may include user interface devices such as a display screen, including a touch screen or multi-touch screen, a keyboard or other input device, a microphone, speakers, etc. In other embodiments, system 150 may be any type of computing system (e.g., a desktop PC, laptop, workstation, tablet, etc.).

[0051] In various embodiments, integrated circuit 10 and / or peripheral device 154 may include the features described above. Figures 1 to 5 The specific implementation of the hybrid DC-DC converter discussed in the article.

[0052] External memory 158 may include any type of memory. For example, external memory 158 may be SRAM, dynamic RAM (DRAM) (such as synchronous DRAM (SDRAM)), dual data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, etc. The external memory 158 may include one or more memory modules to which the memory device is mounted, such as single in-line memory modules (SIMM), dual in-line memory modules (DIMM), etc.

[0053] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. This disclosure is intended to make the following claims interpretable as encompassing all such variations and modifications.

Claims

1. A circuit comprising: A first two-stage buck converter, configured to generate one of two voltage levels, includes a first inductor coupled to receive one of the two voltage levels and configured to provide a corresponding first current at the output node; A first N-stage buck converter is configured to generate one of N voltage levels, where N is an integer value of three or greater, and wherein the first N-stage buck converter includes a second inductor coupled to receive one of the N voltage levels and configured to provide a corresponding second current at the output node; At least one M-stage buck converter, the at least one M-stage buck converter being configured to provide a corresponding current to the output node, wherein M is an integer value of three or greater and wherein M is different from N, wherein the at least one M-stage buck converter is configured to provide a corresponding third current at the output node; and A control circuit, coupled to receive a feedback signal based on the voltage present at the output node, and configured to control the respective states of the transistors in the first two-stage buck converter, the first N-stage buck converter, and the at least one M-stage buck converter, such that the voltage at the output node is maintained at a desired value.

2. The circuit of claim 1, wherein the control circuit is configured to independently control the switching sequence of the first two-stage buck converter, the first N-stage buck converter, and the at least one M-stage buck converter.

3. The circuit according to claim 1, wherein, The circuit includes a second two-stage buck converter, wherein the control circuit is configured to control the switching sequences of the first two-stage buck converter and the second two-stage buck converter such that their duty cycles are different from each other.

4. The circuit of claim 1, wherein the circuit includes a second N-stage buck converter, wherein the control circuit is configured to control the switching sequences of the first N-stage buck converter and the second N-stage buck converter such that their duty cycles are different from each other.

5. The circuit of claim 1, wherein the control circuit is configured to operate the first two-stage buck converter with a 50% duty cycle, and is further configured to operate the first N-stage buck converter with a duty cycle not equal to 50%.

6. The circuit of claim 1, further comprising a feedback circuit, wherein the control circuit is configured to control the duty cycle of each of the first two-stage buck converter, the first N-stage buck converter, and the at least one M-stage buck converter based on the desired value of the voltage at the output node and the feedback voltage generated by the feedback circuit.

7. The circuit according to claim 1 further includes a plurality of two-stage buck converters comprising the first two-stage buck converter.

8. The circuit according to claim 1 further includes a plurality of N-stage buck converters comprising the first N-stage buck converter.

9. The circuit according to claim 1, wherein the N-stage buck converter is a three-stage buck converter.

10. The circuit of claim 9, wherein the three-stage buck converter comprises: A pull-up stack having a first transistor and a second transistor connected in series between a first terminal of the second inductor and an input voltage node, the first transistor having a source terminal coupled to the input voltage node, and the second transistor having a drain terminal coupled to the first terminal of the second inductor; A pull-down stack having a third transistor and a fourth transistor connected in series between the first terminal of the second inductor and a ground node, the third transistor having a drain terminal coupled to the first terminal of the second inductor, and the fourth transistor having a source terminal coupled to the ground node; and A capacitor is coupled between the drain terminal of the first transistor and the drain terminal of the fourth transistor.

11. A method comprising: A first current is provided at the output node, wherein the first current is generated by alternately generating one of two voltage levels through a first two-stage buck converter and by using a first inductor to convert the two voltage levels into the first current; A second current is provided at the output node, wherein the second current is generated by generating one of N voltage levels in a predefined order through a first N-stage buck converter and converting the N voltage levels into the second current using a second inductor, wherein N is an integer value of at least three; A third current is provided at the output node using at least one M-stage buck converter, where M is an integer value of three or greater, and where M is not equal to N; as well as The control circuit controls the duty cycle of the transistors in each of the first two-stage buck converter and the first N-stage buck converter based on the desired output voltage and a feedback signal generated using the voltage present at the output node.

12. The method of claim 11, further comprising independently controlling the switching sequence of the first two-stage buck converter, the first N-stage buck converter, and the at least one M-stage buck converter.

13. The method of claim 11, further comprising controlling the switching sequences of the first two-stage buck converter and the second two-stage buck converter such that their duty cycles are different from each other.

14. The method of claim 11, further comprising operating the first two-stage buck converter at a 50% duty cycle and operating the first N-stage buck converter at a duty cycle not equal to 50%.

15. The method of claim 11, further comprising controlling the duty cycle of each of the first two-stage buck converter, the first N-stage buck converter, and the at least one M-stage buck converter based on the expected value of the output voltage and the feedback voltage generated by the feedback circuit.

16. A system comprising: Load circuit; A hybrid voltage regulator, configured to provide a power supply voltage to the load circuit, the hybrid voltage regulator comprising: The first two-stage buck converter is configured to provide a corresponding first current at the output node; The first N-stage buck converter is configured to provide a corresponding second current at the output node, where N is an integer value greater than two. The first M-stage buck converter is configured to provide a corresponding third current at the output node, where M is an integer value greater than two and different from N; and A control circuit configured to independently control the switching sequence of transistors in the first two-stage buck converter, the first N-stage buck converter, and the first M-stage buck converter to generate the power supply voltage at the output node with a desired voltage value.

17. The system of claim 16, wherein the hybrid voltage regulator includes a second two-stage buck converter, wherein the control circuit is configured to control the switching sequences of the first and second two-stage buck converters such that their respective duty cycles are different from each other.

18. The system of claim 16, wherein the hybrid voltage regulator includes a second N-stage buck converter, wherein the control circuit is configured to control the switching sequences of the first and second N-stage buck converters such that their respective duty cycles are different from each other.

19. The system of claim 16, wherein the control circuit is configured to operate the first two-stage buck converter with a 50% duty cycle, and is further configured to operate the first N-stage buck converter with a duty cycle not equal to 50%.

20. The system of claim 16, wherein N=3, and wherein the first N-stage buck converter comprises: A pull-up stack having a first transistor and a second transistor connected in series between a first terminal of an inductor and an input voltage node, the first transistor having a source terminal coupled to the input voltage node, and the second transistor having a drain terminal coupled to the first terminal of the inductor; A pull-down stack having a third transistor and a fourth transistor connected in series between the first terminal of the inductor and a ground node, the third transistor having a drain terminal coupled to the first terminal of the inductor, and the fourth transistor having a source terminal coupled to the ground node; and A capacitor is coupled between the drain terminal of the first transistor and the drain terminal of the fourth transistor.

Images