Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: forming discrete core layers, where the opposite sidewalls of adjacent core layers in a second direction are a first sidewall and a second sidewall respectively; forming sacrificial sidewalls on the sidewalls of the core layers; forming a sacrificial layer on a part of the substrate between adjacent sacrificial sidewalls; forming a filling layer on the substrate; removing the sacrificial layer to form an opening; removing the sacrificial sidewalls to form a trench; forming masking sidewalls on the sidewalls of the trench, and also filling between the sidewalls of the core layer and the filling layer, and the masking sidewalls on the sidewalls of the trench enclose a first groove; forming a second groove that penetrates the filling layer between the masking sidewalls on the sidewalls of the trench and the second sidewall; removing the core layer to form a third groove; a dividing layer is formed in at least one of the third groove, the second groove and the first groove to divide the corresponding groove along a first direction; etching a target layer below the third groove, the second groove and the first groove to form a target pattern. Embodiments of the present invention improve the pattern accuracy of the target pattern.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's law, making integrated circuits develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] During the development of integrated circuits, generally, as the function density (i.e., the number of internal connection structures per chip) gradually increases, the geometric size (i.e., the minimum element size that can be produced using process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, in the case of continuously shrinking technology nodes, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which improve the flexibility and freedom of layout design of the target pattern.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer for forming a target pattern; forming core layers on the substrate that extend in a first direction and are spaced apart in a second direction perpendicular to the first direction, and the opposite sidewalls of adjacent core layers in the second direction are a first sidewall and a second sidewall respectively; forming sacrificial sidewalls on the sidewalls of the core layers; forming a sacrificial layer extending in the first direction on a part of the substrate between adjacent sacrificial sidewalls, the sacrificial layer covering the sidewall of the sacrificial sidewall on the first sidewall and being spaced apart from the sacrificial sidewall on the second sidewall; forming a filling layer on the substrate exposed by the core layers, the sacrificial sidewalls and the sacrificial layer; removing the sacrificial layer to form an opening in the filling layer; removing the sacrificial sidewalls; the opening and the first sidewall enclose a trench; forming a mask sidewall on the sidewall of the trench, and the mask sidewall also fills the space between the sidewall of the core layer and the filling layer, and the mask sidewalls on the sidewall of the trench enclose a first groove; forming a second groove that penetrates the filling layer between the sidewall of the trench and the mask sidewall on the second sidewall; removing the core layer to form a third groove; wherein, a dividing layer is formed in at least one of the third groove, the second groove and the first groove, and the dividing layer divides the corresponding groove in the first direction; using the dividing layer, the mask sidewall and the filling layer as a mask, patterning the target layer below the third groove, the second groove and the first groove to form a target pattern.

[0007] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a target layer for forming a target pattern; a core layer located on the substrate, the core layer extending in a first direction and spaced apart in a second direction perpendicular to the first direction, and the opposite sidewalls of adjacent core layers in the second direction are a first sidewall and a second sidewall respectively; a filling layer located on the substrate exposed by the core layer, and a trench penetrating part of the filling layer is formed between adjacent core layers in the second direction, the trench exposes the first sidewall and is spaced apart from the second sidewall; a mask sidewall located on the sidewall of the trench and between the sidewall of the core layer and the filling layer, and the mask sidewalls on the sidewall of the trench enclose a first groove; a second groove that penetrates the filling layer between the first groove and the mask sidewall on the second sidewall; wherein, the core layer is used to occupy space for forming a third groove; a dividing layer penetrates at least one of the core layer, the second groove and the first groove in the second direction, and the dividing layer is used to divide the corresponding groove in the first direction.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the shape and position of the first groove are defined by using the sacrificial layer and the mask sidewall, the shape and position of the second groove are defined by using the core layer, and the second groove is formed in different steps, which is beneficial to reducing the difficulty of forming the first groove, the second groove, and the third groove, increasing the process window (for example: improving the optical proximity effect and alleviating the limitation of lithography resolution), and improving the accuracy of pattern transfer, so as to ensure the pattern accuracy of the first groove, the second groove, and the third groove; wherein, a dividing layer is formed in at least one of the third groove, the second groove, and the first groove, and the dividing layer divides the corresponding groove along the first direction, so that a smaller distance can be achieved between the grooves on both sides of the dividing layer. Correspondingly, after patterning the target layer below the third groove, the second groove, and the first groove to form a target pattern, a smaller distance can also be achieved at the head-to-head (HTH) position of adjacent target patterns, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern and meeting the requirement of continuously reducing the pitch in integrated circuits. Description of the Drawings

[0010] Figures 1 to 32 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiment

[0011] As can be seen from the background art, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Specifically, in the current back-end process, the patterning process of metal interconnect lines is difficult and the process window is small.

[0012] For example: when the pattern of the interconnect pattern is relatively complex, the number of masks required for the lithography process is large, which not only results in too high process costs, but also the pattern of the mask is complex, and the optical proximity correction process of the mask is also difficult, resulting in poor pattern accuracy and pattern quality of the formed interconnect lines, and even prone to the problem of short circuit (bridge) at the positions where the interconnect lines do not need to be connected.

[0013] One method uses dummy lines to increase the process window of the lithography process and reduce the complexity of the mask pattern. When the device is working, these dummy lines are in a floating state, that is to say, these interconnect lines are not electrically connected to the external circuit or other interconnect structures. However, these floating dummy lines are likely to increase the parasitic capacitance of the back-end interconnect, resulting in poor performance of the formed semiconductor structure. The currently formed devices still have problems with poor performance.

[0014] To solve the above technical problems, in the method for forming a semiconductor structure provided by an embodiment of the present invention, the shape and position of the first groove are defined by using the sacrificial layer and the mask sidewall, the shape and position of the second groove are defined by using the core layer, and the second groove is formed in different steps, which is beneficial to reducing the difficulty of forming the first groove, the second groove and the third groove, increasing the process window (for example: improving the optical proximity effect and alleviating the limitation of lithography resolution), and improving the accuracy of pattern transfer, so as to ensure the pattern accuracy of the first groove, the second groove and the third groove; wherein, a split layer is formed in at least one of the third groove, the second groove and the first groove, and the split layer splits the corresponding groove along the first direction, so that a smaller distance can be achieved between the corresponding grooves on both sides of the split layer. Correspondingly, after patterning the target layer below the third groove, the second groove and the first groove to form a target pattern, a smaller distance can also be achieved at the head-to-head (HTH) position of adjacent target patterns, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern and meeting the requirement of continuously reducing the pitch in integrated circuits.

[0015] To make the above objects, features and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0016] Figures 1 to 32 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0017] Reference Figure 1 and Figure 2 , Figure 2 is Figure 1 a cross-sectional view at the AA position, providing a substrate 200, including a target layer 100 for forming a target pattern.

[0018] The substrate 200 is used to provide a platform for subsequent process steps. The target layer 100 is a film layer to be patterned to form a target pattern. Among them, the target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor or a fork-sheet transistor, a hard mask (HM) layer and other patterns.

[0019] In this embodiment, the target layer 100 is a dielectric layer. Subsequently, the dielectric layer is patterned to form a plurality of interconnect grooves therein, and then interconnect lines are formed in the interconnect grooves. The dielectric layer is used to achieve electrical isolation between adjacent interconnect lines. Correspondingly, the target pattern is an interconnect groove. The dielectric layer is correspondingly an Inter Metal Dielectric (IMD) layer. The material of the dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0020] In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate 200, and functional structures such as resistor structures and conductive structures may also be formed in the substrate 200. In this embodiment, the substrate 200 further includes a substrate 110 located at the bottom of the target layer 100. As an example, the substrate 110 is a silicon substrate.

[0021] In this embodiment, the substrate 200 further includes a hard mask material layer 115 located on the target layer 100. Subsequently, the hard mask material layer 115 is first patterned to form a hard mask layer, and then the target layer 100 is patterned using the hard mask layer as a mask, which is beneficial to improving the process stability of patterning the target layer 100 and the accuracy of pattern transfer.

[0022] The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon carbonitride, and silicon oxynitride. As an example, the material of the hard mask material layer 115 is titanium nitride.

[0023] In a specific process, according to actual process requirements, a stress buffer layer can also be provided between the hard mask material layer 115 and the target layer 100 to improve the adhesion between the hard mask material layer 115 and the target layer 100 and reduce the stress generated between the film layers. In addition, an etch stop layer can also be provided between the hard mask material layer 115 and the stress buffer layer and on the hard mask material layer 115 to define the stop position of the subsequent etching process, which is beneficial to improving the effect of the subsequent patterning process. The related descriptions of the stress buffer layer and the etch stop layer are not elaborated in this embodiment.

[0024] Continue to refer to Figure 1 and Figure 2 , a core layer 120 extending along a first direction (such as the X direction shown in Figure 1 ) and spaced apart along a second direction (such as the Y direction shown in Figure 1 ) is formed on the substrate 200. The second direction is perpendicular to the first direction. The opposite sidewalls of the core layer 120 adjacent to each other in the second direction are respectively a first sidewall 11 and a second sidewall 12.

[0025] In this embodiment, the core layer 120 is used to occupy the spatial position for forming the third groove, thereby defining the shape and position of the third groove. Compared with directly forming the third groove by an etching process, in this embodiment, the third groove is formed by first forming the core layer 120 for occupying the position of the third groove and then removing the core layer 120, which is beneficial to reducing the formation difficulty of the third groove, increasing the process window for forming the third groove, ensuring the pattern accuracy of the third groove. Correspondingly, after subsequently etching the target layer 100 below the third groove to form the target pattern, it is beneficial to improve the pattern accuracy of the target pattern. The core layer 120 also provides support for subsequently forming the sacrificial sidewall.

[0026] In this embodiment, the core layer 120 is made of a material that is easy to be removed, thereby reducing the process difficulty of subsequently removing the core layer 120. The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0027] As an example, the core layer 120 is a single-layer structure, and the material of the core layer 120 is amorphous silicon.

[0028] Reference Figure 3 and Figure 4 , Figure 4 For Figure 3 is a cross-sectional view at the AA position, and a sacrificial sidewall 130 is formed on the sidewall of the core layer 120.

[0029] The sacrificial sidewall 130 is used to occupy the space for subsequently forming the mask sidewall. The thickness of the sacrificial sidewall 130 also defines the interval between the subsequent adjacent third groove and the second groove. In this embodiment, it is easy to adjust the thickness of the sacrificial sidewall 130 to make the adjacent third groove and the second groove meet the designed minimum interval.

[0030] In this embodiment, the core layer 120 is first formed, and then the sacrificial sidewall 130 is formed on the sidewall of the core layer 120. The sacrificial sidewall 130 is an outer spacer; after removing the core layer 120 to form the third groove, the distance between the adjacent third grooves along the first direction is defined by the core layer 120. Compared with first forming the groove and then forming the inner sidewall on the sidewall of the groove, in this embodiment, the distance between the adjacent second grooves along the first direction is not the sum of the distance between the adjacent core layers and twice the thickness of the inner sidewall, which is beneficial to achieving a smaller distance between the adjacent third grooves along the first direction. Correspondingly, after patterning the target layer below the third groove to form the target pattern, the adjacent target patterns can achieve a smaller distance at the head-to-head position, which is beneficial to improving the layout design flexibility and freedom of the target pattern and also beneficial to saving the process cost.

[0031] The sacrificial sidewall 130 is made of a material that has an etching selectivity with respect to the core layer 120 and the target layer 100. The material of the sacrificial sidewall 130 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide, and amorphous silicon. As an example, the material of the sacrificial sidewall 130 is silicon nitride.

[0032] In this embodiment, forming the sacrificial sidewall 130 includes an atomic layer deposition process, which is beneficial to improving the thickness uniformity of the sacrificial sidewall 130 and facilitating precise control of the thickness of the sacrificial sidewall 130.

[0033] Reference Figure 5 and Figure 6 , Figure 6 is Figure 5 a cross-sectional view at the AA position. A sacrificial layer 140 extending in a first direction (such as the X direction shown in Figure 5 ) is formed on a portion of the substrate 200 between adjacent sacrificial sidewalls 130. The sacrificial layer 140 covers the sidewalls of the sacrificial sidewalls 130 on the first sidewall 11 and is spaced apart from the sacrificial sidewalls 130 on the second sidewall 12.

[0034] The sacrificial layer 140 is used to occupy a spatial position for forming an opening. Subsequently, after a filling layer is formed on the substrate 200 exposed by the core layer 120, the sacrificial sidewall 130, and the sacrificial layer 140, and the sacrificial sidewall 130 is removed to form a trench surrounded by the opening and the first sidewall 11, the trench is used to provide support for forming a mask sidewall subsequently, so that the mask sidewall in the trench can surround a first groove. Therefore, in this embodiment, the shape and position of the first groove are defined by the sacrificial layer 140 and the mask sidewall.

[0035] Compared with directly defining the shape and position of the first groove by an etching process or a single film layer, in this embodiment, the shape and position of the first groove are defined by the sacrificial layer 140 and the mask sidewall. In the step of forming the sacrificial layer 140, the critical dimension of the sacrificial layer 140 is larger than the critical dimension of the subsequent first groove (for example: the dimensions in the first direction and the second direction), which is beneficial to reducing the process difficulty of forming the sacrificial layer 140, reducing the process precision requirements for forming the sacrificial layer 140, for example: reducing the lithography process difficulty of forming the sacrificial layer 140, improving the lithography process tolerance for forming the sacrificial layer 140, and further enabling the pattern quality and pattern precision of the sacrificial layer 140 to be relatively high, and correspondingly ensuring the pattern quality and pattern precision of the subsequent first groove.

[0036] In this embodiment, the sacrificial layer 140 covers the sidewalls of the sacrificial sidewalls 130 located on the first sidewall 11 and is spaced apart from the sacrificial sidewalls 130 located on the second sidewall 12. Among them, along the second direction, the space between the sacrificial layer 140 and the sacrificial sidewalls 130 on the second sidewall 12 is used to fill the subsequent filling layer, so as to facilitate the formation of the second groove subsequently.

[0037] The sacrificial layer 140 is selected from materials having an etching selectivity with respect to the materials of the core layer 120 and the target layer 100. The material of the sacrificial layer 140 includes one or more of organic planarization materials, silicon oxide, and amorphous carbon. Among them, the organic planarization materials include BARC (Bottom Anti-reflective Coating), SOC (spin-on carbon), etc. In this embodiment, the material of the sacrificial layer 140 is spin-on carbon. Spin-on carbon has good filling performance, and the spin-on carbon material is easy to be etched, which is beneficial to reducing the difficulty of forming the sacrificial layer 140 and the difficulty of removing the sacrificial layer 140 subsequently.

[0038] In this embodiment, the top surface of the sacrificial layer 140 is higher than the top surface of the core layer 120. The process of forming the sacrificial layer 140 includes the steps of forming a sacrificial material layer covering the sacrificial sidewalls 130 and the core layer 120 and patterning the sacrificial material layer. By making the top surface of the sacrificial layer 140 higher than the top surface of the core layer 120, the step of removing the sacrificial material layer higher than the top surface of the core layer is omitted. Among them, the difficulty of removing the sacrificial material layer higher than the top surface of the core layer 120 is relatively large, which is beneficial to reducing the process difficulty of forming the sacrificial layer 140.

[0039] In this embodiment, the sacrificial layer 140 also covers the top surfaces of the sacrificial sidewalls 130 located on the first sidewall 11.

[0040] In other embodiments, the top surface of the sacrificial layer can also be flush with the top surface of the core layer.

[0041] Reference Figures 7 to 9 , a filling layer 160 is formed on the substrate 200 where the core layer 120, the sacrificial sidewalls 130, and the sacrificial layer 140 are exposed.

[0042] The filling layer 160 is used to provide a process basis for the subsequent formation of the second groove. The filling layer 160 is used as a mask for patterning the target layer 100 together with the subsequent mask sidewalls and the dividing layer. In this embodiment, the filling layer 160 includes a preset region D (as Figure 8 shown) between the sidewalls of the sacrificial layer 140 and the sacrificial sidewalls 130 located on the second sidewall 12. The preset region D is used to form the second groove.

[0043] The filling layer 160 is made of a material that has an etching selectivity with respect to the materials of the core layer 120, the sacrificial layer 140, and the sacrificial sidewall 130. The material of the filling layer 160 includes spin-on silica, metal oxides (e.g., titanium oxide), polysilicon, and amorphous silicon. In this embodiment, the material of the filling layer 160 is spin-on silica. The process for forming the filling layer 160 includes a spin-coating process, which is beneficial to improving the filling ability and filling quality of the filling layer 160, and is also beneficial to improving the top surface flatness of the filling layer 160.

[0044] In this embodiment, the steps for forming the filling layer 160 include:

[0045] As Figure 7 shown, Figure 7 is a cross-sectional view based on Figure 6 wherein a filling material layer 150 covering the core layer 120, the sacrificial layer 140, and the sacrificial sidewall 130 is formed on the substrate 200.

[0046] The process for forming the filling material layer 150 includes one or more of atomic layer deposition process, chemical vapor deposition process, and spin-coating process. As an example, the spin-coating process is used to form the filling material layer 150. The spin-coating process is simple to operate, has a low process cost, and is beneficial to improving the top surface flatness of the filling material layer 150.

[0047] As Figure 8 and Figure 9 shown, Figure 9 is Figure 8 a cross-sectional view at the AA position, where the filling material layer 150 above the top surface of the core layer 120 is removed, and the remaining filling material layer 150 is used as the filling layer 160.

[0048] In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to remove the filling material layer 150 above the top surface of the core layer 120.

[0049] Referring to Figure 10 and Figure 11 , Figure 11 is Figure 10 a cross-sectional view at the AA position, where the sacrificial layer 140 is removed, and an opening 10 is formed in the filling layer 160.

[0050] In this embodiment, the forming method further includes: removing the sacrificial sidewall 130. After removing the sacrificial sidewall 130, the opening 10 is used to form a trench together with the first sidewall 11.

[0051] In this embodiment, the sacrificial layer 140 also covers the top surface of the sacrificial sidewall 130 located on the first sidewall 11. Therefore, the sacrificial layer 140 is first removed to expose the sacrificial sidewall 130 on the first sidewall 11, facilitating the removal of the sacrificial sidewall 130. In other embodiments, according to actual process requirements, the order of removing the sacrificial layer and the sacrificial sidewall can be flexibly adjusted.

[0052] The process of removing the sacrificial layer 140 includes one or both of wet etching and dry etching processes. In this embodiment, the dry etching process is used to remove the sacrificial layer 140. Specifically, the material of the sacrificial layer 140 is spin-on carbon, and the ashing process is used to remove the sacrificial layer 140. As an example, the sacrificial layer 140 is removed using oxygen plasma. The process of removing the sacrificial layer 140 is simple, has low difficulty, and has little impact on other film layers.

[0053] Reference Figure 12 and Figure 13 , Figure 13 is Figure 12 a cross-sectional view at the AA position, removing the sacrificial sidewall 130; the opening 10 and the first sidewall 11 enclose a trench 30.

[0054] The sidewall of the trench 30 is used to provide support for forming the mask sidewall. Correspondingly, the trench 30 and the mask sidewall located on the sidewall of the trench 30 are used to define the shape and position of the first groove.

[0055] By removing the sacrificial sidewall 130, the first sidewall 11 of the core layer 120 is exposed. Subsequently, after forming the mask sidewall on the sidewall of the trench 30, the mask sidewalls located on the sidewall of the trench 30 enclose the first groove. The interval between the first groove and the first sidewall 11 is correspondingly the thickness of the mask sidewall, and the interval between the first groove and the third groove is also correspondingly the thickness of the mask sidewall, which is conducive to ensuring that the minimum design interval is satisfied between the first groove and the third groove.

[0056] In this embodiment, after removing the sacrificial sidewall 130, a gap 20 is formed between the sidewall of the core layer 120 and the filling layer 160. The gap 20 is used to reserve space for forming the mask sidewall.

[0057] The process of removing the sacrificial sidewall 130 includes one or both of dry etching and wet etching processes. In this embodiment, the wet etching process is used to remove the sacrificial sidewall 130. The wet etching process is easy to achieve a high etching selectivity, which is conducive to completely removing the sacrificial sidewall 130 and has simple operation.

[0058] Reference Figure 14 and Figure 15, in this embodiment, the forming method further includes: after forming the core layer 120, forming a third blocking groove 210 that penetrates the core layer 120 in the second direction (as Figure 15 shown).

[0059] The third blocking groove 210 is used to divide the core layer 120 in the first direction, so that a smaller distance can be achieved between adjacent core layers 120 in the first direction. The third blocking groove 210 is also used to provide a spatial position for forming a third dividing layer. Thus, after removing the core layer 120 to form a third groove, the third dividing layer divides the third groove in the first direction.

[0060] As an example, after removing the sacrificial layer 140 and the sacrificial sidewall 130 and before forming the mask sidewall, the third blocking groove 210 is formed. Forming the third blocking groove 210 before forming the mask sidewall, so that in the subsequent step of forming the mask sidewall, the mask sidewall can be formed in the third blocking groove 210, and the mask sidewall located in the third blocking groove 210 can be used as the third dividing layer. Accordingly, the steps of forming the mask sidewall and the third dividing layer are integrated, and the step of additionally forming the third dividing layer is omitted, which is beneficial to simplifying the process and improving the process integration degree.

[0061] In other embodiments, according to actual process requirements, other process steps can also be used to form the third dividing layer.

[0062] The following combines the drawings to detail the specific steps of forming the third blocking groove in this embodiment.

[0063] As Figure 14 shown, a covering layer 170 covering the core layer 120 is formed on the filling layer 160, and the covering layer 170 also fills the gap 20 and the trench 30.

[0064] Subsequently, a dividing opening is formed in the covering layer 170, and the remaining covering layer 170 is used as a mask for etching the core layer 120. In this embodiment, the material of the covering layer 170 includes spin-on carbon.

[0065] As Figure 14 shown, a dividing opening 180 that spans the core layer 120, the trench 30, the filling layer 160, and the gap 20 in the second direction (such as the Y direction in Figure 14 ) is formed in the covering layer 170.

[0066] The dividing opening 180 is used to define the size and position for cutting the core layer 120.

[0067] In this embodiment, the dividing opening 180 straddles the core layer 120, the trench 30, the filling layer 160, and the gap 20, so that the requirement for the dimensional accuracy of the dividing opening 180 in the second direction is low, which is conducive to reducing the difficulty of forming the dividing opening 180 and increasing the process window for forming the dividing opening 180.

[0068] As Figure 15 shown, using the covering layer 170 as a mask, the core layer 120 exposed by the dividing opening 180 is removed to form a third blocking groove 210 that penetrates the core layer 120 in the second direction; the covering layer 170 is removed.

[0069] Since there is an etching selectivity between the core layer 120 and the substrate 200 or the filling layer 160, even if the dividing opening 180 also straddles the trench 30, the filling layer 160, and the gap 20, the probability of accidentally etching the substrate 200 and the filling layer 160 during the process of removing the core layer 120 exposed by the dividing opening 180 is low.

[0070] In this embodiment, an anisotropic dry etching process is used to remove the core layer 120 exposed by the dividing opening 180, thereby improving the accuracy of pattern transfer. In this embodiment, one or both of an ashing process and a wet stripping process are used to remove the covering layer 170.

[0071] In some other embodiments, the step of forming the third dividing layer may further include: after forming the core layer and before removing the core layer, ion doping is performed on a part of the core layer to improve the etch resistance of the core layer, and the core layer doped with ions is used as the third dividing layer. The material of the core layer includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride; the ions for ion doping a part of the core layer include one or more of boron ions, phosphorus ions, and argon ions. By forming the third dividing layer by ion doping a part of the core layer, the etch resistance of the third dividing layer is greater than that of the core layer. In the step of removing the core layer to form the third groove, a high selectivity can be achieved between the core layer and the third dividing layer, so that the third dividing layer can be retained for dividing the third groove in the first direction. Moreover, by forming the third dividing layer by ion doping a part of the core layer, the steps of etching to form the third blocking groove and filling the third dividing layer in the third blocking groove are also omitted, which is conducive to simplifying the process.

[0072] Referring to Figures 16 to 17 , the forming method further includes: after forming the filling layer 160 and before forming the mask sidewall, forming a second blocking groove 230 that penetrates the filling layer 160 in the second direction in a preset area D.

[0073] The second blocking groove 230 is used to divide the filling layer 160 of the preset area D along the first direction, and the second blocking groove 230 also provides a spatial position for forming the second dividing layer. After subsequently forming the second dividing layer in the second blocking groove 230 and forming the second groove in the filling layer 160 of the second preset area D, the second groove can be divided by the second dividing layer along the first direction, which is beneficial to achieving a smaller distance between the second grooves along the first direction.

[0074] In this embodiment, the second blocking groove 230 is formed after removing the sacrificial layer 140 and the sacrificial sidewall 130 and before forming the mask sidewall. By forming the second blocking groove 230 before forming the mask sidewall, in the step of forming the mask sidewall, the mask sidewall can be formed in the second blocking groove 230, and the mask sidewalls located in the second blocking groove 230 are in contact with each other. The mask sidewall filled in the second blocking groove can be used as the second dividing layer, and accordingly, the steps of forming the mask sidewall and the second dividing layer are integrated, eliminating the step of additionally forming the third dividing layer, which is beneficial to simplifying the process and improving the process integration degree.

[0075] The process sequence of forming the second blocking groove 230 is not limited to this. In other embodiments, according to the actual process, the process sequence of forming the second blocking groove can also be flexibly adjusted.

[0076] As an example, the second blocking groove 230 is formed after forming the third blocking groove 210. The sequence of forming the second blocking groove 230 and the third blocking groove 210 is not limited to this.

[0077] The following will describe the specific steps of forming the second blocking groove 230 in this embodiment with reference to the accompanying drawings.

[0078] As shown in Figure 16 a pattern definition layer 190 covering the core layer 120 is formed on the filling layer 160, and the pattern definition layer 190 also fills the gap 20 and the trench 30.

[0079] Subsequently, a cutting opening is formed in the pattern definition layer 190, and the remaining pattern definition layer 190 is used as a mask for etching the filling layer 160 to form the second blocking groove.

[0080] In this embodiment, the material of the pattern definition layer 190 is spin-on carbon.

[0081] As shown in Figure 16 a cutting opening 220 spanning the filling layer 160, the trench 30, the core layer 120, and the gap 20 in the second direction across the preset area D is formed in the pattern definition layer 190.

[0082] The cutting opening 220 is used to define the size, shape and position of the second blocking groove.

[0083] In this embodiment, the cutting opening 220 spans the filling layer 160, the groove 30, the core layer 120 and the gap 20 of the preset area D, so that the requirement for the dimensional accuracy of the cutting opening 220 in the second direction is low, which is beneficial to reducing the difficulty of forming the cutting opening 220 and increasing the process window for forming the cutting opening 220.

[0084] As Figure 17 shown, using the pattern definition layer 190 as a mask, the filling layer 160 exposed by the cutting opening 220 is removed, and the second blocking groove 230 is formed in the filling layer 160 of the preset area D; the pattern definition layer 190 is removed.

[0085] In this embodiment, an anisotropic dry etching process is used to remove the filling layer 160 exposed by the cutting opening 220, which is beneficial to improving the accuracy of pattern transfer and the control of the etching profile. In this embodiment, one or both of an ashing process and a wet stripping process are used to remove the pattern definition layer 190.

[0086] Refer to Figure 18 and Figure 19 , Figure 19 For Figure 18 the cross-sectional view at the AA position, a mask sidewall 240 is formed on the sidewall of the groove 30, and the mask sidewall 240 also fills between the sidewall of the core layer 120 and the filling layer 160. The mask sidewalls 240 located on the sidewalls of the groove 30 enclose a first groove 101.

[0087] The mask sidewall 240 fills the gap 20.

[0088] The mask sidewall 240 is used as a mask for the filling layer 160 and the dividing layer as the patterned target layer 100. The mask sidewall 240 is also used to achieve isolation between adjacent grooves. Therefore, in this embodiment, it is easy to adjust the thickness of the mask sidewall 240 to make the minimum design interval between adjacent grooves satisfied.

[0089] The first groove 101 is used to define the shape and position of the target pattern.

[0090] In this embodiment, the thickness of the mask sidewall 240 located on the sidewall of the groove 30 is greater than or equal to 0.5 times the thickness of the sacrificial sidewall 130, so as to ensure that the mask sidewall 240 can fill the gap 20 completely.

[0091] In this embodiment, the thickness of the mask sidewall 240 is the same as that of the sacrificial sidewall 130. Correspondingly, after the second groove and the third groove are formed subsequently, the intervals between two adjacent grooves along the second direction are the same. After the target layer 100 under the first groove 101, the second groove, and the third groove is patterned to form the target pattern, the intervals between the target patterns along the second direction are also the same, thereby improving the interval uniformity of the target pattern.

[0092] In a specific implementation, the thickness of the mask sidewall 240 can also be different from that of the sacrificial sidewall 130. Thus, according to actual requirements, by adjusting the thicknesses of the mask sidewall 240 and the sacrificial sidewall 130, the intervals between two adjacent grooves can be made different, and further, the target patterns can have diverse intervals.

[0093] In this embodiment, the mask sidewall 240 is made of a material that has an etching selectivity with respect to the materials of the core layer 120 and the substrate 200. The material of the mask sidewall 240 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon. The material of the mask sidewall 240 is the same as or different from that of the sacrificial sidewall 130.

[0094] In this embodiment, the process for forming the mask sidewall 240 includes an atomic layer deposition process, which is beneficial to improving the thickness uniformity, gap filling ability, and film formation quality of the mask sidewall 240, and is also beneficial to precisely controlling the thickness of the mask sidewall 240.

[0095] In this embodiment, the method for forming the semiconductor structure further includes: after forming the filling layer 160, forming the second dividing layer 320 that penetrates through part of the preset region D along the second direction of the filling layer 160 (as Figure 18 shown), and the second dividing layer 320 divides the filling layer 160 in the preset region D along the first direction.

[0096] The second dividing layer 320 is also used as a mask for subsequent patterning of the target layer 100. By forming the second dividing layer 320, after the second groove that penetrates through the filling layer 160 in the preset region D is formed, the second groove can be divided by the second dividing layer 320 along the first direction, which is beneficial to achieving a smaller distance between the second grooves along the first direction.

[0097] In this embodiment, the step of forming the second dividing layer 320 includes: in the step of forming the mask sidewall 240, the mask sidewall 240 is also formed in the second blocking groove 230, and the mask sidewalls 240 located in the second blocking groove 230 are in contact with each other. The mask sidewall 240 filled in the second blocking groove 230 is used as the second dividing layer 320.

[0098] Therefore, in this embodiment, the second dividing layer 320 is formed by the mask sidewall 240 with its sidewalls in contact, and the material of the second dividing layer 320 is the same as that of the mask sidewall 240 accordingly.

[0099] In this embodiment, the method for forming the semiconductor structure further includes: after forming the core layer 120 and before removing the core layer 120, forming a third dividing layer 330 that penetrates the core layer 120 along the second direction (as Figure 18 shown), and the third dividing layer 330 divides the core layer 120 along the first direction.

[0100] The third dividing layer 330 is also used as a mask for subsequent patterning of the target layer 100.

[0101] Subsequently, the core layer 120 is removed to form a third groove, and the third dividing layer 330 is correspondingly formed in the third groove. The third dividing layer 330 divides the third groove along the first direction, so that a smaller distance can be achieved between the third grooves on both sides of the third dividing layer 330. Correspondingly, after forming the target pattern in the target layer 100 under the third groove, a smaller distance can also be achieved at the head-to-head positions of adjacent target patterns.

[0102] In this embodiment, the step of forming the third dividing layer 330 includes: in the step of forming the mask sidewall 240, the mask sidewall 240 is also formed in the third blocking groove 210, and the mask sidewalls 240 located in the third blocking groove 210 are in contact. The mask sidewall 240 located in the third blocking groove 210 is used as the third dividing layer 330.

[0103] Therefore, in this embodiment, the third dividing layer 330 is formed by the mask sidewall 240 with its sidewalls in contact, and the material of the third dividing layer 330 is the same as that of the mask sidewall 240 accordingly.

[0104] In this embodiment, taking the mask sidewall 240 filling the second blocking groove 230 to form the second dividing layer 320 and also filling the third blocking groove 210 to form the third dividing layer 330 as an example. In other embodiments, according to actual process requirements, forming the second dividing layer and the third dividing layer may further include other steps.

[0105] Refer to Figures 20 to 24 , in this embodiment, after forming the first groove 101 and before forming the second groove and removing the core layer, the method for forming the semiconductor structure further includes: forming a first dividing layer 310 in the first groove 101.

[0106] The first dividing layer 310 is also used as a mask for subsequent patterning of the target layer 100.

[0107] The first dividing layer 310 is used to divide the first groove 101 along the first direction, so that a smaller distance can be achieved between adjacent first grooves 101 along the first direction. After the target pattern is formed on the target layer 100 below the patterned first groove 101, a smaller distance can also be achieved at the head-to-head positions of the target pattern, which is beneficial to improving the design flexibility and freedom of the target pattern, and is also beneficial to meeting the requirement of continuously reducing the pitch in integrated circuits.

[0108] The first dividing layer 310 is selected to have an etching selectivity with the materials of the core layer 120 and the substrate 200. The material of the first dividing layer 310 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon.

[0109] The following describes the specific steps of forming the first dividing layer 310 in this embodiment with reference to the accompanying drawings.

[0110] As Figure 20 and Figure 21 shown, Figure 21 is Figure 20 a cross-sectional view at the AA position. A support layer 250 covering the mask sidewall 240, the core layer 120, and the first groove 101 is formed on the filling layer 160.

[0111] The support layer 250 is used to form the first blocking groove subsequently. After the first blocking groove is formed, the support layer 250 is used to provide support for forming the first dividing layer in the first blocking groove.

[0112] After the first dividing layer is formed, the support layer 250 will also be removed. Therefore, the support layer 250 is selected to be a material that is easy to remove, so as to reduce the difficulty of removing the support layer 250. In this embodiment, the material of the support layer 250 is Spin-On Carbon (SOC). It is suitable for the spin coating process, which is beneficial to reducing the difficulty of forming the support layer 250 and improving the top surface flatness of the support layer 250. Spin-On Carbon is also easy to remove.

[0113] In other embodiments, the material of the support layer may further include one or several of an Organic Dielectric layer (ODL), a Bottom Anti-reflective coating (BARC), a Silicon Anti-reflective coating (Si-ARC), a Deep UV light absorbing Oxide (DUO), a Dielectric Anti-reflective Coating (DARC), and an Advanced Patterning Film (APF). In this embodiment, the support layer 250 is formed by a spin coating process.

[0114] As Figure 20 and Figure 21 shown, a first blocking groove 260 extending in the second direction and spanning the first groove 101 is formed in the support layer 250.

[0115] The first blocking groove 260 is used to define the size, shape, and position of the first dividing layer. In this embodiment, the first blocking groove 260 also spans the adjacent mask sidewall 240, the core layer 120, and the filling layer 160 in the second direction, which is beneficial to reducing the dimensional accuracy requirements for the first blocking groove 260 in the second direction.

[0116] As Figures 22 to 24 shown, the first dividing layer 310 is formed in the first blocking groove 260.

[0117] In this embodiment, the step of forming the first dividing layer 310 in the first blocking groove 260 includes: as Figure 22 shown, a dividing material layer 270 is filled in the first blocking groove 260, and the dividing material layer 270 also covers the support layer 250; as Figures 23 to 24 shown, Figure 24 is Figure 23 a cross-sectional view at the AA position, removing the dividing material layer 270 on the support layer 250, the mask sidewall 240, the core layer 120, and the filling layer 160, and retaining a part of the dividing material layer 270 in the first blocking groove 260 to be used as the first dividing layer 310.

[0118] As an example, a chemical vapor deposition process or an atomic layer deposition process is used to form the dividing material layer 270. Among them, in the step of forming the dividing material layer 270, as the deposition thickness increases, the dividing material layer 270 in the first blocking groove 260 gradually comes into contact and thus fills the first blocking groove 260.

[0119] In this embodiment, a dry etching process (for example: an anisotropic dry etching process) is used to remove the dividing material layer 270 on the support layer 250, the mask sidewall 240, the core layer 120, and the filling layer 160.

[0120] The method for forming the semiconductor structure further includes: removing the support layer 250 to prepare for subsequent processes. The process for removing the support layer 250 includes one or both of an ashing process and a wet stripping process.

[0121] Reference Figure 25 and Figure 26 , Figure 26 is Figure 25 a cross-sectional view at the AA position, forming a second groove 102 that penetrates the filling layer 160 between the sidewall of the trench 30 and the mask sidewall 240 on the second sidewall 12. The second groove 102 is used to define the shape and position of the target pattern.

[0122] In this embodiment, in the step of forming the second groove 102, along the second direction, the mask sidewall 240 can further define the position where etching stops, so that the etching process for forming the second groove 102 can achieve self-alignment according to the position of the mask sidewall 240, correspondingly increasing the process window for forming the second groove 102, and enabling the second groove 102 to be isolated from the first groove 101 and between the second groove 102 and the core layer 120 by the mask sidewall 240.

[0123] In this embodiment, after forming the second groove 102, a second dividing layer 320 is formed in the second groove 102, and the second dividing layer 320 divides the second groove 102 along the first direction, so that a smaller distance can be achieved at the position of the second dividing layer 320 in the second groove 102.

[0124] Reference Figures 27 to 28 , Figure 28 is Figure 27 a cross-sectional view at the AA position, removing the core layer 120 to form a third groove 103; among them, a dividing layer is formed in at least one of the third groove 103, the second groove 102, and the first groove 101, and the dividing layer divides the corresponding groove along the first direction.

[0125] The third groove 103 is used to define the shape and position of the target pattern together with the second groove 102 and the first groove 101. In this embodiment, the shape and position of the first groove 101 are defined by using the sacrificial layer 140 and the mask sidewall 240, and the shape and position of the second groove 102 are defined by using the core layer 120, and the second groove 102 is formed in different steps, which is beneficial to reducing the difficulty of forming the first groove 101, the second groove 102 and the third groove 103, increasing the process window (for example: improving the optical proximity effect and alleviating the limitation of lithography resolution), and improving the accuracy of pattern transfer, so as to ensure the pattern accuracy of the first groove 101, the second groove 102 and the third groove 103.

[0126] Moreover, a dividing layer is formed in at least one of the third groove 103, the second groove 102 and the first groove 101. The dividing layer divides the corresponding groove along the first direction, so that a smaller distance can be achieved between the corresponding grooves on both sides of the dividing layer. Correspondingly, after the target pattern is formed on the target layer under the third groove 103, the second groove 102 and the first groove 101 through patterning, a smaller distance can also be achieved at the head-to-head (HTH) position of adjacent target patterns, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern and meeting the requirement of continuously reducing the pitch in the integrated circuit.

[0127] In this embodiment, the third groove 103, the second groove 102 and the first groove 101 all extend along the first direction and are arranged at intervals along the second direction. Adjacent grooves are isolated from each other by the mask sidewall 240, which is beneficial to making the adjacent grooves meet the designed minimum interval. Correspondingly, after the target pattern is formed on the target layer 100 under the third groove 103, the second groove 102 and the first groove 101 through patterning, it is also easy for adjacent target patterns to meet the designed minimum interval.

[0128] The process of removing the core layer 120 includes one or both of wet etching and dry etching processes.

[0129] As an example, the core layer 120 is removed by using a wet etching process. In this embodiment, the etching solution of the wet etching process includes a TMAH solution (tetramethylammonium hydroxide solution), an SC1 solution or an SC2 solution. Among them, the SC1 solution refers to a mixed solution of NH4OH and H2O2, and the SC2 solution refers to a mixed solution of HCl and H2O2.

[0130] Specifically, in this embodiment, a first dividing layer 310 is formed in the first groove 101, and the first dividing layer 310 divides the first groove 101 along the first direction; a second dividing layer 320 is formed in the second groove 102, and the second dividing layer 320 divides the second groove 102 along the first direction; a third dividing layer 330 is formed in the third groove 103, and the third dividing layer 330 divides the third groove 103 along the first direction.

[0131] It should be noted that the positions and numbers of the above dividing layers are only taken as an example. In actual processes, the positions and numbers of the dividing layers can also be adjusted according to process requirements. For example, dividing layers may not be provided in some grooves, and multiple dividing layers may also be provided in the same groove.

[0132] Reference Figure 29 and Figure 20 , Figure 30 is Figure 29 a cross-sectional view at the AA position. Using the dividing layer, the mask sidewall 240, and the filling layer 160 as a mask, the target layer 100 below the third groove 103, the second groove 102, and the first groove 101 is patterned to form a target pattern 400.

[0133] As can be seen from the foregoing, the graphic design of the first groove 101, the second groove 102, and the third groove 103 has high degrees of freedom and flexibility. The graphic precision of the first groove 101, the second groove 102, and the third groove 103 can be guaranteed. It is easy to meet the minimum design interval between adjacent grooves. After the target layer 100 below the first groove 101, the second groove 102, and the third groove 103 is patterned to form the target pattern 400, the graphic quality and graphic precision of the target pattern 400 can also be guaranteed accordingly, and it is easy to achieve the minimum design interval between adjacent target patterns 400 along the second direction.

[0134] Moreover, a smaller distance can be achieved between the corresponding grooves on both sides of the dividing layer. After the target pattern 400 is formed, a smaller distance can also be achieved at the head-to-head (HTH) position of adjacent target patterns 400, which is conducive to improving the layout design flexibility and freedom of the target pattern 400 and meeting the requirement of continuously decreasing pitch in integrated circuits.

[0135] In this embodiment, the target layer 100 is a dielectric layer. The dielectric layer below the first groove 101, the second groove 102, and the third groove 103 is patterned to form an interconnect trench 40. Correspondingly, the target pattern 400 is an interconnect trench 410. The interconnect trench 410 provides space for forming interconnect lines.

[0136] Specifically, in this embodiment, using the mask sidewall 240, the dividing layer, and the filling layer 160 as a mask, the hard mask material layer 115 under the first groove 101, the second groove 102, and the third groove 103 is patterned to form a hard mask layer 280; using the hard mask layer 280 as a mask, the dielectric layer is patterned to form an interconnect trench 410.

[0137] Reference Figure 31 and Figure 32 , Figure 32 is Figure 31 a cross-sectional view at the AA position, and the forming method further includes: after forming the interconnect trench 410, forming an interconnect line 420 in the interconnect trench 410.

[0138] In this embodiment, the interconnect trenches 410 can achieve a smaller distance at the head-to-head positions, and the interconnect lines 420 can correspondingly achieve a smaller distance at the head-to-head positions, which is beneficial to improving the wiring ability of the interconnect lines 420 at the head-to-head positions, and is also beneficial to improving the freedom and flexibility of the layout design of the interconnect lines 420; moreover, the spacing between adjacent interconnect trenches 410 in the second direction is easy to meet the design minimum spacing, and at the same time, the pattern accuracy of the interconnect trenches 410 is relatively high, which is correspondingly beneficial to making the spacing between the interconnect lines 420 in the second direction meet the design minimum spacing and improving the pattern accuracy of the interconnect lines 420, thereby improving the performance of the semiconductor structure.

[0139] The interconnect line 420 is used to realize the electrical connection between the semiconductor structure and an external circuit or other interconnect structures. In this embodiment, the material of the interconnect line 420 is copper. In other embodiments, the material of the interconnect line can also be a conductive material such as cobalt, tungsten, or aluminum. In this embodiment, in the step of forming the interconnect line 420, the filling layer 160, the mask sidewall 240, the dividing layer, and the hard mask layer 280 are also removed to prepare for subsequent processes.

[0140] Correspondingly, the present invention also provides a semiconductor structure. Reference Figure 25 and Figure 26 , Figure 26 is Figure 25 a cross-sectional view at the AA position, showing a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0141] The semiconductor structure includes: a substrate 200, including a target layer 100 for forming a target pattern; a core layer 120, located on the substrate 200, the core layer 120 extends in a first direction (such as Figure 25 the X direction shown in Figure 25 ) and is arranged at intervals in a second direction (such as Figure 17as shown) and the second sidewall 12 (such as Figure 17 as shown); a filling layer 160, located on the exposed substrate 200 of the core layer 120, and a groove 30 (such as Figure 17 as shown) penetrating through a part of the filling layer 160 is formed between the core layers 120 adjacent in the second direction. The groove 30 exposes the first sidewall 11 and is spaced from the second sidewall 12; a mask sidewall 240 is located between the sidewalls of the groove 30 and between the sidewalls of the core layer 120 and the filling layer 160. The mask sidewalls 240 located on the sidewalls of the groove 30 enclose a first groove 101; a second groove 102 penetrates through the filling layer 160 between the first groove 101 and the mask sidewall 240 located on the second sidewall 12; wherein, the core layer 120 is used to occupy space for forming a third groove; a dividing layer penetrates through at least one of the core layer 120, the second groove 102 and the first groove 101 in the second direction, and the dividing layer is used to divide the corresponding groove in the first direction.

[0142] The core layer 120 occupies space for forming a third groove, and the core layer 120 correspondingly defines the shape and position of the third groove; through the groove 30 and the mask sidewall 240, the pattern and position of the first groove 101 are defined, and the second groove 102 penetrates through the filling layer 160 between the first groove 101 and the mask sidewall 240 located on the second sidewall 12; therefore, in this embodiment, through the core layer 120, and the groove 30 and the mask sidewall 240, the patterns and positions of the third groove and the first groove 101 are respectively defined, and the second groove 102 is formed in different steps, which is beneficial to reducing the formation difficulty of the first groove 101, the second groove 102 and the third groove, increasing the process window (for example: improving the optical proximity effect, alleviating the limitation of lithography resolution), thereby improving the graphic design freedom and flexibility of the first groove 101, the second groove 102 and the third groove, ensuring the graphic accuracy of the first groove 101, the second groove 102 and the third groove, and moreover, adjacent grooves are isolated from each other by the mask sidewall 240, which is beneficial to realizing the minimum designed interval between adjacent grooves, and correspondingly beneficial to enabling adjacent target patterns to meet the minimum designed interval.

[0143] In this embodiment, the semiconductor structure further includes the dividing layer, which penetrates at least one of the core layer 120, the second groove 102, and the first groove 101 along the second direction. The dividing layer is used to divide the corresponding groove along the first direction, so that a smaller distance can be achieved between the corresponding grooves on both sides of the dividing layer. Correspondingly, after patterning the target layer under the third groove, the second groove 102, and the first groove 101 to form the target pattern, a smaller distance can also be achieved at the head-to-head (HTH) position of adjacent target patterns, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern and meeting the requirement of continuously reducing the pitch in the integrated circuit.

[0144] The substrate 200 is used to provide a platform for the process. The target layer 100 is a film layer to be patterned to form the target pattern. Among them, the target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor or a fork-sheet transistor, a hard mask (HM) layer, and other patterns.

[0145] In this embodiment, the target layer 100 is a dielectric layer. Subsequently, the dielectric layer is patterned to form a plurality of interconnect trenches, and then interconnect lines are formed in the interconnect trenches. The dielectric layer is used to achieve electrical isolation between adjacent interconnect lines. Correspondingly, in this embodiment, the target pattern is an interconnect trench, and the dielectric layer is an inter-metal dielectric (IMD) layer.

[0146] In this embodiment, semiconductor devices such as transistors and capacitors can be formed in the substrate 200, and functional structures such as resistor structures and conductive structures can also be formed in the substrate 200. In this embodiment, the substrate 200 further includes a substrate 110 located at the bottom of the target layer 100. As an example, the substrate 110 is a silicon substrate.

[0147] In this embodiment, the substrate 200 further includes a hard mask material layer 115 located on the target layer 100. Subsequently, the hard mask material layer 115 is first patterned to form a hard mask layer, and then the target layer 100 is patterned using the hard mask layer as a mask, which is beneficial to improving the process stability of patterning the target layer 100 and the accuracy of pattern transfer.

[0148] The core layer 120 is used to occupy the spatial position for forming the third groove.

[0149] In this embodiment, the core layer 120 is made of a material that is easy to remove, thereby reducing the process difficulty of removing the core layer 120 subsequently to form the third groove. The core layer 120 has a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0150] As an example, the core layer 120 has a single-layer structure, and the material of the core layer 120 is amorphous silicon.

[0151] The filling layer 160 is used to serve as a mask for the mask sidewall 240 and the dividing layer for the patterned target layer 100. The material of the filling layer 160 includes spin-on silicon oxide, metal oxides (such as titanium oxide), polycrystalline silicon, and amorphous silicon. In this embodiment, the material of the filling layer 160 is spin-on silicon oxide.

[0152] The sidewall of the trench 30 is used to provide support for forming the mask sidewall 240. Correspondingly, the trench 30 and the mask sidewall 240 located on the sidewall of the trench 30 are used to define the shape and position of the first groove 101.

[0153] The trench 30 exposes the first sidewall 11 of the core layer 120, so that the interval between the first groove 101 and the first sidewall 11 is correspondingly the thickness of the mask sidewall 240, and the interval between the first groove 101 and the third groove is also correspondingly the thickness of the mask sidewall 240, which is conducive to making the interval between the first groove 101 and the third groove meet the designed minimum interval.

[0154] The mask sidewall 240 is used to serve as a mask for the filling layer 160 and the dividing layer for the patterned target layer 100. The mask sidewall 240 is also used to achieve isolation between adjacent grooves. Therefore, in this embodiment, it is easy to adjust the thickness of the mask sidewall 240 to achieve the designed minimum interval between adjacent grooves.

[0155] In this embodiment, the mask sidewall 240 is selected to be a material that has an etching selectivity with respect to the materials of the core layer 120 and the substrate 200. The material of the mask sidewall 240 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon carbon oxide, and amorphous silicon.

[0156] The first groove 101 is used to define the shape and position of the target pattern.

[0157] The second groove 102 is used to define the shape and position of the target pattern.

[0158] Both the first groove 101 and the second groove 102 extend in the first direction and are arranged in the second direction.

[0159] The dividing layer is used to divide the corresponding groove along the first direction, so that a smaller distance can be achieved at the position of the corresponding groove where the dividing layer is located.

[0160] In this embodiment, the dividing layer includes a first dividing layer 310 located in the first groove 101; the first dividing layer 310 divides the first groove 101 along the first direction.

[0161] The first dividing layer 310 is also used as a mask for subsequent patterning of the target layer 100.

[0162] The first dividing layer 310 is used to divide the first groove 101 along the first direction, so that a smaller distance can be achieved between adjacent first grooves 101 along the first direction. After the target pattern is formed on the target layer 100 below the patterned first groove 101, a smaller distance can also be achieved at the head-to-head position of the target pattern, which is beneficial to improving the design flexibility and freedom of the target pattern, and is also beneficial to meeting the requirement of continuously reducing the pitch in integrated circuits.

[0163] The first dividing layer 310 is selected from a material having an etching selectivity with respect to the materials of the core layer 120 and the substrate 200. The material of the first dividing layer 310 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon.

[0164] In this embodiment, the dividing layer includes a second dividing layer 320 located in the second groove 102; the second dividing layer 320 divides the second groove 102 along the first direction.

[0165] The second dividing layer 320 is also used as a mask for subsequent patterning of the target layer 100. The second groove 102 is divided by the second dividing layer 320 along the first direction, which is beneficial to achieving a smaller distance between the second grooves 102 along the first direction.

[0166] In this embodiment, the second dividing layer 320 is composed of mask sidewalls 240 with sidewalls in contact, and the material of the second dividing layer 320 is correspondingly the same as the material of the mask sidewalls 240. The second dividing layer 320 is composed of mask sidewalls 240 with sidewalls in contact because the formation step of the second dividing layer 320 includes: after forming the filling layer 160 and before forming the mask sidewalls 230, forming a second blocking groove in the filling layer 160; in the step of forming the mask sidewalls 240, the mask sidewalls 240 are formed in the second blocking groove and the mask sidewalls 240 located in the second blocking groove are in contact and are used as the second dividing layer 320.

[0167] In this embodiment, the splitting layer includes a third splitting layer 330 that penetrates the core layer 120 in the second direction; the third splitting layer 330 splits the core layer 120 in the first direction.

[0168] The third splitting layer 330 is also used as a mask for the subsequent patterning of the target layer 100.

[0169] Subsequently, the core layer 120 is removed to form a third groove, and the third splitting layer 330 is correspondingly formed in the third groove. The third splitting layer 330 splits the third groove in the first direction, so that a smaller distance can be achieved between the third grooves on both sides of the third splitting layer 330. Correspondingly, after patterning the target layer 100 below the third groove, the second groove, and the first groove to form a target pattern, a smaller distance can also be achieved at the head-to-head position of adjacent target patterns.

[0170] In this embodiment, a third blocking groove 210 that penetrates the core layer 120 in the second direction is formed in the core layer 120 (as Figure 17 shown); the mask sidewall 240 is located in the third blocking groove 210, and the mask sidewall 240 located in the third blocking groove 210 is in contact and used as the third splitting layer 330. Therefore, in this embodiment, the material of the third splitting layer 330 is the same as the material of the mask sidewall 240.

[0171] In other embodiments, the material of the third splitting layer is the same as the material of the core layer, and the third splitting layer has doped ions, and the doped ions are suitable for making the etching resistance of the third splitting layer greater than the etching resistance of the core layer. The third splitting layer has doped ions for improving the etching resistance. Therefore, the etching resistance of the third splitting layer is greater than that of the core layer. In the subsequent step of removing the core layer to form a third groove, the core layer and the third splitting layer have a high selectivity, so that the third splitting layer can be retained for splitting the third groove. The material of the third splitting layer includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon. The doped ions include one or more of boron ions, phosphorus ions, and argon ions.

[0172] It should be noted that the positions and numbers of the above splitting layers are only taken as an example. In actual processes, the positions and numbers of the splitting layers can also be flexibly adjusted according to process requirements. For example, no splitting layer can be provided in some grooves, and multiple splitting layers can also be provided in the same groove.

[0173] The semiconductor structure may be formed by the formation method described in the foregoing embodiments, or may be formed by other formation methods. For a specific description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details thereof will not be repeated herein.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including a target layer for forming a target pattern; Forming core layers on the substrate that extend in a first direction and are spaced apart in a second direction, the second direction being perpendicular to the first direction, and the opposite side walls of the adjacent core layers in the second direction being a first side wall and a second side wall respectively; Forming sacrificial sidewalls on the side walls of the core layers; Forming a sacrificial layer on a part of the substrate between the adjacent sacrificial sidewalls, the sacrificial layer covering the side walls of the sacrificial sidewalls on the first side wall and being spaced apart from the sacrificial sidewalls on the second side wall; Forming a filling layer on the substrate exposed by the core layers, sacrificial sidewalls and sacrificial layer; Removing the sacrificial layer to form an opening in the filling layer; Removing the sacrificial sidewalls; The opening and the first side wall enclose a trench; Forming mask sidewalls on the side walls of the trench, the mask sidewalls also filling between the side walls of the core layer and the filling layer, and the mask sidewalls on the side walls of the trench enclose a first groove; Forming a second groove that penetrates the filling layer between the side walls of the trench and the mask sidewalls on the second side wall; Removing the core layer to form a third groove; Wherein, a dividing layer is formed in at least one of the third groove, the second groove and the first groove, and the dividing layer divides the corresponding groove along the first direction; Using the dividing layer, mask sidewalls and filling layer as a mask to pattern the target layer below the third groove, second groove and first groove to form a target pattern.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein, A first dividing layer is formed in the first groove; After forming the first groove and before forming the second groove and removing the core layer, the first dividing layer is formed in the first groove.

3. The method for forming a semiconductor structure as described in claim 2, wherein, The step of forming the first dividing layer includes: forming a support layer on the filling layer to cover the mask sidewalls, core layer and first groove; forming a first blocking groove that extends in the second direction and straddles the first groove in the support layer; forming the first dividing layer in the first blocking groove; removing the support layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first blocking groove also straddles the adjacent mask sidewalls, core layer and filling layer along the second direction; The step of forming the first dividing layer in the first blocking groove includes: filling a dividing material layer in the first blocking groove, and the dividing material layer also covers the support layer; Removing the dividing material layer on the support layer, mask sidewalls, core layer and filling layer, and retaining a part of the dividing material layer in the first blocking groove to be used as the first dividing layer.

5. The method for forming a semiconductor structure according to claim 1, wherein, A second dividing layer is formed in the second groove; In the step of forming the filling layer, the filling layer includes a preset area between the side walls of the sacrificial layer and the sacrificial sidewalls on the second side wall for forming the second groove; After forming the filling layer and before forming the second groove, the second dividing layer that penetrates part of the preset area of the filling layer in the second direction is formed, and the second dividing layer divides the filling layer of the preset area along the first direction.

6. The method for forming a semiconductor structure according to claim 5, wherein, The method for forming the semiconductor structure further includes: after forming the filling layer and before forming the mask sidewall, forming a second blocking groove that penetrates the filling layer in the second direction through the preset area; The step of forming the second dividing layer includes: in the step of forming the mask sidewall, the mask sidewalls located in the second blocking groove are in contact, and the mask sidewalls filling the second blocking groove are used as the second dividing layer.

7. The method for forming a semiconductor structure according to claim 6, wherein After removing the sacrificial layer and the sacrificial sidewall and before forming the mask sidewall, form the second blocking groove; In the step of removing the sacrificial layer, a gap is formed between the sidewall of the core layer and the filling layer; The step of forming the second blocking groove includes: forming a pattern definition layer covering the core layer on the filling layer, and the pattern definition layer also fills the gap and the trench; forming a cutting opening in the pattern definition layer that spans the filling layer, the trench, the core layer, and the gap in the second direction; using the pattern definition layer as a mask, removing the filling layer exposed by the cutting opening, and forming the second blocking groove in the filling layer of the preset area; removing the pattern definition layer.

8. The method for forming a semiconductor structure according to claim 1, wherein, A third dividing layer is formed in the third groove; After forming the core layer and before removing the core layer, form the third dividing layer that penetrates the core layer in the second direction, and the third dividing layer divides the core layer in the first direction.

9. The method for forming a semiconductor structure according to claim 8, wherein, The method for forming the semiconductor structure further includes: after forming the core layer and before forming the mask sidewall, forming a third blocking groove that penetrates the core layer in the second direction; the step of forming the third dividing layer includes: in the step of forming the mask sidewall, the mask sidewalls located in the third blocking groove are in contact, and the mask sidewalls located in the third blocking groove are used as the third dividing layer; Or, The step of forming the third dividing layer includes: after forming the core layer and before removing the core layer, performing ion doping on a part of the core layer to improve the etching resistance of the core layer, and the core layer doped with ions is used as the third dividing layer.

10. The method for forming a semiconductor structure according to claim 9, wherein, After removing the sacrificial layer and the sacrificial sidewall and before forming the mask sidewall, form the third blocking groove; In the step of removing the sacrificial layer, a gap is formed between the sidewall of the core layer and the filling layer; The step of forming the third blocking groove includes: forming a covering layer covering the core layer on the filling layer, and the covering layer also fills the gap and the trench; Forming a dividing opening in the covering layer that spans the core layer, the trench, the filling layer, and the gap in the second direction; using the covering layer as a mask, removing the core layer exposed by the dividing opening, and forming a third blocking groove that penetrates the core layer in the second direction.

11. The method for forming a semiconductor structure as claimed in claim 9, wherein, The step of forming the third dividing layer includes performing ion doping on a part of the core layer; The materials of the core layer include one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride; the ions for ion doping a part of the core layer include one or more of boron ions, phosphorus ions, and argon ions.

12. The method for forming a semiconductor structure according to claim 1, wherein The target layer is a dielectric layer; the target pattern is an interconnect trench. The method for forming the semiconductor structure further includes: after forming the interconnect trench, forming an interconnect wire in the interconnect trench.

13. A semiconductor structure, characterized in that, Comprising: A substrate including a target layer for forming a target pattern. A core layer located on the substrate, the core layer extending in a first direction and arranged at intervals in a second direction, the second direction being perpendicular to the first direction, and the opposite sidewalls of the core layer adjacent in the second direction are respectively a first sidewall and a second sidewall. A filling layer located on the substrate exposed by the core layer, and a trench penetrating through a part of the filling layer is formed between the core layers adjacent in the second direction, the trench exposing the first sidewall and being spaced apart from the second sidewall. A mask sidewall located on the sidewall of the trench and between the sidewall of the core layer and the filling layer, and the mask sidewalls located on the sidewall of the trench enclose a first groove. A second groove penetrating through the filling layer between the first groove and the mask sidewall located on the second sidewall; wherein, the core layer is used to occupy space for forming a third groove. A dividing layer penetrating through at least one of the core layer, the second groove, and the first groove in the second direction, and the dividing layer is used to divide the corresponding groove in the first direction.

14. The semiconductor structure according to claim 13, wherein The dividing layer includes a first dividing layer located in the first groove; the first dividing layer divides the first groove in the first direction.

15. The semiconductor structure according to claim 13, wherein, The dividing layer includes a second dividing layer located in the second groove; the second dividing layer divides the second groove in the first direction.

16. The semiconductor structure according to claim 15, wherein The second dividing layer is composed of mask sidewalls with sidewalls in contact.

17. The semiconductor structure according to claim 13, wherein, The dividing layer includes a third dividing layer penetrating through the core layer in the second direction; the third dividing layer divides the core layer in the first direction.

18. The semiconductor structure according to claim 17, wherein, A third blocking groove penetrating through the core layer in the second direction is formed in the core layer; the mask sidewall is located in the third blocking groove, and the mask sidewalls located in the third blocking groove are in contact to serve as the third dividing layer. Alternatively, the material of the third dividing layer is the same as that of the core layer, and the third dividing layer has doping ions, and the doping ions are suitable for making the etching resistance of the third dividing layer greater than that of the core layer.

19. The semiconductor structure according to claim 18, wherein, The material of the third dividing layer is the same as that of the core layer, and the third dividing layer has doping ions; the material of the third dividing layer includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon carbon oxide, and amorphous silicon; the doping ions include one or more of boron ions, phosphorus ions, and argon ions.

20. The semiconductor structure according to claim 13, wherein The target layer is a dielectric layer; the target pattern is an interconnect trench.

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