Semiconductor structure and method for manufacturing the same

Abstract

A semiconductor structure is provided, comprising a silicon substrate, a buried word line, an active region, an isolation region, and a nitride column. The silicon substrate has a carrier surface. The buried word line is buried in the silicon substrate. The active region and the isolation region are located on the carrier surface. Nitride columns are respectively disposed in the isolation region. The active region and the isolation region are arranged along a first direction. The buried word line extends along a second direction. The nitride column is located below the buried word line in the isolation region. A method for manufacturing the semiconductor structure is also provided. The semiconductor structure disclosed herein can reduce word line interference by using a nitride column below the buried word line.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and, more particularly, to a dynamic random access memory (DRAM) with buried word lines and a method for manufacturing the same. Background Art

[0002] Current DRAM cells consist of a transistor and a capacitor coupled to the transistor. As DRAM density increases, the channel length of traditional planar transistors decreases, leading to short-channel effects such as drain-induced barrier lowering (DIBL). This shrinking device size reduces the distance between wordlines and bitlines, ultimately leading to higher parasitic capacitance between them.

[0003] Buried-WL DRAM structures, which bury the word lines in the substrate, are one solution to this problem. However, as the structure shrinks further, the etching depth of the shallow trench isolation (STI) will vary significantly, eventually causing word line interference after the buried word line is formed. Summary of the Invention

[0004] Therefore, embodiments of the present disclosure are directed to providing a semiconductor structure with buried word lines and a method for fabricating the same.

[0005] According to an embodiment of the present disclosure, a semiconductor structure includes a silicon substrate, a buried word line, an active region, an isolation region, and a nitride pillar. The silicon substrate has a carrier surface. The buried word line is buried in the silicon substrate. The active region and the isolation region are located on the carrier surface. The nitride pillars are respectively disposed in the isolation region. The active region and the isolation region are arranged along a first direction. The buried word line extends along a second direction. The nitride pillar is located below the buried word line in the isolation region.

[0006] In an embodiment of the present disclosure, a top surface of the nitride pillar is aligned with a bottom surface of the buried word line in the active region.

[0007] In an embodiment of the present disclosure, in the first direction, the width of each nitride pillar is smaller than the width of the buried word line in the active region.

[0008] In an embodiment of the present disclosure, in the first direction, a width of a bottom surface of each buried word line above the nitride pillar is smaller than a width of each buried word line in the active region.

[0009] In an embodiment of the present disclosure, in each buried word line, a top surface of the nitride pillar is aligned with a top surface of the silicon substrate.

[0010] According to an embodiment of the present disclosure, a method for fabricating a semiconductor structure includes the following steps: etching second trenches along a second direction on a carrier surface of a silicon substrate; disposing a nitride structure in each second trench; etching a plurality of first trenches along the second direction on the silicon substrate, and etching the nitride structures into a plurality of nitride pillars; and disposing a plurality of buried word lines. Some of the buried word lines are located in the first trenches, while the remaining buried word lines are located above the nitride pillars.

[0011] In an embodiment of the present disclosure, the manufacturing method further comprises the step of conformally disposing an oxide layer in the second trench before disposing the nitride structure.

[0012] In an embodiment of the present disclosure, the step of forming a nitride structure includes the following steps: forming a plurality of nitride strips extending along a first direction; and etching the nitride strips into the nitride structure using a first hard mask. The first hard mask exposes the second trench.

[0013] In an embodiment of the present disclosure, a bottom surface of the first trench on the silicon substrate is aligned with a top surface of the nitride structure.

[0014] In an embodiment of the present disclosure, a top surface of the nitride structure is aligned with a carrier surface of the silicon substrate.

[0015] As described above, in the semiconductor structure of the embodiment of the present disclosure, the nitride pillars buried under the word lines can further prevent word line interference. The manufacturing method of the embodiment of the present disclosure can provide a semiconductor structure without word line interference.

[0016] The foregoing has generally outlined the features and technical advantages of the present disclosure so that the detailed description of the disclosure below may be better understood. Additional features and technical advantages of the present disclosure are described below and form the subject of the claims of the present disclosure. Those skilled in the art will appreciate that the concepts and specific embodiments disclosed herein may be used as a basis for modifying or designing other structures or processes to achieve the objectives of the present disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit or scope of the present disclosure as set forth in the claims.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary descriptions, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present disclosure may be more fully understood by reading the following detailed description of the embodiments in conjunction with the accompanying drawings:

[0019] Figures 1 to 10is a schematic cross-sectional view of an intermediate stage of a method for manufacturing a DRAM according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to the present embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0021] Referring to the drawings, the thickness of layers and regions may be exaggerated to facilitate explanation. When a first layer is referred to as being "on" a second layer or "on" a substrate, it may mean that the first layer is formed directly on the second layer or substrate, or it may mean that a third layer may be present between the first layer and the second layer or substrate.

[0022] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or portions, such elements, components, regions, layers, or portions are not limited by such terms. Rather, such terms are used solely to distinguish one element, component, region, layer, or portion from another region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of this disclosure.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the concepts of the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that, when used in this specification, the terms "comprises" and "comprising" indicate the presence of the stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0024] As used herein, the terms "patterning" and "patterned" are used in this disclosure to describe the operation of forming a predetermined pattern on a surface. The patterning operation includes various steps and processes, and varies according to different embodiments. In some embodiments, a patterning process is used to pattern an existing film or layer. The patterning process includes the following steps: forming a mask on the existing film or layer; and removing the unmasked film or layer using an etching process or other removal process. The mask can be a photoresist or a hard mask. In some embodiments, a patterned layer is formed directly on the surface using a patterning process. The patterning process includes the following steps: forming a photosensitive film on the surface; performing a photolithography process; and performing a development process. The remaining photosensitive film is retained and integrated into the semiconductor device.

[0025] The semiconductor structure according to the embodiments of the present disclosure may be used in DRAM. Figures 1 to 10 is a schematic cross-sectional view of an intermediate stage of a DRAM manufacturing method according to an embodiment of the present disclosure. Figure 1 and Figures 3 to 9 Taken along the first direction d1, Figure 2 and Figure 10 Taken along the second direction d2 , the first direction d1 is parallel to the extension direction of the DRAM active region, and the second direction d2 is parallel to the buried word line of the DRAM.

[0026] See Figure 1 According to an embodiment of the present disclosure, the manufacturing method includes the following steps: providing a silicon substrate 100 having a carrier surface 101 .

[0027] For example, in an embodiment, the oxide layer 110 and the nitride layer 111 are disposed on the carrier surface 101 of the silicon substrate 100 , with the oxide layer 110 located between the silicon substrate 100 and the nitride layer 111 . Furthermore, the photoresist layer 112 is disposed on the nitride layer 111 .

[0028] See Figure 2 , patterning the photoresist layer 112, and the method of the present disclosure further includes the steps of etching the silicon substrate 100 and forming a plurality of oxide structures 102. In other words, the oxide structures 102 in the silicon substrate 100 form a plurality of shallow trench isolations (STIs). After the etching operation, a plurality of first regions 103 are formed between the oxide structures 102.

[0029] See Figure 3 , the manufacturing method of the present disclosure removes Figure 2 The oxide layer 110 and the nitride layer 111 are shown above each first region 103 , and a first hard mask 120 is disposed on the carrier surface 101 of the first region 103 of the silicon substrate 100 . In one embodiment, the first hard mask 120 has a plurality of first openings 121 .

[0030] In addition, in the first direction d1, each first opening 121 has a width w1. For example, the width w1 in the embodiment is about 24 nm, but the present disclosure is not limited thereto. In some embodiments, the width w1 can range from about 23 nm to about 25 nm.

[0031] Specifically, in the embodiment, when the first hard mask 120 is disposed on the silicon substrate 100 , the first region 103 remains untrimmed. The first opening 121 of the first hard mask 120 overlaps with the first region 103 .

[0032] For example, in one embodiment, each first region 103 is exposed to more than one first opening 121. Furthermore, an etching hard mask layer 122 is disposed between the first hard mask 120 and the carrier surface 101 of the silicon substrate 100 for silicon etching. The distribution area of the first hard mask 120 on the carrier surface 101 is substantially the same as the distribution area of the etching hard mask layer 122 on the carrier surface 101.

[0033] In one embodiment, the material of the first hard mask 120 may be TEOS oxide, and the material of the etching hard mask layer 122 may be silicon-containing nitride, but the present disclosure is not limited thereto.

[0034] See Figure 4 In an embodiment, the second hard mask 130 is disposed on the first hard mask 120 . Specifically, the second hard mask 130 is disposed on the silicon substrate 100 carrying the first hard mask 120 , and some of the first openings 121 are filled with the second hard mask 130 .

[0035] The second hard mask 130 has a plurality of second openings 131 , and each second opening 131 is aligned with one of the first openings 121 of the first hard mask 120 . In other words, each second opening 131 exposes one of the first openings 121 of the first hard mask 120 .

[0036] For example, in one embodiment, the second hard mask 130 includes an oxide layer 132, a silicon layer 133, and a bottom layer 134. The bottom layer 134 includes an organic material for gap filling and uniformity. Each second opening 131 passes through the oxide layer 132, the silicon layer 133, and the bottom layer 134 and is aligned with one of the first openings 121. Some of the first openings 121 are filled with the bottom layer 134.

[0037] Furthermore, each second opening 131 also has a width w2 in the first direction d1. This width w2 ranges from approximately 39 nm to approximately 43 nm, for example, 41 nm. Specifically, in the first direction d1, the width w2 of the first opening 121 and the width w2 of the second opening 131 can be the same, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, the width of the second opening 131 in the first direction d1 can be greater than the width of the first opening 121.

[0038] See Figure 5 The manufacturing method disclosed herein is to form a silicon substrate 100 on the carrier surface 101 along Figure 2 A plurality of second trenches 104 are etched along the second direction d2 as shown.

[0039] The silicon substrate 100 is etched using the second hard mask 130, and the second trench 104 is formed. Specifically, the etching removes the portion of the silicon substrate 100 exposed by the second hard mask 130. Figure 3 The first region 103 is shown cut into a plurality of active regions 105 .

[0040] See Figure 6 and Figure 7 The manufacturing method of the present disclosure removes the second hard mask 130 and disposes a nitride structure 140 in each second trench 104 .

[0041] Specifically, if Figure 6 As shown, an oxide layer 141 is conformally disposed in the second trench 104, and a nitride strip 142 is disposed on the oxide layer 141. The nitride strip 142 extends along a first direction d1. Furthermore, the oxide layer 141 and the nitride strip 142 further cover the first hard mask 120, and the top surfaces of the nitride strip 142 and the oxide layer 141 are above the top surface of the first hard mask 120.

[0042] Additionally, oxide layer 141 forms a plurality of oxide openings 143, and nitride strips 142 fill oxide openings 143. For example, in one embodiment, thickness t1 of oxide layer 141 is approximately 11 nm, and thickness t2 of nitride strips 142 above first hard mask 120 is approximately 24 nm.

[0043] See Figure 7 The fabrication method of the present disclosure uses the first hard mask 120 to etch the nitride strips 142 into the nitride structure 140. Since the first hard mask 120 exposes the second trench 104, the nitride structure 140 remains in the second trench 104. In addition, a portion of the oxide layer 141 remains between the second trench 104 and the nitride structure 140.

[0044] In one embodiment, the top surface 144 of the nitride structure 140 is aligned with the carrier surface 101 of the silicon substrate 100 and exposes the carrier surface 101 of the silicon substrate 100 in the active region 105 .

[0045] See Figure 8 The manufacturing method disclosed herein is as follows: Figure 2 The plurality of first trenches 106 are etched along the second direction d2 shown, and the manufacturing method etches the nitride structure 140 into a plurality of nitride pillars 145 .

[0046] The etching process forms a nitride opening 146 on each nitride pillar 145. In addition, the oxide layer 141 except for the nitride opening 146 is tapered from the top surface 147 of the nitride pillar 145 to the carrier surface 101 of the silicon substrate 100.

[0047] On the other hand, the top surface 147 of the nitride pillar 145 is substantially aligned with the bottom surface 107 of the first trench 106 .

[0048] See Figure 9 The manufacturing method of the present disclosure provides a plurality of buried word lines 150. Some of the buried word lines 150 are respectively located in the first trenches 106, and the remaining buried word lines 150 are respectively located above the nitride pillars 145, thereby forming the semiconductor structure 200 of the embodiment.

[0049] In one embodiment, buried word lines 150 are buried in silicon substrate 100, and active regions 105 and isolation regions 108 are located on carrier surface 101. Nitride pillars 145 are disposed in isolation regions 108. Furthermore, active regions 105 and isolation regions 108 are arranged along a first direction d1.

[0050] Furthermore, the top surface 147 of the nitride pillar 145 is aligned with the bottom surface 107 of the buried word line 150 in the active region 105, but the disclosure is not limited thereto. In some embodiments of the disclosure, the height of the buried word line 150 is in the range of approximately 70 nm to 90 nm, and the height of the nitride pillar 145 is in the range of approximately 160 nm to 190 nm.

[0051] In the first direction d1, the width w3 of the nitride pillar 145 is smaller than the width w4 of the buried word line 150 in the active region 105. Furthermore, the width w3 of the bottom surface 107 of the buried word line 150 above the nitride pillar 145 is smaller than the width w4 of the buried word line 150 in the active region 105. Therefore, the buried word line 150 of the embodiment can further reduce word line interference in the semiconductor structure 200.

[0052] See Figure 10 In each buried word line 150, the top surface 147 of the nitride pillar 145 is aligned with the top surface 109 of the silicon substrate 100. Specifically, the shape of the nitride pillar 145 and the shape of the silicon substrate 100 in the buried word line 150 can maintain the fin shape and provide saddle-shaped benefits. The saddle-shaped fin is maintained to increase the channel width and reduce the W volume to improve gate-induced drain leakage (GIDL).

[0053] See Figure 9 and Figure 10 The buried word line 150 may include a conductive layer 151 and a conductive layer 152. Specifically, the material of the conductive layer 151 may include tungsten, and the material of the conductive layer 152 may include polysilicon. In addition, a nitride layer 153 is disposed on the conductive layer 152 and covers the etching hard mask layer 122. However, an oxide layer may also be disposed on the nitride layer 153, but the present disclosure is not limited thereto.

[0054] As described above, in the semiconductor structure of the embodiment of the present disclosure, word line interference can be reduced by burying the nitride pillars under the word lines. The manufacturing method of the embodiment of the present disclosure can provide a semiconductor structure without word line interference.

[0055] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0056] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover modifications and variations of the present disclosure as long as such modifications and variations fall within the scope of the claims of the invention.

[0057]

Explanation of symbols

[0058] 100:Silicon substrate

[0059] 101: Carrier surface

[0060] 102: Oxide structure

[0061] 103: District 1

[0062] 104: Second groove

[0063] 105: Active Zone

[0064] 106: first groove

[0065] 107: bottom surface

[0066] 108: Isolation Area

[0067] 109: Top surface

[0068] 110: oxide layer

[0069] 111: Nitride layer

[0070] 112: Photoresist layer

[0071] 120: First hard mask

[0072] 121: First Opening

[0073] 122: Etching hard mask layer

[0074] 130: Second hard mask

[0075] 131: Second opening

[0076] 132: oxide layer

[0077] 133:Silicon layer

[0078] 134: Bottom

[0079] 140: Nitride structure

[0080] 141: oxide layer

[0081] 142: Nitride strips

[0082] 143: Oxide opening

[0083] 144: Top surface

[0084] 145: Nitride column

[0085] 146: Nitride opening

[0086] 147: Top surface

[0087] 150: buried word line

[0088] 151, 152: conductive layer

[0089] 153: Nitride layer

[0090] 200:Semiconductor structure

[0091] d1: first direction

[0092] d2: second direction

[0093] t1, t2: thickness

[0094] w1, w2, w3, w4: width.

Claims

1. A semiconductor structure, characterized in that Include: a silicon substrate having a carrier surface; a plurality of buried word lines buried in the silicon substrate; A plurality of active regions are located on the surface of the carrier; a plurality of isolation regions located on the surface of the carrier; and A plurality of nitride columns are respectively disposed in the plurality of isolation regions. The plurality of active regions and the plurality of isolation regions are arranged along a first direction, the plurality of buried word lines extend along a second direction, and the plurality of nitride pillars are located below the plurality of buried word lines in the plurality of isolation regions, wherein in each buried word line, a top surface of the plurality of nitride pillars is aligned with an upper surface of the silicon substrate along the second direction. 2 . The semiconductor structure of claim 1 , wherein the top surfaces of the plurality of nitride pillars and bottom surfaces of the plurality of buried word lines in each active region are aligned along the first direction. 3 . The semiconductor structure of claim 1 , wherein in the first direction, a width of each nitride pillar is smaller than a width of each buried word line in the active region. 4 . The semiconductor structure of claim 1 , wherein in the first direction, widths of bottom surfaces of the plurality of buried word lines above the plurality of nitride pillars are smaller than widths of the plurality of buried word lines in the plurality of active regions.

5. A method for manufacturing a semiconductor structure, characterized in that: Include: Etching a plurality of second trenches along a second direction on the carrier surface of the silicon substrate; Disposing a plurality of nitride structures in the plurality of second trenches respectively; Etching a plurality of first trenches along the second direction on the silicon substrate, and etching the plurality of nitride structures into a plurality of nitride pillars; and A plurality of buried word lines are provided, wherein some of the plurality of buried word lines are respectively located in the plurality of first trenches, and the remaining buried word lines are respectively located above the plurality of nitride pillars, and the top surfaces of the plurality of nitride pillars are aligned with the upper surface of the silicon substrate along the second direction.

6. The manufacturing method according to claim 5, further comprising: Before providing the plurality of nitride structures, an oxide layer is conformally provided in the plurality of second trenches.

7. The manufacturing method according to claim 5, wherein providing the plurality of nitride structures comprises: Disposing a plurality of nitride strips extending along a first direction; and etching the plurality of nitride strips into the plurality of nitride structures using a first hard mask, The first hard mask exposes the plurality of second grooves. 8 . The manufacturing method according to claim 5 , wherein bottom surfaces of the plurality of first trenches on the silicon substrate and the top surfaces of the plurality of nitride pillars are aligned along a first direction. 9 . The manufacturing method according to claim 5 , wherein top surfaces of the plurality of nitride structures are aligned with the carrier surface of the silicon substrate along a first direction.

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