Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate comprises: a base substrate, a plurality of first light-emitting elements, a plurality of second light-emitting elements, a plurality of pixel circuits, at least one first initial signal line extending along a first direction, and at least one virtual data line extending along a second direction. The plurality of pixel circuits comprise: a plurality of first effective pixel circuits, a plurality of first invalid pixel circuits, and a plurality of second pixel circuits. At least one first initial signal line is electrically connected to a plurality of pixel circuits arranged along the first direction, and is configured to provide a first initial signal to the pixel circuits. The orthographic projection of at least one virtual data line on the base substrate partially overlaps with the orthographic projection of a plurality of first invalid pixel circuits arranged along the second direction on the base substrate. At least one virtual data line is electrically connected to at least one first initial signal line. The first direction intersects with the second direction.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. The under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of the display device. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a substrate substrate, a plurality of first light-emitting elements, a plurality of second light-emitting elements, a plurality of pixel circuits, at least one first initial signal line extending along a first direction, and at least one virtual data line extending along a second direction. The substrate substrate comprises a first display area and a second display area at least partially surrounding the first display area. A plurality of first light-emitting elements are located in the first display area. A plurality of second light-emitting elements, a plurality of pixel circuits and virtual data lines are located in the second display area. The first initial signal line is located at least in the second display area. The plurality of pixel circuits comprise: a plurality of first effective pixel circuits, a plurality of first invalid pixel circuits and a plurality of second pixel circuits. At least one first effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element. At least one first initial signal line is electrically connected to a plurality of pixel circuits arranged along the first direction, and is configured to provide a first initial signal to the pixel circuit. The orthographic projection of at least one virtual data line on the substrate substrate partially overlaps with the orthographic projection of a plurality of first invalid pixel circuits arranged along the second direction on the substrate substrate. At least one virtual data line is electrically connected to at least one first initial signal line. The first direction intersects the second direction.

[0006] In some exemplary embodiments, the virtual data line is electrically connected to the first initial signal line through a first connecting electrode; the first connecting electrode is located on a side of the first initial signal line away from the base substrate, and the virtual data line is located on a side of the first connecting electrode away from the base substrate.

[0007] In some exemplary embodiments, the first connection electrode has an L-shape in an orthographic projection on the base substrate.

[0008] In some exemplary embodiments, an orthographic projection of the first connecting electrode on the base substrate overlaps with an orthographic projection of the first invalid pixel circuit on the base substrate.

[0009] In some exemplary embodiments, the display substrate of the second display area includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the base substrate. The first initial signal line is located in the second conductive layer, the first connection electrode is located in the third conductive layer, and the dummy data line is located in the fourth conductive layer.

[0010] In some exemplary embodiments, the pixel circuit includes: a driving transistor and a first transistor, wherein a first electrode of the first transistor is electrically connected to a gate of the driving transistor. An orthographic projection of the first initial signal line on the substrate overlaps an orthographic projection of a channel region of an active layer of the first transistor on the substrate.

[0011] In some exemplary embodiments, the first transistor includes a first gate and a second gate; the channel region of the active layer of the first transistor includes: a first channel region, a second channel region and a third channel region, and the third channel region is located between the first channel region and the second channel region. The orthographic projection of the first gate of the first transistor on the substrate covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second gate of the first transistor on the substrate covers the orthographic projection of the second channel region on the substrate. The orthographic projection of the first initial signal line on the substrate overlaps with the orthographic projection of the third channel region of the active layer of the first transistor on the substrate.

[0012] In some exemplary embodiments, the third channel region of the active layer of the first transistor has an L-shape in an orthographic projection on the substrate.

[0013] In some exemplary embodiments, the first initial signal line includes: a main body extending along the first direction and a first extension extending from the main body along the second direction, wherein an orthographic projection of the first extension on the substrate overlaps an orthographic projection of a channel region of an active layer of the first transistor on the substrate.

[0014] In some exemplary embodiments, the first initial signal line further includes: a second extension portion extending from the main body portion along the second direction, the first extension portion and the second extension portion being located at opposite sides of the main body portion in the second direction, and the second extension portion being electrically connected to the dummy data line via a first connection electrode.

[0015] In some exemplary embodiments, the orthographic projection of at least one first effective pixel circuit of the second display area on the substrate substrate does not overlap with the orthographic projection of at least one first light-emitting element of the first display area on the substrate substrate. The orthographic projection of at least one second pixel circuit of the second display area on the substrate substrate at least partially overlaps with the orthographic projection of at least one second light-emitting element on the substrate substrate.

[0016] In some exemplary embodiments, the base substrate further includes: a peripheral region located outside the display region. The display substrate further includes: a first initial peripheral routing line located in the peripheral region, the first initial peripheral routing line being electrically connected to the at least one first initial signal line.

[0017] On the other hand, an embodiment of the present disclosure provides a display device, including the display substrate as described above.

[0018] On the other hand, the embodiment of the present disclosure provides a method for preparing a display substrate, comprising: forming a plurality of pixel circuits, at least one first initial signal line extending along a first direction, and at least one virtual data line extending along a second direction in a second display area of ​​a substrate substrate; forming a plurality of second light-emitting elements in the second display area of ​​the substrate substrate, forming a plurality of first light-emitting elements in the first display area, and the second display area at least partially surrounds the first display area. Wherein, the plurality of pixel circuits include: a plurality of first effective pixel circuits, a plurality of first invalid pixel circuits, and a plurality of second pixel circuits; at least one first effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element. The at least one first initial signal line is electrically connected to the plurality of pixel circuits arranged along the first direction, and is configured to provide the pixel circuit with a first initial signal; the orthographic projection of the at least one virtual data line on the substrate substrate overlaps with the orthographic projection of the plurality of first invalid pixel circuits arranged along the second direction on the substrate substrate; the at least one virtual data line is electrically connected to the at least one first initial signal line. The first direction intersects with the second direction.

[0019] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of one or more components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0021] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0022] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0023] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided;

[0024] Figure 4 A schematic diagram of the arrangement of a plurality of pixel circuits in the second display area of ​​at least one embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of the wiring arrangement of the second display area of ​​at least one embodiment of the present disclosure;

[0026] Figure 6 A partial plan view of a second display area of ​​at least one embodiment of the present disclosure;

[0027] Figure 7 for Figure 6 Schematic diagram of a local cross section along the P-P' direction;

[0028] Fig. 8A for Figure 6 A partial plan view of the second display area after the semiconductor layer is formed;

[0029] Figure 8B for Figure 6 A partial plan view of the second display area after the first conductive layer is formed;

[0030] Figure 8C for Figure 6 A partial plan view of the second display area after the second conductive layer is formed;

[0031] Fig.8D for Figure 6 A partial plan view of the second display area after the third insulating layer is formed;

[0032] Fig. 8E for Figure 6 A partial plan view of the second display area after the third conductive layer is formed;

[0033] Fig.8F for Figure 6A partial plan view of the second display area after the fourth insulating layer is formed;

[0034] Fig. 9 is another partial plan view of the second display area of ​​at least one embodiment of the present disclosure;

[0035] Fig.10 for Fig. 9 A partial plan view of the second display area after the third conductive layer is formed;

[0036] Fig.11 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0038] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0039] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0040] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0041] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0042] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0043] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0044] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged. In addition, the gate electrode may also be called a control electrode.

[0045] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0046] The "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.

[0047] In the present disclosure, "about" and "substantially" mean that the limits are not strictly defined and the situation within the range of process and measurement errors is allowed. In the present disclosure, "substantially the same" may refer to the situation where the numerical values ​​differ by less than 10%.

[0048] The embodiment of the present disclosure provides a display substrate, comprising: a substrate substrate, a plurality of first light-emitting elements, a plurality of second light-emitting elements, a plurality of pixel circuits, at least one first initial signal line extending along a first direction, and at least one virtual data line extending along a second direction. The substrate substrate comprises a first display area and a second display area at least partially surrounding the first display area. The plurality of first light-emitting elements are located in the first display area. The plurality of second light-emitting elements, a plurality of pixel circuits and virtual data lines are located in the second display area. The first initial signal line is located at least in the second display area. The plurality of pixel circuits comprise: a plurality of first effective pixel circuits, a plurality of first invalid pixel circuits and a plurality of second pixel circuits. At least one first effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element. At least one first initial signal line is electrically connected to a plurality of pixel circuits arranged along the first direction, and is configured to provide a first initial signal to the pixel circuit. The orthographic projection of at least one virtual data line on the substrate substrate partially overlaps with the orthographic projection of a plurality of first invalid pixel circuits arranged along the second direction on the substrate substrate. At least one virtual data line is electrically connected to at least one first initial signal line. The first direction intersects with the second direction. For example, the first direction and the second direction are perpendicular to each other. However, this embodiment is not limited to this.

[0049] The display substrate provided in this embodiment can form a mesh structure for transmitting the first initial signal in the second display area by electrically connecting the first initial signal line extending along the first direction and the virtual data line extending along the second direction, thereby optimizing the spatial design of the pixel circuit, thereby improving the recovery ability of the first initial signal and reducing the fluctuation of the first initial signal during resetting.

[0050] In some exemplary embodiments, the virtual data line is electrically connected to the first initial signal line through the first connection electrode. The first connection electrode is located on a side of the first initial signal line away from the substrate substrate, and the virtual data line is located on a side of the first connection electrode away from the substrate substrate. In some examples, the display substrate of the second display area includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the substrate substrate. The first initial signal line is located in the second conductive layer, the first connection electrode is located in the third conductive layer, and the virtual data line is located in the fourth conductive layer. However, this embodiment is not limited to this. For example, the first connection electrode may be located in the fourth conductive layer, and the first connection electrode may be an integral structure with the virtual data line. Alternatively, the virtual data line may be located in the third conductive layer, and the first connection electrode may be located in the fourth conductive layer. In this exemplary embodiment, the electrical connection between the virtual data line and the first initial signal line is achieved through the first connection electrode, which can optimize the design space of the pixel circuit.

[0051] In some exemplary embodiments, the orthographic projection of the first connecting electrode on the substrate overlaps with the orthographic projection of the first invalid pixel circuit on the substrate. In some examples, the first invalid pixel circuit includes: a driving transistor, a first reset transistor, and a data writing transistor. The first electrode of the first reset transistor is electrically connected to the first initial signal line, and the second electrode of the first reset transistor is electrically connected to the gate of the driving transistor. The second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor. The orthographic projection of the first connecting electrode on the substrate overlaps with the orthographic projection of the first reset transistor and the data writing transistor on the substrate. In other examples, the orthographic projection of the first connecting electrode on the substrate substrate may overlap with the orthographic projection of the data writing transistor on the substrate substrate, and is electrically connected to the first reset transistor. However, this embodiment is not limited to this.

[0052] In some exemplary embodiments, the pixel circuit may include: a driving transistor and a first transistor. The first electrode of the first transistor is electrically connected to the gate of the driving transistor. The orthographic projection of the first initial signal line on the substrate overlaps with the orthographic projection of the channel region of the active layer of the first transistor on the substrate. In this exemplary embodiment, the channel region of the first transistor is shielded by the first initial signal line, so as to ensure the stability of the gate signal of the first transistor, optimize the design space of the pixel circuit, and provide support for realizing high-resolution pixel circuit design.

[0053] In some exemplary embodiments, the first transistor includes a first gate and a second gate. The channel region of the active layer of the first transistor includes: a first channel region, a second channel region and a third channel region, and the third channel region is located between the first channel region and the second channel region. The orthographic projection of the first gate of the first transistor on the substrate substrate covers the orthographic projection of the first channel region on the substrate substrate, and the orthographic projection of the second gate of the first transistor on the substrate substrate covers the orthographic projection of the second channel region on the substrate substrate. The orthographic projection of the first initial signal line on the substrate substrate overlaps with the orthographic projection of the third channel region of the active layer of the first transistor on the substrate substrate. In this example, the first transistor is a dual-gate transistor.

[0054] In some exemplary embodiments, the first initial signal line may include a body portion extending in a first direction and a first extension portion extending from the body portion in a second direction, wherein an orthographic projection of the first extension portion on the substrate overlaps an orthographic projection of a channel region of an active layer of the first transistor on the substrate.

[0055] In some exemplary embodiments, the first initial signal line further includes: a second extension portion extending from the main body portion along the second direction. The first extension portion and the second extension portion are located on opposite sides of the main body portion in the second direction. The second extension portion is electrically connected to the virtual data line through the first connecting electrode. The design method of the first initial signal line provided in this exemplary embodiment can optimize the design space of the pixel circuit.

[0056] In some exemplary embodiments, the display substrate may further include: at least one second initial signal line extending along the first direction. At least one second initial signal line is electrically connected to a plurality of pixel circuits arranged along the first direction, and is configured to provide a second initial signal to the first light-emitting element through a first effective pixel circuit, and to provide a second initial signal to the second light-emitting element through a second pixel circuit. The orthographic projection of the first initial signal line on the substrate substrate is located between the orthographic projections of the second initial signal line and the scan line on the substrate substrate. In some examples, the first initial signal line and the second initial signal line may be of the same layer structure. However, this embodiment is not limited to this.

[0057] In some exemplary embodiments, the base substrate further includes a peripheral region located outside the display region. The display substrate further includes: a first initial peripheral routing line located in the peripheral region. The first initial peripheral routing line is electrically connected to at least one first initial signal line.

[0058] The solution of this embodiment is described below by means of some examples.

[0059] Figure 1 Schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 1 As shown, the display substrate may include: a display area AA and a peripheral area BB surrounding the periphery of the display area AA. The display area AA of the display substrate may include: a first display area A1 and a second display area A2 at least partially surrounding the first display area A1. In this example, the second display area A2 surrounds the first display area A1.

[0060] In some exemplary embodiments, Figure 1 As shown, the first display area A1 is a light-transmitting display area, which can also be called the under display camera (UDC) area; the second display area A2 is a non-light-transmitting display area, which can also be called the normal display area. For example, the orthographic projection of a light-sensitive sensor (such as a camera or other hardware) on the display substrate can be located in the first display area A1 of the display substrate. In some examples, such as Figure 1As shown, the first display area A1 may be circular, and the size of the orthographic projection of the light-sensitive sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the light-sensitive sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0061] In some exemplary embodiments, Figure 1 As shown, the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other positions such as the upper left corner or the upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0062] In some exemplary embodiments, Figure 1 As shown, the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be a circle or an ellipse. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon or other shapes.

[0063] In some exemplary embodiments, the display area AA is provided with a plurality of sub-pixels. At least one sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the connected light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor, for example, the pixel circuit may be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc. In some examples, the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, or white light, etc., when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0064] In some exemplary embodiments, a pixel unit of the display area may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.

[0065] In some exemplary embodiments, the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangle; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square. However, this embodiment is not limited to this.

[0066] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 3 for Figure 2 The pixel circuit of this exemplary embodiment is described by taking the 7T1C structure as an example. However, this embodiment is not limited to this.

[0067] In some exemplary embodiments, Figure 2 As shown, the pixel circuit of this example includes six switch transistors (T1, T2, T4 to T7), a drive transistor T3 and a storage capacitor Cst. The six switch transistors are respectively a data write transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light emitting element EL includes an anode, a cathode and an organic light emitting layer arranged between the anode and the cathode. The first transistor mentioned above is the threshold compensation transistor T2 in this example.

[0068] In some exemplary embodiments, the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.

[0069] In some exemplary embodiments, the driving transistor and the six switching transistors may be low-temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0070] In some exemplary embodiments, Figure 2As shown, the display substrate includes a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emitting control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL is configured to provide a scan signal SCAN to the pixel circuit, the data line DL is configured to provide a data signal DATA to the pixel circuit, the light emitting control line EML is configured to provide a light emitting control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, in the nth row of pixel circuits, the first reset control line RST1 can be electrically connected to the scan line GL of the n-1th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected to the scan line GL of the nth row of pixel circuits to be input with the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In some examples, the second reset control line RST2 electrically connected to the nth row of pixel circuits and the first reset control line RST1 electrically connected to the n+1th row of pixel circuits can be an integrated structure. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be realized. However, this embodiment is not limited to this.

[0071] In some exemplary embodiments, the first initial signal line INIT1 is configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 is configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.

[0072] In some exemplary embodiments, Figure 2As shown, the driving transistor T3 is electrically connected to the light emitting element EL, and outputs a driving current under the control of the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals to drive the light emitting element EL to emit light. The gate of the data writing transistor T4 is electrically connected to the scanning line GL, the first electrode of the data writing transistor T4 is electrically connected to the data line DL, and the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scanning line GL, the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3. The gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is electrically connected to the first power line PL1, and the second electrode of the first light emission control transistor T5 is electrically connected to the first electrode of the driving transistor T3. The gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second light emission control transistor T6 is electrically connected to the anode of the light emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light emitting element EL and is configured to reset the anode of the light emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the anode of the light emitting element EL. A first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3 , and a second capacitor plate of the storage capacitor Cst is electrically connected to the first power line PL1 .

[0073] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6, and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0074] Refer to the following Figure 3 right Figure 2 The working process of the pixel circuit is explained as follows. Figure 2 The pixel circuit shown is illustrated by taking the case where the plurality of transistors included therein are all P-type transistors as an example.

[0075] In some exemplary embodiments, Figure 3 As shown, in a frame display time period, the working process of the pixel circuit includes: a first stage S1, a second stage S2 and a third stage S3.

[0076] The first stage S1 is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, which initializes the first node N1 and clears the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, which turns off the data writing transistor T4, the threshold compensation transistor T2, the first light control transistor T5, the second light control transistor T6 and the second reset transistor T7. In this stage, the light emitting element EL does not emit light.

[0077] The second stage S2 is called the data writing stage or the threshold compensation stage. The scanning signal SCAN provided by the scanning line GL is a low level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the light control signal EM provided by the light control line EML are both high level signals, and the data line DL outputs the data signal DATA. In this stage, since the first capacitor plate of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on. The scanning signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, and the voltage of the first capacitor plate (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, the anode of the light-emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and it is ensured that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, which turns off the first reset transistor T1. The light emitting control signal EM provided by the light emitting control signal line EML is a high level signal, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off.

[0078] The third stage S3 is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, and the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, and the first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor T5, the driving transistor T3 and the second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0079] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0080] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0081] Among them, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0082] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the driving transistor T3.

[0083] In some exemplary embodiments, the first display area A1 is provided with a plurality of first light-emitting elements, and the second display area A2 is provided with a plurality of second light-emitting elements and a plurality of pixel circuits. The plurality of pixel circuits of the second display area A2 are configured to drive the first light-emitting elements of the first display area A1 and the second light-emitting elements of the second display area A2 to emit light. In this example, the pixel circuit is provided only in the second display area A2, and the pixel circuit is not provided in the first display area A1, so that the light transmittance of the first display area A1 can be improved.

[0084] Figure 4 The diagram is a schematic diagram of the arrangement of multiple pixel circuits in the second display area of ​​at least one embodiment of the present disclosure. In this example, multiple pixel circuits arranged in sequence along the first direction F1 can be called a row of pixel circuits, and multiple pixel circuits arranged in sequence along the second direction F2 can be called a column of pixel circuits.

[0085] In some exemplary embodiments, Figure 4As shown, the plurality of pixel circuits of the second display area A2 may include: a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12. The plurality of first pixel circuits 11 may include a plurality of first effective pixel circuits and a plurality of first invalid (Dummy) pixel circuits. At least one first effective pixel circuit of the second display area A2 may be electrically connected to at least one first light-emitting element of the first display area A1 through a transparent conductive line. The orthographic projection of at least one first effective pixel circuit of the second display area A2 on the substrate substrate does not overlap with the orthographic projection of at least one first light-emitting element of the first display area A1 on the substrate substrate. For example, the first effective pixel circuit and the first light-emitting element may be in a one-to-one or one-to-many relationship. At least one second pixel circuit of the second display area A2 is electrically connected to at least one second light-emitting element. The orthographic projection of at least one second pixel circuit of the second display area A2 on the substrate substrate overlaps at least partially with the orthographic projection of at least one second light-emitting element on the substrate substrate. For example, the second pixel circuit and the second light-emitting element may be in a one-to-one relationship. The first invalid pixel circuit of the second display area A2 is not electrically connected to either the first light-emitting element of the first display area A1 or the second light-emitting element of the second display area A2.

[0086] In some exemplary embodiments, Figure 4 As shown, at least one first pixel circuit 11 is arranged between a plurality of second pixel circuits 12 arranged along the first direction F1. The first pixel circuit 11 may be arranged between a plurality of columns of second pixel circuits 12. For example, a column of first pixel circuits 11 is arranged between every three columns of second pixel circuits 12. Compared with the second display area in which only second pixel circuits are arranged, in this exemplary embodiment, the original three columns of second pixel circuits are compressed along the first direction F1, thereby adding an arrangement space for a column of first pixel circuits 11, and the space occupied by the three columns of pixel circuits before compression and the four columns of pixel circuits after compression is the same. However, this embodiment is not limited to this.

[0087] Figure 5 FIG. 1 is a schematic diagram of the wiring arrangement of the second display area of ​​at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 5As shown, the peripheral area BB is provided with a first initial peripheral wiring 101. For example, the first initial peripheral wiring 101 is provided in the peripheral area BB on both sides of the display area AA on the first direction F1. The first initial peripheral wiring 101 can be electrically connected to the driving chip (IC) to transmit the first initial signal. The first initial peripheral wiring 101 can extend along the second direction F2 in the peripheral area BB. The second display area A2 is provided with a plurality of first initial signal lines INIT1 extending along the first direction F1. The plurality of first initial signal lines INIT1 can be arranged in sequence along the second direction F2. The first initial signal line INIT1 can be electrically connected to a plurality of pixel circuits arranged along the first direction F1, and is configured to provide a first initial signal to the gate of the driving transistor of the pixel circuit, and reset the gate of the driving transistor. The first initial signal line INIT1 can extend to the peripheral area BB along the first direction F1, and be electrically connected to the first initial peripheral wiring 101 of the peripheral area BB.

[0088] In some exemplary embodiments, Figure 5 As shown, the second display area A2 is also provided with a plurality of virtual data lines 102 extending along the second direction F2. The plurality of virtual data lines 102 are arranged in sequence along the first direction F1. The orthographic projection of the virtual data line 102 on the substrate substrate may overlap with the orthographic projection of the plurality of first invalid pixel circuits arranged along the second direction F2 on the substrate substrate. The first initial signal line INIT1 is electrically connected to the virtual data line 102. In this example, the first initial signal line INIT1 extending along the first direction F1 is electrically connected to the virtual data line 102 extending along the second direction F2, and a mesh structure for transmitting the first initial signal can be formed in the second display area A2. In this way, the signal stability of the first initial signal can be improved, the signal recovery capability of the first initial signal away from the driving chip can be improved, the fluctuation of the first initial signal during reset can be reduced, and the reset effect on the gate of the driving transistor can be improved.

[0089] In some exemplary embodiments, Figure 5 As shown, the second display area A2 is also provided with a plurality of data lines (in Figure 5The plurality of data lines may include: a plurality of first data lines DL1 electrically connected only to the second pixel circuit, and a plurality of second data lines DL2 electrically connected to at least the first effective pixel circuit. For example, the first data line DL1 may extend along the second direction F2, and be electrically connected to a plurality of second pixel circuits arranged along the second direction F2. The second data line DL2 may be electrically connected to a plurality of second pixel circuits located in the second display area A2 on both sides of the first display area A1 along the second direction F2, and may also be electrically connected to a plurality of first effective pixel circuits located in the second display area A2 on one side of the first direction F1 of the first display area A1 and arranged along the second direction F2. The virtual data line 102 may be arranged between the plurality of data lines at intervals along the first direction F1. In some examples, such as Figure 5 As shown, in the second display area A2, the virtual data line 102 close to the center of the second display area A2 in the first direction F1 can extend to the bottom of the first display area A1 along the second direction F2, and the virtual data line 102 far from the center of the second display area A2 in the first direction F1 can extend to the upper part of the second display area A2 along the second direction F2. The orthographic projection of the virtual data line 102 on the base substrate may not overlap with the orthographic projection of the first effective pixel circuit on the base substrate. However, this embodiment is not limited to this.

[0090] Figure 6 It is a partial plan view of the second display area of ​​at least one embodiment of the present disclosure. Figure 7 for Figure 6 Schematic diagram of the local cross-section along the P-P' direction. Figure 6 The planar structure of the first invalid pixel circuit in the second display area is taken as an example for illustration.

[0091] In some exemplary embodiments, Figure 6 and Figure 7 As shown, in a direction perpendicular to the display substrate, the display substrate of the second display area may include: a base substrate 30, and a semiconductor layer 41, a first conductive layer 42, a second conductive layer 43, a third conductive layer 44, and a fourth conductive layer 45 sequentially arranged on the base substrate 30. A first insulating layer 31 is arranged between the semiconductor layer 41 and the first conductive layer 42, a second insulating layer 32 is arranged between the first conductive layer 42 and the second conductive layer 43, a third insulating layer 33 is arranged between the second conductive layer 43 and the third conductive layer 44, and a fourth insulating layer 34 is arranged between the third conductive layer 44 and the fourth conductive layer 45. In some examples, the first insulating layer 31 to the fourth insulating layer 34 may all be inorganic insulating layers. The first conductive layer 42 may also be referred to as a first gate metal layer, the second conductive layer 43 may also be referred to as a second gate metal layer, the third conductive layer 44 may also be referred to as a first source-drain metal layer, and the fourth conductive layer 45 may also be referred to as a second source-drain metal layer. However, this embodiment is not limited to this.

[0092] Fig. 8A for Figure 6 A partial plan view of the second display area after the semiconductor layer is formed. Figure 8B for Figure 6 A partial plan view of the second display area after the first conductive layer is formed. Figure 8C for Figure 6 A partial plan view of the second display area after the second conductive layer is formed. Fig.8D for Figure 6 A partial plan view of the second display area after the third insulating layer is formed. Fig. 8E for Figure 6 A partial plan view of the second display area after the third conductive layer is formed. Fig.8F for Figure 6 A partial plan view of the second display area after the fourth insulating layer is formed.

[0093] Fig. 9 FIG. 4 is another partial schematic plan view of the second display area of ​​at least one embodiment of the present disclosure. Fig.10 for Fig. 9 A partial plan view of the second display area after the third conductive layer is formed. Fig. 9 and Fig.10 Schematic diagram of the first circuit area A21 and the second circuit area A22 arranged alternately in the first direction F1 in the second display area A2. The second circuit area A22 is provided with multiple columns of second pixel circuits (for example, three columns of second pixel circuits), and the first circuit area A21 is provided with one column of first pixel circuits (for example, including multiple first invalid pixel circuits). Fig. 9 and Fig.10 In the figure, a first invalid pixel circuit arranged in the first circuit area A21 and three second pixel circuits arranged in the second circuit area A22 are taken as an example for illustration.

[0094] In some exemplary embodiments, Fig. 8A and Fig. 9As shown, the semiconductor layer 41 of the second display area A2 may include at least: active layers of multiple transistors of multiple pixel circuits (for example, including: active layer 110 of the first reset transistor 11 of the first invalid pixel circuit, active layer 120 of the threshold compensation transistor 12, active layer 130 of the driving transistor 13, active layer 140 of the data writing transistor 14, active layer 150 of the first light emission control transistor 15, active layer 160 of the second light emission control transistor 16, and active layer 170 of the second reset transistor 17; active layer of the first reset transistor 21 of the second pixel circuit, active layer of the threshold compensation transistor 22, active layer of the driving transistor 23, active layer of the data writing transistor 24, active layer of the first light emission control transistor 25, active layer of the second light emission control transistor 26, and active layer of the second reset transistor 27). In this example, the active layers of the seven transistors of the pixel circuit may be an integrated structure. In some examples, the length of the channel region of the active layer of the driving transistor along the first direction F1 may be approximately 24 micrometers to 26 micrometers, for example, may be approximately 26 micrometers. However, this embodiment is not limited thereto.

[0095] In some exemplary embodiments, Figure 8B and Fig. 9 As shown, the first conductive layer 42 of the second display area A2 may include at least: gates of multiple transistors of multiple pixel circuits and a first capacitor plate of a storage capacitor (for example, the first capacitor plate 181 of the storage capacitor 18 of the first invalid pixel circuit), a scan line GL(i), a light-emitting control line EML(i), and a first reset control line (for example, a first reset control line RST1(i) and RST1(i+1)). The scan line GL(i), the light-emitting control line EML(i), and the first reset control line RST1(i) and RST1(i+1) all extend along the first direction F1, and the first reset control line RST1(i), the scan line GL(i), the light-emitting control line EML(i), and the first reset control line RST1(i+1) are arranged in sequence along the second direction F2. Wherein, i is an integer.

[0096] In some exemplary embodiments, Figure 8B and Fig. 9As shown, the first reset control line RST1(i) can be an integrated structure with the gate of the first reset transistor 21 of the second pixel circuit of the present row, the gate of the second reset transistor of the second pixel circuit of the previous row, the gate 111 of the first reset transistor 11 of the first invalid pixel circuit of the present row, and the gate of the second reset transistor of the first invalid pixel circuit of the previous row. The first reset control line RST1(i+1) can be an integrated structure with the gate of the second reset transistor 27 of the second pixel circuit of the present row, the gate of the first reset transistor of the second pixel circuit of the next row, the gate 171 of the second reset transistor 17 of the first invalid pixel circuit of the present row, and the gate of the first reset transistor of the first invalid pixel circuit of the next row. The scanning line GL(i) can be an integrated structure with the gate of the data write transistor 24 and the threshold compensation transistor 22 of the second pixel circuit of the present row, and the gate 141 of the data write transistor 14 and the first gate 121a and the second gate 121b of the threshold compensation transistor 12 of the first invalid pixel circuit of the present row. The light emitting control line EML(i) may be an integrated structure with the gates of the first light emitting control transistor 25 and the second light emitting control transistor 26 of the second pixel circuit of the row, and the gate 151 of the first light emitting control transistor 15 and the gate 161 of the second light emitting control transistor 16 of the first invalid pixel circuit of the row. The first capacitor plate 181 of the storage capacitor 18 of the first invalid pixel circuit and the gate 131 of the driving transistor 13 may be an integrated structure. The first capacitor plate of the storage capacitor 28 of the second pixel circuit and the gate of the driving transistor may be an integrated structure. However, this embodiment is not limited to this.

[0097] In some exemplary embodiments, Figure 8C and Fig. 9As shown, the second conductive layer 43 of the second display area A2 may include at least: a second capacitor plate of a storage capacitor of a plurality of pixel circuits (for example, a second capacitor plate 182 of a storage capacitor 18 of a first invalid pixel circuit), a first initial signal line INIT1(i), and a second initial signal line (for example, a second initial signal line INIT2(i-1) and INIT2(i)). The first initial signal line INIT1(i), the second initial signal line INIT2(i-1), and INIT2(i) all extend along the first direction F1, and the second initial signal line INIT2(i-1), the first initial signal line INIT1(i), and the second initial signal line INIT2(i) are sequentially arranged along the second direction F2. The orthographic projection of the first initial signal line INIT1(i) on the substrate substrate is located between the orthographic projections of the second initial signal line INIT2(i-1) and the scanning line GL(i) on the substrate substrate. The orthographic projection of the first reset control line RST1(i) on the substrate is located between the orthographic projection of the second initial signal line INIT2(i-1) and the first initial signal line INIT1(i) on the substrate. The second capacitor plates of the storage capacitors of the adjacent pixel circuits arranged along the first direction F1 may be an integrated structure. However, this embodiment is not limited to this.

[0098] In some exemplary embodiments, Figure 8C and Fig. 9As shown, the first initial signal line INIT1(i) may include a main body 201 extending along a first direction F1, a first extension 202 and a second extension 203 extending from the main body 201 along a second direction F2. The first extension 202 and the second extension 203 are located on opposite sides of the main body 201 in the second direction F2. The orthographic projection of the first extension 202 on the substrate overlaps with the orthographic projection of the channel region of the active layer 120 of the threshold compensation transistor 12 (i.e., the aforementioned first transistor) of the first invalid pixel circuit on the substrate. The channel region of the active layer 120 of the threshold compensation transistor 12 may include: a first channel region, a second channel region, and a third channel region. The orthographic projection of the first gate 121a of the threshold compensation transistor 12 on the substrate covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second gate 121b of the threshold compensation transistor 12 on the substrate covers the orthographic projection of the second channel region on the substrate. The third channel region is located between the first channel region and the second channel region. The orthographic projection of the third channel region on the substrate substrate may be L-shaped. The orthographic projection of the first extension 202 of the first initial signal line INIT1(i) on the substrate substrate overlaps with the orthographic projection of the third channel region of the active layer 120 of the threshold compensation transistor 12 on the substrate substrate. In this example, the first initial signal line may also shield the channel region of the active layer of the threshold compensation transistor of the first effective pixel circuit and the second pixel circuit of the same row. In this exemplary embodiment, shielding the channel region of the active layer of the threshold compensation transistor using the first initial signal line can ensure the stability of the performance of the threshold compensation transistor of the pixel circuit and optimize the design space of the pixel circuit.

[0099] In some exemplary embodiments, Fig.8D and Fig. 9 As shown, the third insulating layer 33 of the second display area A2 is provided with a plurality of via holes, for example, including: the third via hole K3 to the seventh via hole K7 and the ninth via hole K9 to the fourteenth via hole K14. The third insulating layer 33, the second insulating layer 32 and the first insulating layer 31 in the third via hole K3 to the seventh via hole K7 are removed, exposing the surface of the semiconductor layer 41. The third insulating layer 33 and the second insulating layer 32 in the ninth via hole K9 are removed, exposing the surface of the first conductive layer 42. The third insulating layer 33 in the tenth via hole K10 to the fourteenth via hole K14 is removed, exposing the surface of the second conductive layer 43.

[0100] In some exemplary embodiments, Fig. 8E and Fig.10As shown, the third conductive layer 44 of the second display area A2 includes at least: a plurality of connection electrodes (for example, first connection electrodes 301 and 307, second connection electrode 302, third connection electrode 303, fourth connection electrode 304, fifth connection electrodes 305 and 306, sixth connection electrode 310, seventh connection electrode 311). In some examples, the first connection electrode 301 can be electrically connected to the second extension 203 of the first initial signal line INIT1(i) through the tenth via K10. The orthographic projection of the first connection electrode 301 on the base substrate can be L-shaped, for example, an L-shaped lying downward. Another first connection electrode 307 can be electrically connected to the first initial signal line INIT1(i+1) through the fourteenth via K14. However, this embodiment is not limited to this.

[0101] In some exemplary embodiments, Fig. 8E As shown, the second connection electrode 302 can be electrically connected to the first doped region of the active layer 120 of the threshold compensation transistor 12 of the first invalid pixel circuit through the third via K3, and can also be electrically connected to the gate 131 of the driving transistor 13 through the ninth via K9. The third connection electrode 303 can be electrically connected to the first doped region of the active layer 150 of the first light emission control transistor 15 through the fourth via K4, and can also be electrically connected to the second capacitor plate 182 of the storage capacitor 18 through the eleventh via K11. The fourth connection electrode 304 can be electrically connected to the second doped region of the active layer 160 of the second light emission control transistor 16 through the fifth via K5. The fifth connection electrode 305 can be electrically connected to the first doped region of the active layer 170 of the second reset transistor 17 through the sixth via K6, and can also be electrically connected to the second initial signal line INIT2(i) through the twelfth via K12. Another fifth connection electrode 306 can be electrically connected to the first doping region of the active layer of the second reset transistor of the first invalid pixel circuit of the previous row through the seventh via hole K7, and can also be electrically connected to the second initial signal line INIT2(i-1) through the thirteenth via hole K13. Fig. 9 and Fig.10 As shown, the first doping region of the active layer of the first reset transistor 21 of the second pixel circuit can be electrically connected to the first initial signal line INIT1(i) through the sixth connection electrode 310. The first doping region of the active layer of the data writing transistor 24 of the second pixel circuit can be electrically connected to the data line through the seventh connection electrode 311.

[0102] In some exemplary embodiments, Fig.8F As shown, the fourth insulating layer 34 of the second display area is provided with a plurality of via holes, for example, including the fifteenth via hole K15 to the seventeenth via hole K17. The fourth insulating layer 34 in the fifteenth via hole K15 to the seventeenth via hole K17 is removed to expose the surface of the third conductive layer 44.

[0103] In some exemplary embodiments, Figure 6 and Fig. 9 As shown, the fourth conductive layer 45 of the second display area may include: a virtual data line 102, a plurality of data lines (e.g., data lines DL(j), DL(j+1), and DL(j+2)), a first power connection line (e.g., first power connection lines 401 and 402), and an anode connection electrode (e.g., anode connection electrodes 403 and 404). The data line and the first power connection line both extend along the second direction F2. The data line and the first power connection line are arranged at intervals along the first direction F1. However, this embodiment is not limited to this.

[0104] In some exemplary embodiments, Figure 6 and Fig. 9 As shown, the virtual data line DL can be electrically connected to the first connection electrode 301 through the fifteenth via hole K15. The first power connection line 401 can be electrically connected to the third connection electrode 303 through the sixteenth via hole K16, so as to realize the electrical connection between the first light emission control transistor 15 and the storage capacitor 18 and the first power line. The anode connection electrode 403 can be electrically connected to the fourth connection electrode 304 through the seventeenth via hole K17. Fig. 9 As shown, the data line DL(j+2) can be electrically connected to the seventh connection electrode 311, thereby realizing electrical connection with the first electrode of the data writing transistor 24 of the second pixel circuit. The first power connection line 402 can be electrically connected to the first light emission control transistor 25 and the storage capacitor 28 of the second pixel circuit through the connection electrode of the third conductive layer. The anode connection electrode 404 can be electrically connected to the second electrode of the second light emission control transistor 26 of the second pixel circuit through the connection electrode of the third conductive layer, and the anode connection electrode 404 can be electrically connected to the anode of the second light emitting element later.

[0105] In this exemplary embodiment, the first initial signal line can be electrically connected to the virtual data line 102 through the first connection electrode 301. The second pixel circuit in the same row as the first invalid pixel circuit can be electrically connected to the first initial signal line through the sixth connection electrode 310 to receive the first initial signal, and can also be electrically connected to the data line through the seventh connection electrode 311 to receive the data signal. The virtual data line 102 that overlaps with the positive projection of the first invalid pixel circuit on the substrate is electrically connected to the first initial signal line, and a mesh structure for transmitting the first initial signal can be formed in the second display area, thereby improving the stability of the first initial signal, improving the transmission stability of the first initial signal away from the driving chip, improving the signal recovery capability, improving the reset effect of the first node in the pixel circuit, and then improving the display effect of the display substrate. However, this embodiment is not limited to this. In other examples, the first connection electrode can be electrically connected to the first pole of the first reset transistor of the first invalid pixel circuit.

[0106] The connection relationship of the multiple transistors in the first invalid pixel circuit in this example can be referred to Figure 2 As shown. Since the first invalid pixel circuit does not need to drive the light emitting element, the first invalid pixel circuit may not be electrically connected to the data line, the first initial signal line or the second initial signal line. However, this embodiment is not limited to this.

[0107] The film structure of the third conductive layer of the first effective pixel circuit and the second pixel circuit in the second display area of ​​this embodiment close to the base substrate is similar to the film structure of the first invalid pixel circuit, so it is not described again.

[0108] Refer to the following Figures 6 to 10 The preparation process of the display substrate is exemplified. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0109] In some exemplary embodiments, a process of preparing a display substrate may include the following operations.

[0110] (1) Forming a semiconductor layer.

[0111] In some exemplary embodiments, forming the semiconductor layer may include: depositing a semiconductor film on the base substrate 30, patterning the semiconductor film through a patterning process, and forming a semiconductor layer 41 in the second display area A2, such as Fig. 8A The active layers of the seven transistors of a pixel circuit may be an integrated structure connected to each other.

[0112] In some exemplary embodiments, the material of the semiconductor layer 41 may include, for example, polysilicon. The active layer may include at least one channel region and a plurality of doped regions. The channel region may not be doped with impurities and may have semiconductor properties. The plurality of doped regions may be on both sides of the channel region and may be doped with impurities and may therefore be conductive. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

[0113] In some exemplary embodiments, the base substrate 30 may be a rigid substrate, such as a glass substrate. However, this embodiment is not limited thereto. For example, the base substrate may be a flexible substrate.

[0114] (2) Forming a first conductive layer.

[0115] In some exemplary embodiments, on the base substrate 30 forming the aforementioned structure, a first insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned by a patterning process to form a first insulating layer 31 covering the semiconductor layer 41, and a first conductive layer 42 disposed on the first insulating layer 31 in the second display area A2, such as Figure 8B shown.

[0116] (3) Forming a second conductive layer.

[0117] In some exemplary embodiments, on the base substrate 30 forming the aforementioned structure, a second insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned by a patterning process to form a second insulating layer 32 covering the first conductive layer 42, and a second conductive layer 43 disposed on the second insulating layer 32 in the second display area A2, such as Figure 8C shown.

[0118] (4) Forming a third insulating layer.

[0119] In some exemplary embodiments, a third insulating film is deposited on the substrate 30 on which the aforementioned pattern is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer 33, such as Fig.8D The third insulating layer 33 of the second display area A2 is provided with a plurality of via holes, for example, the plurality of via holes can expose the surfaces of the semiconductor layer 41, the first conductive layer 42 and the second conductive layer 43 respectively.

[0120] (5) Forming a third conductive layer.

[0121] In some exemplary embodiments, a third conductive film is deposited on the base substrate 30 on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer 44 on the third insulating layer 33 of the second display area A2, such as Fig. 8E and Fig.10 shown.

[0122] (6) Forming a fourth insulating layer.

[0123] In some exemplary embodiments, a fourth insulating film is deposited on the substrate 30 on which the aforementioned pattern is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 34, such as Fig.8F A plurality of via holes exposing the surface of the third conductive layer 44 are formed on the fourth insulating layer 34 of the second display area A2.

[0124] (7) Forming a fourth conductive layer.

[0125] In some exemplary embodiments, a fourth conductive film is deposited on the base substrate 30 on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer 45 on the fourth insulating layer 34 of the second display area A2, such as Figure 6 and Fig. 9 shown.

[0126] At this point, the circuit structure layer of the second display area A2 is prepared. The first display area A1 may include a base substrate 30 and a first insulating layer 31 , a second insulating layer 32 , a third insulating layer 33 and a fourth insulating layer 34 stacked on the base substrate 30 .

[0127] (8) Forming a first planar layer, a transparent conductive layer, a second planar layer, an anode layer, a pixel definition layer, an organic light emitting layer and a cathode layer in sequence.

[0128] In some exemplary embodiments, a first flat film is coated on the substrate substrate 30 forming the aforementioned pattern, and the first flat film is patterned by a patterning process to form a first flat layer. The first flat layer may be provided with a plurality of first transfer holes and a plurality of second transfer holes. The first flat layer in the first transfer hole is removed to expose the anode connection electrode of the first effective pixel circuit, and the first flat layer in the second transfer hole is removed to expose the anode connection electrode of the second pixel circuit. Subsequently, a transparent conductive film is deposited on the substrate substrate forming the aforementioned pattern, and the transparent conductive film is patterned by a patterning process to form a transparent conductive layer. The transparent conductive layer may include a transparent conductive line electrically connecting the first effective pixel circuit and the first light-emitting element. Subsequently, a second flat film is coated on the substrate substrate forming the aforementioned pattern, and the second flat film is patterned by a patterning process to form a second flat layer. Subsequently, an anode film is deposited on the substrate substrate forming the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer. Subsequently, a pixel definition film is coated on the substrate base forming the aforementioned pattern, and a pixel definition layer is formed by masking, exposure and development processes. The pixel definition layer is formed with a plurality of pixel openings exposing the anode layer. Subsequently, an organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode layer, and the cathode layer is electrically connected to the organic light-emitting layer and the second power line, respectively. In some examples, an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0129] In some exemplary embodiments, the first conductive layer 42, the second conductive layer 43, the third conductive layer 44 and the fourth conductive layer 45 may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer 31, the second insulating layer 32, the third insulating layer 33 and the fourth insulating layer 34 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer 31 and the second insulating layer 32 may be referred to as a gate insulating (GI) layer, and the third insulating layer 33 and the fourth insulating layer 34 may be referred to as an interlayer insulating (ILD) layer. The first planar layer and the second planar layer may be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The pixel definition layer may be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The anode layer may be made of reflective materials such as metal, and the cathode layer may be made of transparent conductive materials. However, this embodiment is not limited to this.

[0130] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs. For example, the circuit structure layer of the second display area may include: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged on the base substrate. However, this embodiment is not limited to this.

[0131] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and can be well compatible with existing preparation processes. The process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0132] The display substrate provided in this embodiment can form a mesh structure for transmitting the first initial signal in the second display area by electrically connecting the first initial signal line extending in the first direction and the virtual data line extending in the second direction, thereby optimizing the spatial design of the pixel circuit, thereby improving the recovery ability of the first initial signal and reducing the fluctuation of the first initial signal during reset. Moreover, by shielding the channel region of the first transistor with the first initial signal line, the stability of the gate signal of the first transistor can be ensured, and the design space of the pixel circuit can be optimized, providing support for realizing high-resolution pixel circuit design.

[0133] The embodiment of the present disclosure also provides a method for preparing a display substrate, comprising: forming a plurality of pixel circuits, at least one first initial signal line extending along a first direction, and at least one virtual data line extending along a second direction in a second display area of ​​a substrate substrate; forming a plurality of second light-emitting elements in the second display area of ​​the substrate substrate, forming a plurality of first light-emitting elements in the first display area, and the second display area at least partially surrounding the first display area. The plurality of pixel circuits include: a plurality of first effective pixel circuits, a plurality of first invalid pixel circuits, and a plurality of second pixel circuits. At least one first effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element. At least one first initial signal line is electrically connected to a plurality of pixel circuits arranged along the first direction, and is configured to provide a first initial signal to the pixel circuit. The orthographic projection of at least one virtual data line on the substrate substrate overlaps with the orthographic projection of a plurality of first invalid pixel circuits arranged along the second direction on the substrate substrate. At least one virtual data line is electrically connected to at least one first initial signal line. The first direction intersects with the second direction.

[0134] The method for preparing the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it will not be described again here.

[0135] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate as described above.

[0136] Fig.11 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.11 As shown, this embodiment provides a display device, including: a display substrate 91 and a light sensor 92 located on the light-emitting side of the display structure layer away from the display substrate 91. The orthographic projection of the light sensor 92 on the display substrate 91 overlaps with the first display area A1.

[0137] In some exemplary embodiments, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component with a display function, such as an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present disclosure are not limited thereto.

[0138] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0139] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A base substrate, comprising: a first display area and a second display area at least partially surrounding the first display area; A plurality of first light emitting elements, located in the first display area; A plurality of second light emitting elements, located in the second display area; A plurality of pixel circuits are located in the second display area; the plurality of pixel circuits include: a plurality of first effective pixel circuits, a plurality of first invalid pixel circuits and a plurality of second pixel circuits; at least one first effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element; At least one first initial signal line extending along a first direction is at least located in the second display area; the at least one first initial signal line is electrically connected to a plurality of pixel circuits arranged along the first direction, and is configured to provide a first initial signal to the pixel circuits; At least one virtual data line extending along the second direction is located in the second display area; the orthographic projection of the at least one virtual data line on the base substrate overlaps with the orthographic projection of a plurality of first invalid pixel circuits arranged along the second direction on the base substrate; the at least one virtual data line is electrically connected to the at least one first initial signal line; the first direction intersects with the second direction.

2. The display substrate according to claim 1, characterized in that: The virtual data line is electrically connected to the first initial signal line through a first connection electrode; the first connection electrode is located on a side of the first initial signal line away from the base substrate, and the virtual data line is located on a side of the first connection electrode away from the base substrate.

3. The display substrate according to claim 2, characterized in that: The orthographic projection of the first connecting electrode on the base substrate is L-shaped.

4. The display substrate according to claim 2 or 3, characterized in that: The orthographic projection of the first connecting electrode on the base substrate overlaps with the orthographic projection of the first invalid pixel circuit on the base substrate.

5. The display substrate according to claim 2, characterized in that: The display substrate of the second display area includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the base substrate; the first initial signal line is located in the second conductive layer, the first connecting electrode is located in the third conductive layer, and the virtual data line is located in the fourth conductive layer.

6. The display substrate according to claim 1, characterized in that: The pixel circuit includes: a driving transistor and a first transistor, wherein a first electrode of the first transistor is electrically connected to a gate of the driving transistor; an orthographic projection of the first initial signal line on the substrate overlaps with an orthographic projection of a channel region of an active layer of the first transistor on the substrate.

7. The display substrate according to claim 6, characterized in that: The first transistor includes a first gate and a second gate; the channel region of the active layer of the first transistor includes: a first channel region, a second channel region and a third channel region, and the third channel region is located between the first channel region and the second channel region; the orthographic projection of the first gate of the first transistor on the substrate covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second gate of the first transistor on the substrate covers the orthographic projection of the second channel region on the substrate; the orthographic projection of the first initial signal line on the substrate overlaps with the orthographic projection of the third channel region of the active layer of the first transistor on the substrate.

8. The display substrate according to claim 7, characterized in that: The third channel region of the active layer of the first transistor has an L-shape in orthographic projection on the substrate.

9. The display substrate according to any one of claims 6 to 8, characterized in that: The first initial signal line includes: a main body extending along the first direction and a first extension portion extending from the main body along the second direction; the orthographic projection of the first extension portion on the base substrate overlaps with the orthographic projection of the channel region of the active layer of the first transistor on the base substrate.

10. The display substrate according to claim 9, characterized in that: The first initial signal line further includes: a second extension portion extending from the main body along the second direction, the first extension portion and the second extension portion are located on opposite sides of the main body in the second direction; the second extension portion is electrically connected to the virtual data line through a first connection electrode.

11. The display substrate according to claim 1, characterized in that: The orthographic projection of at least one first effective pixel circuit in the second display area on the substrate does not overlap with the orthographic projection of at least one first light-emitting element in the first display area on the substrate; the orthographic projection of at least one second pixel circuit in the second display area on the substrate at least partially overlaps with the orthographic projection of at least one second light-emitting element on the substrate.

12. The display substrate according to claim 1, characterized in that: The base substrate further includes: a peripheral area located outside the display area; the display substrate further includes: a first initial peripheral wiring located in the peripheral area, and the first initial peripheral wiring is electrically connected to the at least one first initial signal line.

13. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 12.

14. A method for preparing a display substrate, characterized in that: include: forming a plurality of pixel circuits, at least one first initial signal line extending along a first direction, and at least one dummy data line extending along a second direction in a second display area of ​​the base substrate; Forming a plurality of second light-emitting elements in the second display area of ​​the base substrate, forming a plurality of first light-emitting elements in the first display area, wherein the second display area at least partially surrounds the first display area; The plurality of pixel circuits include: a plurality of first effective pixel circuits, a plurality of first invalid pixel circuits, and a plurality of second pixel circuits; at least one first effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element; The at least one first initial signal line is electrically connected to a plurality of pixel circuits arranged along the first direction, and is configured to provide a first initial signal to the pixel circuits; the orthographic projection of the at least one virtual data line on the substrate overlaps with the orthographic projection of a plurality of first invalid pixel circuits arranged along the second direction on the substrate; the at least one virtual data line is electrically connected to the at least one first initial signal line; the first direction intersects with the second direction.

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