Semiconductor device and method of forming the same

Abstract

The application discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate, a first inner connecting layer and a second inner connecting layer. The first inner connecting layer is arranged on the substrate, and the first inner connecting layer comprises a first dielectric layer surrounding a plurality of first magnetic tunnel junction structures. The second inner connecting layer is arranged on the first inner connecting layer, and the second inner connecting layer comprises a second dielectric layer surrounding a plurality of second magnetic tunnel junction structures. The second magnetic tunnel junction structures and the first magnetic tunnel junction structures are alternately arranged along a direction. The semiconductor device can obtain a reduced bit cell size and improve the element integration degree under the premise of a manufacturing process space.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method for forming the same, and more particularly to a magnetoresistive random access memory (MRAM) and a method for forming the same. BACKGROUND

[0002] Magnetoresistance (MR) effect is an effect that the resistance of a material changes with the change of an applied magnetic field. The physical quantity is defined as the difference between the resistances with and without a magnetic field divided by the original resistance, which represents the resistance change rate. Currently, the MR effect has been successfully applied in the production of hard disks, which has important commercial application value. In addition, using the characteristics of giant magnetoresistance materials having different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of continuing to retain stored data without power.

[0003] The above-mentioned MR effect is also applied in the field of magnetic field sensors, for example, an electronic compass component in a mobile phone with a global positioning system (GPS) to provide the user with information about the direction of movement. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and susceptible to temperature changes, etc., and further improvement is necessary. SUMMARY

[0004] An object of the present application is to provide a semiconductor device, which arranges misaligned magnetic tunneling junction sensing elements in different inner connection layers, thereby reducing the bit cell height of the semiconductor device and improving the element integration of the semiconductor device.

[0005] One object of the present application is to provide a semiconductor device and a method of forming the same, which defines two inner connection lines arranged below a magnetic tunnel junction sensing element by a self-aligned merge process, thereby overcoming a size bottleneck of a conventional process. The semiconductor device of the present application can achieve a reduced bit cell line height and improved element integration under a space constraint of a process.

[0006] To achieve the above object, one preferred embodiment of the present application provides a semiconductor device, which includes a substrate, a first inner connection layer, and a second inner connection layer. The first inner connection layer is arranged on the substrate, and includes a first dielectric layer surrounding a plurality of first magnetic tunnel junction structures. The second inner connection layer is arranged on the first inner connection layer, and includes a second dielectric layer surrounding a plurality of second magnetic tunnel junction structures. The second magnetic tunnel junction structures and the first magnetic tunnel junction structures are alternately arranged along a direction.

[0007] To achieve the above object, another preferred embodiment of the present application provides a method of forming a semiconductor device, which includes the following steps. First, a substrate is provided, and a first inner connection layer is formed on the substrate. The first inner connection layer includes a first dielectric layer surrounding a plurality of first metal inner connection lines. Then, a second inner connection layer is formed on the first inner connection layer. The second inner connection layer includes a second dielectric layer surrounding a plurality of second metal inner connection lines and a plurality of third metal inner connection lines. The formation of the second inner connection layer further includes the following steps. First mask patterns are formed on the second dielectric layer. The first mask patterns are arranged according to a first pitch. Second mask patterns are formed on the first mask patterns. The second mask patterns are arranged according to a second pitch, which is greater than the first pitch. An etching process is performed through the second mask patterns and the first mask patterns. First openings are formed through the second dielectric layer, and second openings are formed in the second dielectric layer. The second metal inner connection lines and the third metal inner connection lines are formed in the first openings and the second openings. Then, a third inner connection layer is formed. The third inner connection layer includes a third dielectric layer surrounding a plurality of first magnetic tunnel junction structures.

[0008] In summary, the method for forming the semiconductor device of the present application integrates the manufacturing processes of two interconnection layers (e.g. the first contact hole layer and the second metal interconnection layer) to simultaneously form the metal interconnections in the first contact hole layer and the second metal interconnection layer by using a self-aligned combination manufacturing process, thereby avoiding the formation of a critical dimension photoresist pattern by using a photolithography imaging manufacturing process, and improving the problem of manufacturing process space shortage caused by reducing the height of the bit cell line of the semiconductor device. In addition, the magnetic storage structure of the semiconductor device can be alternately arranged in the two interconnection layers, so that the minimum arrangement line width / interval of each magnetic storage structure and other metal interconnections arranged in the two interconnection layers can be correspondingly expanded. Therefore, the semiconductor device of the present application can effectively reduce the height of the bit cell line of the semiconductor device under the premise of manufacturing process permission, improve the element integration of the semiconductor device and maintain the operation performance of the overall device. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a top view schematic diagram of the layout of a semiconductor device in the first embodiment of the present application;

[0010] Figure 2 is a cross-sectional view along the tangent line A-A' in the first embodiment of the present application; Figure 1

[0011] Figure 3 is a top view schematic diagram of the layout of a semiconductor device in the second embodiment of the present application;

[0012] Figure 4 is a cross-sectional view along the tangent line B-B' in the second embodiment of the present application; Figure 3

[0013] Figures 5 to 8 is a cross-sectional view of the method for forming a semiconductor device in the second embodiment of the present application, wherein:

[0014] Figure 5 is a cross-sectional view of a semiconductor device after forming a first mask pattern;

[0015] Figure 6 is a cross-sectional view of a semiconductor device after forming a second mask pattern;

[0016] Figure 7 is a cross-sectional view of a semiconductor device after performing an etching manufacturing process; and

[0017] Figure 8 is a cross-sectional view of a semiconductor device after forming a conductor;

[0018] Figure 9 is a top view schematic diagram of the layout of a semiconductor device in the third embodiment of the present application;

[0019] ​​Figure 10 Fig. 2 is a cross-sectional view along the tangent C-C' of Fig. 1; Figure 9 Fig. 3 is a cross-sectional view along the tangent C-C' of Fig. 1;

[0020] Figures 11 to 13 Fig. 4 is a cross-sectional view along the tangent C-C' of Fig. 1, showing a method of forming a semiconductor device according to a third embodiment of the present application;

[0021] Figure 11 Fig. 5 is a cross-sectional view along the tangent C-C' of Fig. 1, showing a method of forming a semiconductor device according to a fourth embodiment of the present application;

[0022] Figure 12 Fig. 6 is a cross-sectional view along the tangent C-C' of Fig. 1, showing a method of forming a semiconductor device according to a fifth embodiment of the present application;

[0023] Figure 13 Fig. 7 is a cross-sectional view along the tangent C-C' of Fig. 1, showing a method of forming a semiconductor device according to a sixth embodiment of the present application;

[0024] Figure 14 Fig. 8 is a plan view of a layout of a semiconductor device according to another embodiment of the present application;

[0025] Figure 15 Fig. 9 is a plan view of a layout of a semiconductor device according to a fourth embodiment of the present application.

[0026] Explanation of Main Elements

[0027] 100 substrate

[0028] 101, 102, 103, 104 magnetic random access memory region

[0029] 110 doped region

[0030] 120 gate structure

[0031] 130 interlayer dielectric layer

[0032] 131, 431 plug

[0033] 140, 150, 160, 170, 190 intermetal dielectric layer

[0034] 141, 151, 161, 161a metal interconnect

[0035] 171, 175, 177 metal interconnect

[0036] 173 magnetic memory structure

[0037] 191 word line

[0038] 201, 301 mask pattern

[0039] 203, 303 barrier layer

[0040] 205, 305 mask pattern

[0041] 250, 260, 270, 280 intermetal dielectric layer

[0042] 251, 253, 253a metal interconnect

[0043] 252, 254 opening

[0044] 261, 263, 267 metal interconnect

[0045] 265, 275 magnetic storage structure

[0046] 271, 273, 277 metal interconnect

[0047] 281, 283 metal interconnect

[0048] 340, 350 intermetal dielectric layer

[0049] 341, 341a metal interconnect

[0050] 351, 353 metal interconnect

[0051] 352, 354 opening

[0052] 410 doped region

[0053] 410a connection

[0054] P1, P2, P3, P4, P5a, P5b, P6 pitch

[0055] P21, P22, P51, P52 pitch

[0056] S1, S2, S3, S4, S5a, S5b, S6 spacing

[0057] S21, S22, S51, S52 spacing

[0058] W1, W2, W3, W4, W5a, W5b, W6 line width

[0059] W21, W22, W51, W52 line width DETAILED DESCRIPTION

[0060] In order to enable one of ordinary skill in the art to better understand the present application, several preferred embodiments of the present application are listed below, and the configuration content and the desired effects of the present application are described in detail with the help of the accompanying drawings.

[0061] Please refer to Figure 1 and Figure 2Fig. 1 shows a schematic diagram of a semiconductor device according to a first embodiment of the present application, Figure 1 Fig. 2 shows a top view of a layout of the semiconductor device, Figure 2 Fig. 3 shows a cross-sectional view of the semiconductor device. The semiconductor device, for example, is a magnetic random access memory (MRAM) device, which mainly comprises a substrate 100, for example, a substrate composed of a semiconductor material selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. The substrate 100 preferably defines a MRAM region 101 and a logic region (not shown) thereon. The MRAM region 101 in detail comprises a plurality of doped regions (DF) 110, each of which extends along a same direction (e.g. X direction) parallel to each other and is separated by a plurality of shallow trench isolations (STI) 100a, as shown in Fig. 1. Figure 2

[0062] The MRAM region 101 further comprises a plurality of metal-oxide semiconductor (MOS) transistors, which are, for example, planar or non-planar (e.g. fin-type) transistor elements. Specifically, the MOS transistors are formed by a plurality of gate structures (e.g. metal gates) 120 extending along another same direction (e.g. Y direction) across the doped regions 110, and the doped regions 110 on both sides of each gate structure 120 can be used as the source / drain (not shown) of the MOS transistors, respectively. The planar or non-planar transistor elements and related fabrication processes are well known in the art and will not be described here.

[0063] ​A layer of inter-layer dielectric layer 130 is disposed on the substrate 100 to cover the metal oxide semiconductor transistors. A plurality of plugs 131 are further disposed in the inter-layer dielectric layer 130 to electrically connect the source / drain of the metal oxide semiconductor transistors 120, respectively. A plurality of multi-layered interconnect layers are further disposed above the inter-layer dielectric layer 130. A plurality of metal interconnects 141 are disposed on the inter-layer dielectric layer 130 and connected to the plugs 131, and an inter-metal dielectric layer 140 is disposed around the metal interconnects 141. A plurality of metal interconnects 151 are disposed on the inter-metal dielectric layer 140 and connected to the metal interconnects 141, and an inter-metal dielectric layer 150 is disposed around the metal interconnects 151. A plurality of metal interconnects 161, 161a are disposed on the inter-metal dielectric layer 150 and connected to the metal interconnects 151, and an inter-metal dielectric layer 160 is disposed around the metal interconnects 161, 161a. It is noted that the metal interconnect 161a is a source line (SL) and is electrically connected to the source of the metal oxide semiconductor transistors via the metal interconnects 141 and the plugs 131. For example, each of the metal interconnects 141, 161, 161a preferably comprises a trench conductor, the metal interconnects 141 are a first layer of metal interconnects (metal 1, M1), and the metal interconnects 161, 161a are a second layer of metal interconnects (metal 2, M2). Each of the metal interconnects 151 preferably comprises a contact hole conductor and is a first layer of contact holes (via 1, V1).

[0064] Next, a plurality of metal interconnects 171, a plurality of magnetic storage structures 173, a plurality of metal interconnects 175, and a plurality of metal interconnects 177 are sequentially disposed on the intermetal dielectric layer 160 and connect the metal interconnects 161, at least one intermetal dielectric layer 170 surrounds the metal interconnects 171, the magnetic storage structures 173, the metal interconnects 175, and the metal interconnects 177; a word line 191 is disposed in an intermetal dielectric layer 190 and is located above the intermetal dielectric layer 170, the word line 191 is not electrically connected to the metal interconnects 177 below, but is electrically connected to the gate structure 120 of the metal oxide semiconductor transistor through an additional interconnection layer (not shown). For example, each of the metal interconnects 171, 175 preferably includes a contact hole conductor, respectively as a second layer via 2 and a third layer via 3; the metal interconnect 177 preferably includes a trench conductor as a fourth layer metal 4. Among them, the magnetic storage structure 173 is, for example, a magnetic tunnel junction (MTJ) structure, and the aforementioned interconnection layers are sequentially disposed between the drain (i.e. doped region 110) of the metal oxide semiconductor transistor and the magnetic storage structure 173, so that the drain can be electrically connected to the magnetic storage structure 173. It should be noted that, Figure 1 In order to clearly distinguish the specific layout pattern, not all of the interconnection layers are completely drawn, only the first layer metal interconnect layer (i.e. metal interconnect 141), the first layer via layer (i.e. metal interconnect 151), the second layer metal interconnect layer (i.e. metal interconnect 161), and the magnetic storage structure 173 are drawn, and the interconnection layers that are positionally overlapped and located below are also omitted, such as the interconnection layers disposed immediately below the magnetic storage structure 173.

[0065] In some embodiments, the magnetic storage structure 173 preferably includes a lower electrode, a pinned layer (not shown), a barrier layer (not shown), a free layer (not shown), and an upper electrode sequentially stacked from bottom to top. The lower electrode and the upper electrode preferably comprise a conductive material, such as but not limited to tantalum (Ta), platinum (Pt), copper, gold (Au), aluminum; the pinned layer can be composed of an antiferromagnetic (AFM) material, such as including iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the direction of the magnetic moment of the adjacent layer; the barrier layer can be composed of an insulating material containing oxide, such as including aluminum oxide (AlO x) or magnesium oxide (MgO); the free layer can be composed of a ferromagnetic material, such as including iron, cobalt, nickel, or an alloy thereof, such as cobalt-iron-boron (CoFeB), but not limited thereto.

[0066] It is particularly noted that the semiconductor device of the present embodiment is to arrange the source line (i.e. metal interconnect 161a) in the second layer metal interconnect layer, so that the line width (W) W1 and the space (S) S1 between the metal interconnects 161, 161a are relatively tight, for example, the line width / space (W1 / S1) is about 50 nanometers (nm) / 50 nanometers, and the pitch P1 of the metal interconnect 161 is about 100 nanometers. In this case, the minimum line width / space of the interconnection layers (including metal interconnects 151, 171, 175 and magnetic storage structure 173) above and below the second layer metal interconnect layer will be affected by the line width / space of the metal interconnect 161, and need to meet the arrangement condition that the line width / space (W / S) is about 50 nanometers, as shown in Figure 2 It is particularly noted that the semiconductor device of the present embodiment is to arrange the source line (i.e. metal interconnect 161a) in the second layer metal interconnect layer, so that the line width (W) W1 and the space (S) S1 between the metal interconnects 161, 161a are relatively tight, for example, the line width / space (W1 / S1) is about 50 nanometers (nm) / 50 nanometers, and the pitch P1 of the metal interconnect 161 is about 100 nanometers. In this case, the minimum line width / space of the interconnection layers (including metal interconnects 151, 171, 175 and magnetic storage structure 173) above and below the second layer metal interconnect layer will be affected by the line width / space of the metal interconnect 161, and need to meet the arrangement condition that the line width / space (W / S) is about 50 nanometers, as shown in

[0067] In short, the semiconductor device of the present embodiment is a two-transistor one-resistor (2T1R) bit cell to improve the driving current value, and the line width and line height of the bit cell are limited to a certain extent, so that the semiconductor device can have a certain element integration. The semiconductor device is arranged with the source line in the second layer metal interconnect layer, so that the minimum line width / space of the metal interconnect 161, the metal interconnect 151, 171, 175 and the magnetic storage structure 173 are about 50 nanometers / 50 nanometers, to reduce the bit cell line height of the semiconductor device, and thus improve the element integration of the semiconductor device.

[0068] Those having ordinary skill in the art should readily understand that other modifications and changes can be made to the semiconductor device of the present application to enable it to be used to meet the needs of actual products, without departing from the spirit and scope of the present application. For example, in the above-mentioned embodiments, the semiconductor device can achieve a reduced bit cell height, but the current manufacturing process has limited space, and it is not conducive to form the inner connection layers (including the metal inner connection layers 151, 171, 175 and the magnetic storage structure 173) with a minimum line width / interval of about 50 nm / 50 nm, which can affect the overall device performance. Therefore, according to another embodiment of the present application, another semiconductor device and a method for forming the same can be further provided, which can enable the semiconductor device to have a reduced bit cell height and improved element integration under the premise of allowing the manufacturing process space. Hereinafter, other embodiments or variations of the semiconductor device will be further described. For simplicity, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeated. In addition, the same elements in the embodiments of the present application are marked with the same reference numerals for ease of mutual comparison between the embodiments.

[0069] Please refer to Figures 3 to 8 which illustrates a schematic diagram of a semiconductor device in a second embodiment of the present application, wherein, Figure 3 is a top view of the layout of the semiconductor device, Figure 4 is a cross-sectional view of the semiconductor device, and Figure 5 and Figure 8 are schematic diagrams of part of the manufacturing process of the semiconductor device, respectively. The semiconductor device is also, for example, a magnetic random storage device, and includes a substrate 100, a doped region 110, a shallow trench isolation 100a, a gate structure 120, a plug 131 disposed in an interlayer dielectric layer 130, a first layer of metal inner connection layers (including a metal inner connection layer 141 disposed in an intermetal dielectric layer 140), and a word line 191 disposed in an intermetal dielectric layer 190. The substrate 100 preferably defines a magnetic random storage device region 102 and a logic region, and the same parts will not be repeated. It should be noted that, Figure 3 In order to clearly distinguish the specific layout pattern, not all inner connection layers are completely drawn, and the inner connection layers that are completely overlapped and located below are not completely drawn.

[0070] A plurality of metal interconnects 251, 253, 253a are further disposed in the magnetic random access memory region 102, on the first layer of metal interconnects and electrically connected to the metal interconnects 141, respectively. An inter-metal dielectric layer 250 is disposed around the metal interconnects 251, 253, 253a. It is to be noted that in the present embodiment, the metal interconnects 251, 253, 253a are embedded in the inter-metal dielectric layer 250 according to a self-aligned merge process. The details of the self-aligned merge process include the following steps. First, as shown in FIG. 2A, the inter-metal dielectric layer 250 is formed on the first layer of metal interconnects, and the inter-metal dielectric layer 250 has a top surface that is planar in its entirety. A plurality of mask patterns 201 are formed on the top surface of the inter-metal dielectric layer 250. Preferably, each mask pattern 201 has the same line width / spacing (W21 / S21), for example, about 50 nm, so that the pitch P21 of the mask patterns 201 is about 100 nm, but not limited thereto. Figure 5 Next, as shown in FIG. 2B, a barrier layer 203 is formed on the mask patterns 201 to cover all of the mask patterns 201. A plurality of mask patterns 205 are formed on the barrier layer 203 by a photolithography process. Preferably, each mask pattern 205 has a relatively larger line width / spacing (W22 / S22), for example, about 110 nm / 190 nm, so that the pitch P22 of the mask patterns 205 is about 300 nm, but not limited thereto. In an embodiment, the mask patterns 201 can include a hard mask material, preferably including a group consisting of silicon nitride (SiN), titanium nitride (TiN), or silicon carbon nitride (SiCN); the barrier layer 203 preferably includes a bottom anti-reflective coating (BARC) layer or an amorphous carbon (APF) layer; and the mask patterns 205 preferably include a photoresist material, but not limited thereto. Figure 6 Next, as shown in FIG. 2B, a barrier layer 203 is formed on the mask patterns 201 to cover all of the mask patterns 201. A plurality of mask patterns 205 are formed on the barrier layer 203 by a photolithography process. Preferably, each mask pattern 205 has a relatively larger line width / spacing (W22 / S22), for example, about 110 nm / 190 nm, so that the pitch P22 of the mask patterns 205 is about 300 nm, but not limited thereto. In an embodiment, the mask patterns 201 can include a hard mask material, preferably including a group consisting of silicon nitride (SiN), titanium nitride (TiN), or silicon carbon nitride (SiCN); the barrier layer 203 preferably includes a bottom anti-reflective coating (BARC) layer or an amorphous carbon (APF) layer; and the mask patterns 205 preferably include a photoresist material, but not limited thereto. Figure 7As shown, an etching process is performed under the sequential coverage of mask pattern 205, barrier layer 203, and mask pattern 201. After etching the intermetallic dielectric layer 250, mask pattern 205, barrier layer 203, and mask pattern 201 are completely removed. The intermetallic dielectric layer 250 hidden beneath mask pattern 201 cannot be etched, while the intermetallic dielectric layer 250 hidden beneath mask pattern 205 has its etching process slowed, forming multiple openings 254 that do not penetrate the intermetallic dielectric layer 250. The intermetallic dielectric layer 250 not hidden beneath mask pattern 201 or mask pattern 205 is removed, forming multiple openings 252 that penetrate the intermetallic dielectric layer 250. Subsequently, as... Figure 8 As shown, a deposition process and a planarization process are performed sequentially to form a conductor filling openings 252 and 254. In one embodiment, the conductor includes a barrier layer (not shown) and a conductive layer (not shown) sequentially deposited within openings 252 and 254. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride, tantalum (Ta), and tantalum nitride (TaN), while the conductive layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., preferably including copper, but not limited thereto.

[0071] Thus, the conductors located in the lower half and upper half of opening 252 respectively constitute metal interconnects 251 and 253, while the conductor located in opening 254 constitutes metal interconnect 253a. Metal interconnect 251 serves as the first contact hole layer (V1), while metal interconnects 253 and 253a serve as the second metal interconnect layer (M2). Metal interconnect 253a, as a source line, can also be electrically connected to the source of the metal-oxide-semiconductor transistors via metal interconnect 141 and plug 131. In other words, this embodiment utilizes the self-aligned merging fabrication process to form the metal interconnects 251, 253, and 253a, improving the problem of tight fabrication processes. This allows the linewidth / spacing (W2 / S2) between the formed metal interconnects 253 and 253a to be the linewidth / spacing (W21 / S21) of the mask pattern 201, for example, approximately 50 nanometers / 50 nanometers, while the spacing P2 between the metal interconnects 253 and 253a is approximately 100 nanometers. In this case, the first contact hole layer (metal interconnect 251) and the second metal interconnect layer (metal interconnect 253) of this embodiment can be integrally formed and have a reduced minimum linewidth / spacing.

[0072] Next, multiple metal interconnects 261, multiple magnetic storage structures 265, multiple metal interconnects 263, and multiple metal interconnects 267 are alternately disposed on the inter-metal dielectric layer 250 and connected to each metal interconnect 253. At least one inter-metal dielectric layer 260 surrounds the metal interconnects 261, magnetic storage structures 265, metal interconnects 263, and metal interconnects 267. Specifically, the metal interconnects 261 and 263 are arranged sequentially on each metal interconnect 253 in an adjacent order. Magnetic storage structures 265 and metal interconnects 267 are respectively disposed above the metal interconnects 261 and 263, as shown below. Figure 4 As shown. Preferably, each metal interconnect 261 and 263 includes a contact hole conductor, serving as the second carrier layer (W2) and the second contact hole layer (V2), respectively; metal interconnect 267 preferably includes a trench conductor, serving as the third metal interconnect layer (M3). Furthermore, multiple metal interconnects 273, multiple metal interconnects 277, multiple metal interconnects 271, and multiple magnetic storage structures 275 are alternately disposed on the inter-metal dielectric layer 260 and respectively connect each magnetic storage structure 265 to each metal interconnect 267. At least one inter-metal dielectric layer 270 surrounds the metal interconnects 273, metal interconnects 277, metal interconnects 271, and magnetic storage structures 275. In detail, the metal interconnects 273 and 271 are sequentially arranged on each magnetic storage structure 265 and each metal interconnect 267 in an adjacent order of one metal interconnect 273 to one metal interconnect 271. Above the metal interconnects 273 and 271, the metal interconnects 277 and the magnetic storage structure 275 are respectively arranged. Figure 4 As shown. Preferably, each metal interconnect 273 and 271 includes a contact hole conductor, serving as the third contact hole layer (V3) and the third carrier layer (W3), respectively; metal interconnect 277 preferably includes a trench conductor, serving as the fourth metal interconnect layer (M4). Then, multiple metal interconnects 281 and multiple metal interconnects 283 are sequentially disposed on the inter-metal dielectric layer 270 and connected to each magnetic storage structure 275, with at least one inter-metal dielectric layer 280 surrounding the metal interconnects 281 and 283. Preferably, each metal interconnect 281 includes a contact hole conductor, serving as the fourth contact hole layer (V4), while the metal interconnect 283 preferably includes a trench conductor, serving as the fifth metal interconnect layer (M5).

[0073] In this embodiment, the magnetic storage structures 265, 275 can also be magnetic tunnel junction structures. The magnetic storage structures 265, 275 can be electrically connected to the drain (i.e., the doped region 110) of the metal oxide semiconductor transistor through the aforementioned inner connection layers. The magnetic storage structures 265 are alternately arranged with the metal interconnects 267 in the intermetal dielectric layer 260, and the magnetic storage structures 275 are alternately arranged with the metal interconnects 277 in the intermetal dielectric layer 270. In other words, the magnetic storage structures 265, 275 are arranged in different inner connection layers and alternately arranged along a direction (e.g., the X direction). In this way, the minimum line width / interval (W3 / S3) of each magnetic storage structure 265 and each magnetic storage structure 275 can be expanded to about 50 nm / 250 nm, and the pitch P3 of each magnetic storage structure 265 and each magnetic storage structure 275 is about 300 nm, but not limited thereto. At the same time, the minimum line width or minimum interval of other metal interconnects (including the metal interconnects 261, 263, 267, 271, 273, 277) arranged in the intermetal dielectric layer 260 or the intermetal dielectric layer 270 can also be expanded accordingly, as shown in FIG. 3B. In this way, the manufacturing process of the magnetic storage structures 265, 275 and other metal interconnects arranged in the same layer of the inner connection layer is no longer limited by the manufacturing process space. Those skilled in the art should understand that the detailed structure of the magnetic storage structures 265, 275 in this embodiment is basically the same as that of the magnetic storage structures 173 in the aforementioned embodiment, and thus will not be described again. Figure 4

[0074] In short, the semiconductor device of this embodiment integrates the manufacturing processes of the first layer of contact hole layer (metal interconnect 251) and the second layer of metal interconnect layer (metal interconnects 253, 253a), and simultaneously forms the metal interconnects 251, 253, 253a using the self-aligned merging manufacturing process, thereby avoiding the formation of a critical dimension photoresist pattern using a photolithographic imaging manufacturing process, and thus improving the aforementioned manufacturing process urgency problem. In addition, the semiconductor device of this embodiment alternately arranges the magnetic storage structures 265, 275 in different inner connection layers, so that the minimum line width / interval of each magnetic storage structure 265, 275 and other metal interconnects (including the metal interconnects 261, 263, 267, 271, 273, 277) arranged in the intermetal dielectric layer 260 or the intermetal dielectric layer 270 can be expanded accordingly. In this way, the manufacturing process of the magnetic storage structures 265, 275 and other metal interconnects arranged in the same layer of the inner connection layer is no longer limited by the manufacturing process space urgency. Under this arrangement, the bit cell line height of the semiconductor device can be effectively reduced under the premise of manufacturing process permission, thereby improving the element integration of the semiconductor device and maintaining the operation performance of the overall device. ​

[0075] Referring to Figures 9 to 13 Fig. 3 shows a schematic diagram of a semiconductor device in a third embodiment of the present application, wherein Figure 9 Fig. 4 is a top view of a layout of the semiconductor device, Figure 10 Fig. 5 is a cross-sectional view of the semiconductor device, and Figure 11 Fig. 6 is a schematic diagram of a partial fabrication process of the semiconductor device, and Figure 13 Fig. 7 is a schematic diagram of another partial fabrication process of the semiconductor device, wherein Figure 9 For clarity, not all the interconnect layers are shown. The semiconductor device is also a magnetic random access memory device, and includes a substrate 100, shallow trench isolation 100a, doped regions 110, gate structures 120, plugs 131 disposed in an interlayer dielectric layer 130, a second level contact hole layer (i.e., metal interconnects 171), magnetic storage structures 173, a third level contact hole layer (i.e., metal interconnects 175), a fourth level metal interconnect layer (i.e., metal interconnects 177), and word lines 191 disposed in an intermetal dielectric layer 190. The substrate 100 preferably defines a magnetic random access memory device region 103 and a logic region. The same features are not described again.

[0076] The main difference between this embodiment and the previous embodiments is that the source lines are disposed in the first level metal interconnect layer (Ml). In detail, a plurality of metal interconnects 341, 341a are disposed on the interlayer dielectric layer 130 and connected to the plugs 131, and an intermetal dielectric layer 340 surrounds the metal interconnects 341, 341a. The metal interconnects 341, 341a preferably include a trench conductor, such that the metal interconnects 341 serve as the first level metal interconnect layer, and the metal interconnects 341a serve as the source lines. The source lines are electrically connected to the sources of the metal oxide semiconductor transistors via the plugs 131, respectively. In this embodiment, since the source lines (i.e., metal interconnects 341a) are disposed in the first level metal interconnect layer, the line width / spacing (W4 / S4) of the metal interconnects 341, 341a is more critical, for example, about 50 nm / 50 nm, and the pitch P4 of the metal interconnects 341, 341a is about 100 nm, as shown in Figure 10 Fig. 8.

[0077] A plurality of metal interconnects 351, 353 are further disposed on the first layer of metal interconnects and are respectively electrically connected to the metal interconnects 341, and an inter-metal dielectric layer 350 surrounds the metal interconnects 351, 353. It is particularly noted that, in order to avoid the minimum line width / spacing of the interconnect layer above the first layer of metal interconnects being affected by the line width / spacing (W4 / S4) of the metal interconnects 341, 341a, the metal interconnects 351, 353 can be embedded in the inter-metal dielectric layer 350 according to a self-aligned damascene fabrication process. The self-aligned damascene fabrication process is substantially the same as that in the foregoing embodiments, and in detail includes the following steps. First, as shown in FIG. 3A, a plurality of mask patterns 301, a barrier layer 303 covering all the mask patterns 301, and a plurality of mask patterns 305 are sequentially formed on the inter-metal dielectric layer 350 having a planar top surface. Among them, each mask pattern 301 preferably has a relatively small line width / spacing (W51 / S51), for example, about 50 nm / 100 nm, so that the pitch P51 of the mask patterns 301 is about 150 nm; each mask pattern 305 preferably has a relatively large line width / spacing (W52 / S52), for example, about 110 nm / 190 nm, so that the pitch P52 of the mask patterns 305 can be expanded to about 300 nm, but not limited thereto. In addition, the materials of the mask patterns 301, the barrier layer 303, and the mask patterns 305 are substantially the same as those of the mask patterns 201, the barrier layer 203, and the mask patterns 205 in the foregoing embodiments, and will not be described here. Then, as shown in FIG. 3B, an etching fabrication process is performed under the sequential coverings of the mask patterns 305, the barrier layer 303, and the mask patterns 301, and after etching the inter-metal dielectric layer 350, the mask patterns 305, the barrier layer 303, and the mask patterns 301 are completely removed. Among them, the inter-metal dielectric layer 350 under the mask patterns 301 is not etched, the inter-metal dielectric layer 350 under the mask patterns 305 is delayed in etching, forming a plurality of openings 354 that do not penetrate the inter-metal dielectric layer 350, and the inter-metal dielectric layer 350 not covered by the mask patterns 301 or the mask patterns 305 is removed, forming a plurality of openings 352 that penetrate the inter-metal dielectric layer 350, and each opening 352 can be in communication with each opening 354. Subsequently, as shown in FIG. 3C, a deposition fabrication process and a planarization fabrication process are sequentially performed to form a conductor filling the openings 352 and the openings 354, and the material of the conductor can also be the same as that in the foregoing embodiments, and will not be described here. Figure 11 Figure 12 Figure 13

[0078] ​​​Thus, the conductor located in the lower half of the opening 352 forms the metal interconnect 351, and the conductor located in the upper half of the opening 352 and in the opening 354 collectively forms the metal interconnect 353, such that the metal interconnect 351 serves as a first layer contact via layer (Vl) and the metal interconnect 353 serves as a second layer metal interconnect layer (M2). That is, the metal interconnects 351, 353 are formed by the self-aligned merging fabrication process of the present embodiment, which improves the fabrication process margin, such that the line width / spacing (W5a / S5a) of the metal interconnect 351 can be scaled to about 70 nm / 50 nm, and the line width / spacing (W5b / S5b) of the metal interconnect 353 can be scaled to about 100 nm / 50 nm, such that the pitch P5a, P5b of the metal interconnects 351, 353 is about 120 nm, 150 nm, respectively, but not limited thereto. In this case, the first layer contact via layer (metal interconnect 351) and the second layer metal interconnect layer (metal interconnect 353) of the present embodiment can be formed integrally, and the minimum line width / spacing of the metal interconnects 351, 353 can not be affected by the fabrication process margin, but can have a relatively large minimum line width / spacing.

[0079] On the other hand, the magnetic storage structure of the present embodiment can be optionally disposed in the same layer interconnect layer as the first embodiment described above. For example, referring to Figure 10 As shown, the magnetic storage structure 173 is disposed in the intermetal dielectric layer 170 and electrically connected to the drain (i.e., doped region 110) of the metal oxide semiconductor transistors through the metal interconnects 171, 353, 351, 341 and the plug 131. Thus, the minimum line width / spacing (W6 / S6) of the magnetic storage structure 173 is about 50 nm / 100 nm, for example, and the pitch P6 of the magnetic storage structure 173 is about 150 nm, but not limited thereto. However, in another embodiment, the magnetic storage structure can be optionally disposed in different layer interconnect layers as the second embodiment described above. For example, referring to Figure 14 As shown, the magnetic storage structure 265 is alternately disposed with the metal interconnect 267 in the intermetal dielectric layer 260, and the magnetic storage structure 275 is alternately disposed with the metal interconnect 277 in the intermetal dielectric layer 270. Thus, the magnetic storage structures 265, 275 are disposed in different layer interconnect layers, such that the minimum line width / spacing (W3 / S3) of each magnetic storage structure 265, 275 can be scaled to about 50 nm / 250 nm, and the pitch P3 of each magnetic storage structure 265, 275 is about 300 nm, but not limited thereto. Thus, the magnetic storage structures 265, 275 and other metal interconnects disposed in the same layer interconnect layer can have a relatively large fabrication process margin.

[0080] Briefly, the semiconductor device of the present embodiment changes the source line to be disposed in the first metal interconnect layer, and simultaneously forms the first contact hole layer (metal interconnect 351) and the second metal interconnect layer (metal interconnect 353) by using the self-aligned merge fabrication process, so as to avoid the fabrication process space of the metal interconnects 351, 353 from being affected by the line width / interval (W4 / S4) of the first metal interconnect layer. Moreover, the semiconductor device of the present embodiment can choose to dispose the magnetic storage structure in the same layer of interconnect layer, so as to further reduce the bit cell line height of the semiconductor device, or can also choose to dispose the magnetic storage structure in different layers of interconnect layer, so as to obtain a more generous fabrication process space for the magnetic storage structure and other metal interconnects disposed in the same layer of interconnect layer.

[0081] Referring to Figure 15 , a top view of the layout of a semiconductor device in a fourth embodiment of the present application is shown, wherein, in order to clearly distinguish specific layout patterns, Figure 15 not all of the interconnect layers are completely drawn. The semiconductor device is also, for example, a magnetic random storage device, and comprises a substrate 100, a gate structure 120, a first metal interconnect layer (i.e. metal interconnects 341, 341a), a first contact hole layer (i.e. metal interconnects 351), a second metal interconnect layer (metal interconnects 353), and a magnetic storage structure 173. The substrate 100 is preferably defined with a magnetic random storage device region 104 and a logic region, and the same parts will not be described again.

[0082] The main difference between the present embodiment and the foregoing embodiments is that the plurality of doped regions 410 extending along the same direction (e.g. X direction) are connected to each other by a plurality of connection portions 410a, which can present an H-shaped structure, as shown in Figure 15 . The gate structure 120 also spans each doped region 410 to form a plurality of metal-oxide-semiconductor transistors, and the doped regions 410 located on both sides of each gate structure 120 can be used as the source / drain (not shown) of the metal-oxide-semiconductor transistors, respectively. Under this arrangement (H-shaped doped regions), the number and positions of the plugs can be correspondingly reduced, for example, the plugs originally disposed above each doped region 410 can be omitted, and the plugs 431 can be disposed above the connection portions 410a. In this way, the number of the first metal interconnect layer (i.e. metal interconnects 341, 341a) can also be correspondingly reduced, for example, the metal interconnects 341 originally disposed above each doped region 410 can be omitted, as shown in Figure 15 , but not limited thereto.

[0083] Briefly, the semiconductor device of the present embodiment is provided with the H-shaped doped regions 410, 410a, thereby reducing the number and locations of the plug 431 and the first metal interconnect layer (i.e., the metal interconnects 341, 341a), and simplifying the complexity of the layout of the lower half of the semiconductor device. Thus, the problem of islanding of the first metal interconnect layer can be avoided.

[0084] In summary, the method of forming the semiconductor device of the present application integrates the fabrication processes of two interconnect layers (i.e., the first contact via layer and the second metal interconnect layer), and simultaneously forms the metal interconnects in the first contact via layer and the second metal interconnect layer by using a self-aligned integration process, thereby avoiding the use of a photolithographic imaging process to form a critical dimension photoresist pattern, and solving the problem of process space constraint caused by reducing the height of the bit cell line of the semiconductor device. Thus, the semiconductor device can choose to place its source line in the second metal interconnect layer or the first metal interconnect layer without affecting the minimum line width / spacing of the interconnect layers above and below the second metal interconnect layer or the first metal interconnect layer. In addition, the semiconductor device can place magnetic storage structures (e.g., magnetic tunnel junction structures) alternately in the two interconnect layers, so that the minimum line width / spacing of each magnetic storage structure and other metal interconnects placed in the two interconnect layers can be correspondingly increased. Thus, the fabrication process of the magnetic storage structures and the metal interconnects placed in the two interconnect layers is no longer limited by process space constraints. Therefore, the semiconductor device of the present application can effectively reduce the height of the bit cell line of the semiconductor device under the premise of process permission, improve the element integration of the semiconductor device, and maintain the overall device operation performance.

[0085] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be within the scope of the present application.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate; a first interconnection layer disposed on the substrate, the first interconnection layer comprising a first dielectric layer surrounding a plurality of first magnetic tunnel junction structures, the first interconnection layer further comprising a plurality of first metal interconnects, the first metal interconnects having a line width greater than a line width of the first magnetic tunnel junction structures, the first metal interconnects and the first magnetic tunnel junction structures having top and bottom surfaces that are coplanar with each other, and the first metal interconnects and the first magnetic tunnel junction structures being alternately arranged within the first dielectric layer; and a second interconnection layer disposed on the first interconnection layer, the second interconnection layer comprising a second dielectric layer surrounding a plurality of second magnetic tunnel junction structures, the second interconnection layer further comprising a plurality of second metal interconnects, the second metal interconnects and the second magnetic tunnel junction structures having top and bottom surfaces that are coplanar with each other, the second magnetic tunnel junction structures and the first magnetic tunnel junction structures being alternately arranged along a direction, each of the second magnetic tunnel junction structures not overlapping each of the first magnetic tunnel junction structures and overlapping each of the first metal interconnects in a vertical direction perpendicular to the substrate, and each of the first magnetic tunnel junction structures overlapping each of the second metal interconnects in the vertical direction.

2. The semiconductor device according to claim 1, wherein The first metal interconnects are disposed directly below the second magnetic tunnel junction structures within the second interconnection layer.

3. The semiconductor device according to claim 1, wherein The second metal interconnects and the second magnetic tunnel junction structures are alternately arranged within the second dielectric layer.

4. The semiconductor device according to claim 3, wherein The second metal interconnects are disposed directly above the first magnetic tunnel junction structures within the first interconnection layer.

5. The semiconductor device according to claim 1, wherein Further comprising: a third interconnection layer disposed below the first interconnection layer and between the substrate and the first interconnection layer, the third interconnection layer comprising a third dielectric layer surrounding a plurality of third metal interconnects, wherein a portion of the third metal interconnects are electrically connected to a source of the substrate.

6. The semiconductor device according to claim 5, wherein Further comprising a fourth interconnection layer, the fourth interconnection layer comprising a fourth dielectric layer surrounding a plurality of fourth metal interconnects.

7. The semiconductor device according to claim 6, wherein The fourth interconnection layer is disposed below the third interconnection layer and between the substrate and the third interconnection layer, and the fourth metal interconnects have a pitch that is greater than a pitch of the third metal interconnects.

8. The semiconductor device according to claim 7, wherein The third interconnection layer is formed by a self-aligned merge fabrication process.

9. The semiconductor device according to claim 6, wherein The fourth interconnection layer is disposed above the third interconnection layer and between the third interconnection layer and the first interconnection layer, and the fourth metal interconnects have a pitch that is greater than a pitch of the third metal interconnects.

10. The semiconductor device according to claim 9, wherein The fourth interconnection layer is formed by a self-aligned merge fabrication process.

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