A high-speed interface transmitter circuit, chip and electronic device

Abstract

The application relates to a high-speed interface transmitter circuit, a chip and an electronic device, wherein the high-speed interface transmitter circuit comprises at least one group of data serialization circuits, at least one group of equalization driving circuits, a clock generation and matching circuit and two load resistors; the clock generation and matching circuit is connected with the data serialization circuit; a clock signal generated by the clock generation and matching circuit is used for clock matching with serialized data in the data serialization circuit, so that the clock signal is accurately matched with the serialized data in the data serialization circuit, thereby greatly improving data performance, reducing the jitter of the output of the serialization circuit, increasing the eye opening and improving system performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-speed interface transmitter circuit, chip, and electronic device. Background Technology

[0002] The rapid development of cloud computing services, IoT applications, and artificial intelligence technologies has driven the explosive growth of network transmission capacity, with instantaneous data exchange speeds reaching Tbit / s. The ever-increasing communication data rates have brought enormous challenges to high-speed interconnect technologies, making data transmission speed a key factor limiting system performance. High-speed serial interface technology, with its high bandwidth, low latency, and good scalability, has become an effective solution for high-speed data transmission and is widely used in processor-peripheral interconnects, multi-chip interconnects, high-speed hard disk interfaces, serial network interfaces, and fiber optic communications. High-speed serial interface technologies involve various design methodologies, including semi-custom, fully custom, and analog circuits. It is a mixed-signal system that typically processes signal rates ranging from tens to hundreds of Gbps.

[0003] Key performance indicators for high-speed interface transmitter chips include transmission rate, data jitter, signal amplitude, equalization capability, and system power consumption. Transmission rate is the core indicator of the system and also a design challenge for transmitter chips. With the increase in communication speed, the design of high-speed interface transmitter chips faces a series of signal integrity issues, such as inter-symbol interference, crosstalk, noise, and channel reflection.

[0004] Equalization techniques can specifically address the signal attenuation problem in the aforementioned serial data transmission. However, the increase in communication frequency also presents significant challenges to the design of high-speed interface transmitter chips. For example, severe signal jitter within the chip can reduce the serial data aperture, severely degrading system performance. Summary of the Invention

[0005] In view of this, the present invention provides a high-speed interface transmitter circuit, chip, and electronic device to solve the problem in the prior art where severe signal jitter inside the high-speed interface transmitter chip leads to a reduction in the serial data aperture, which in turn severely degrades system performance.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A high-speed interface transmitter circuit includes:

[0008] At least one set of data serialization circuits, at least one set of equalization drive circuits, a clock generation and matching circuit, and two load resistors;

[0009] Each set of data serialization circuits includes a positive data serialization circuit and a negative data serialization circuit for forming differential signals; each set of equalization drive circuits includes a positive equalization drive circuit and a negative equalization drive circuit; the output terminal of the positive data serialization circuit is connected to the input terminal of the positive equalization drive circuit; the output terminal of the negative data serialization circuit is connected to the input terminal of the negative equalization drive circuit.

[0010] The output terminals of the equalization drive circuit are all connected to one end of the two load resistors, serving as the output terminals of the high-speed interface transmitter circuit; the other ends of the two load resistors are all connected to the power supply.

[0011] Both the positive data serialization circuit and the negative data serialization circuit are connected to the clock generation and matching circuit. The clock generation and matching circuit generates a clock signal, which is transmitted to the positive data serialization circuit and the negative data serialization circuit of the data serialization circuit.

[0012] The clock signal generated by the clock generation and matching circuit is used to perform clock matching with the serialized data in the data serialization circuit.

[0013] Preferably, the clock generation and matching circuit includes: a first buffer, a multi-phase clock signal generator, a clock delay unit, and a bias signal generator;

[0014] The input terminal of the first buffer is used to receive a clock input signal and to delay the clock input signal.

[0015] The output of the first buffer is connected to the input of the multiphase clock signal generator; the multiphase clock signal generator is used to generate a multiphase clock based on the preset phase difference between sampling clocks.

[0016] The output of the multiphase clock signal generator is connected to the synchronization circuit in the positive data serialization circuit and the negative data serialization circuit.

[0017] The output of the multiphase clock signal generator is also used to connect to the clock delayer.

[0018] The clock delay unit is connected to the bias signal generator, receives bias signal control, and inputs a delayed clock signal to the selector of the positive data serialization circuit and the negative data serialization circuit.

[0019] Preferably, the clock delay includes:

[0020] Second buffer, third buffer, fourth buffer, fifth buffer, sixth buffer, seventh buffer, eighth buffer, ninth buffer, tenth buffer, eleventh buffer and first variable capacitor, second variable capacitor, third variable capacitor, fourth variable capacitor;

[0021] The second buffer, the third buffer, and the fourth buffer are connected in series; the input terminal of the second buffer receives a first clock input signal; the output terminal of the second buffer is connected to one end of the first variable capacitor; the output terminal of the third buffer is connected to one end of the second variable capacitor; the other ends of the first variable capacitor and the other ends of the second variable capacitor are both grounded; the output terminal of the fourth buffer outputs the first clock signal.

[0022] The fifth buffer and the sixth buffer are connected in series; the input terminal of the fifth buffer receives the second clock input signal, and the output terminal of the sixth buffer outputs the second clock signal.

[0023] The seventh buffer, the eighth buffer, and the ninth buffer are connected in series. The input terminal of the seventh buffer receives a third clock input signal. The output terminal of the seventh buffer is connected to one end of the third variable capacitor. The output terminal of the eighth buffer is connected to one end of the fourth variable capacitor. The other ends of the third and fourth variable capacitors are both grounded. The output terminal of the ninth buffer outputs the third clock signal.

[0024] The tenth buffer and the eleventh buffer are connected in series; the input terminal of the tenth buffer receives the fourth clock input signal, and the output terminal of the eleventh buffer outputs the fourth clock signal.

[0025] Preferably, the positive data serialization circuit and the negative data serialization circuit have the same structure, both including:

[0026] A random data generator, a synchronization circuit, and a selector connected in sequence;

[0027] The random data generator generates parallel data, which is then synchronized and sampled by the synchronization circuit. The selector samples the parallel data according to the sampling clock to generate multiple serial data.

[0028] Preferably, the data serialization circuit further includes a logic equalization circuit; the logic equalization circuit is connected between the selector and the equalization drive circuit.

[0029] The logic equalization circuit includes multiple logic equalization units connected in parallel;

[0030] Each of the aforementioned logic equalization units includes: a selection switch, an inverter, and logic gates;

[0031] The selection switch is connected to the input terminal of the inverter;

[0032] The output of the inverter is connected to the logic gate circuit.

[0033] The logic gate circuit is used to receive the serial differential data of the previous stage and the serial differential data of the next stage, and output the serial differential data of the main stage.

[0034] Preferably, the logic gate circuit includes: a first NAND gate, a first NOR gate, a second NAND gate and a second NOR gate, and a plurality of transistors;

[0035] The first terminals of both the first NAND gate and the second NAND gate are connected to the output terminal of the inverter.

[0036] The second terminal of the first NAND gate and the first terminal of the first NOR gate are both used to receive the preceding serial differential data.

[0037] The second terminal of the second NAND gate and the first terminal of the second NOR gate are both used to receive the subsequent serial differential data;

[0038] The second terminals of both the first NOR gate and the second NOR gate are connected to the input terminal of the inverter.

[0039] The multiple transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0040] The control terminal of the first transistor is connected to the output terminal of the first NAND gate; the control terminal of the second transistor is connected to the output terminal of the first NOR gate; the first terminal of the first transistor is connected to the power supply; the second terminal of the first transistor is connected to the first terminal of the second transistor and is used to output the main stage serial differential data; the second terminal of the second transistor is grounded.

[0041] The control terminal of the third transistor is connected to the output terminal of the second NAND gate; the control terminal of the fourth transistor is connected to the output terminal of the second NOR gate; the first terminal of the third transistor is connected to the power supply; the second terminal of the third transistor is connected to the first terminal of the fourth transistor and is used to output the main stage serial differential data; the second terminal of the fourth transistor is grounded.

[0042] Preferably, the positive equalization driving circuit receives a differential signal opposite to that received by the negative equalization driving circuit, and the positive equalization driving circuit specifically includes:

[0043] The circuit consists of a pre-stage equalization control circuit, a post-stage equalization control circuit, a main stage equalization control circuit, a first capacitor, and a second capacitor.

[0044] The pre-stage equalization control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0045] The main-level equalization control circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

[0046] The subsequent equalization control circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0047] The control terminals of the fifth transistor and the sixth transistor both receive the pre-amplifier bias voltage input; the first terminal of the fifth transistor is used to connect to the first terminals of the ninth transistor and the thirteenth transistor, and is also used to connect to one end of the first load resistor.

[0048] The first terminal of the sixth transistor is used to connect to the first terminals of the tenth and fourteenth transistors, and is also used to connect to one end of the second load resistor;

[0049] The second terminal of the fifth transistor is connected to the first terminal of the seventh transistor, and the control terminal of the seventh transistor is used to receive negative differential data of the preceding serial differential data.

[0050] The second terminal of the sixth transistor is connected to the first terminal of the eighth transistor, and the control terminal of the eighth transistor is used to receive positive differential data of the previous stage serial differential data.

[0051] The control terminals of the ninth transistor and the tenth transistor both receive the main stage bias voltage input; the second terminal of the ninth transistor is connected to the first terminal of the eleventh transistor, and the control terminal of the eleventh transistor is used to receive the positive differential data of the main stage serial differential data.

[0052] The second terminal of the tenth transistor is connected to the first terminal of the twelfth transistor, and the control terminal of the twelfth transistor is used to receive negative differential data of the main stage serial differential data;

[0053] The control terminals of the thirteenth transistor and the fourteenth transistor both receive the subsequent bias voltage input; the second terminal of the thirteenth transistor is connected to the first terminal of the fifteenth transistor, and the control terminal of the fifteenth transistor is used to receive the negative differential data of the subsequent serial differential data;

[0054] The second terminal of the fourteenth transistor is connected to the first terminal of the sixteenth transistor, and the control terminal of the sixteenth transistor is used to receive positive differential data of the subsequent serial differential data.

[0055] The second terminal of the seventh transistor, the second terminal of the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, and the sixteenth transistor are all grounded;

[0056] One end of the first capacitor is connected to the second end of the tenth transistor, and the other end of the first capacitor is connected to the control terminal of the eleventh transistor.

[0057] One end of the second capacitor is connected to the second terminal of the ninth transistor, and the other end of the second capacitor is connected to the control terminal of the twelfth transistor.

[0058] Preferably, the data serialization circuit comprises two sets connected in parallel, and the number of equalization drive circuits is also two sets.

[0059] The present invention also provides a high-speed interface transmitter chip, including the high-speed interface transmitter circuit described in any of the above claims.

[0060] The present invention also provides an electronic device, including the high-speed interface transmitter chip described above.

[0061] As can be seen from the above technical solution, the high-speed interface transmitter circuit provided by the present invention includes: at least one set of data serialization circuits, at least one set of equalization drive circuits, a clock generation and matching circuit, and two load resistors; the clock generation and matching circuit is connected to the data serialization circuit, and the clock signal generated by the clock generation and matching circuit is used to perform clock matching with the serialized data in the data serialization circuit, so that the clock signal and the serialized data in the data serialization circuit are accurately matched, thereby greatly improving data performance, reducing the jitter of the output of the serialization circuit, thereby increasing the opening and improving system performance. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0063] Figure 1 Comparison of eye opening for output signals of serialization circuits with different timing matching;

[0064] Figure 2 This invention provides a schematic diagram of a high-speed interface transmitter circuit structure;

[0065] Figure 3 A schematic diagram of the specific structure of a high-speed interface transmitter circuit provided in an embodiment of the present invention;

[0066] Figure 4 This is a schematic diagram of a clock delay structure provided in an embodiment of the present invention;

[0067] Figure 5 A schematic diagram of the selector structure provided in an embodiment of the present invention;

[0068] Figure 6This is a comparison diagram of data frequency domain characteristics provided in an embodiment of the present invention;

[0069] Figure 7 This is a schematic diagram of another high-speed interface transmitter circuit structure provided in an embodiment of the present invention;

[0070] Figure 8 A schematic diagram of the logic equalization circuit structure provided in an embodiment of the present invention;

[0071] Figure 9 This is a schematic diagram of a high-speed interface transmitter circuit structure provided in an embodiment of the present invention;

[0072] Figure 10 This is a schematic diagram of the positive equalization driving circuit provided in an embodiment of the present invention;

[0073] Figure 11 This is a schematic diagram of another high-speed interface transmitter circuit structure provided in an embodiment of the present invention;

[0074] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0075] As described in the background section, in the prior art, the internal signal jitter of the high-speed interface transmitter chip is severe, which leads to a reduction in the serial data opening and thus seriously degrades the system performance.

[0076] The inventors discovered that the reason for the above phenomenon is that, Figure 1 As shown, Figure 1 The diagram shows a comparison of the eye opening of the data serialization circuit output signal under different timing matches. As can be seen from the diagram, the optimal clock position should be located in the data center (clock signal timing diagram above). At this position, the data jitter of the data serialization circuit output is minimized. If the edge of the clock signal deviates from the data center (clock signal timing diagram below), additional jitter will be introduced when selecting the output signal. This jitter cannot be canceled by external circuitry. Increased jitter will lead to a decrease in the data eye opening, severely degrading system performance.

[0077] Based on this, the present invention provides a high-speed interface transmitter circuit, comprising:

[0078] At least one set of data serialization circuits, at least one set of equalization drive circuits, a clock generation and matching circuit, and two load resistors;

[0079] Each set of data serialization circuits includes a positive data serialization circuit and a negative data serialization circuit for forming differential signals; each set of equalization drive circuits includes a positive equalization drive circuit and a negative equalization drive circuit; the output terminal of the positive data serialization circuit is connected to the input terminal of the positive equalization drive circuit; the output terminal of the negative data serialization circuit is connected to the input terminal of the negative equalization drive circuit.

[0080] The output terminals of the equalization drive circuit are all connected to one end of the two load resistors, serving as the output terminals of the high-speed interface transmitter circuit; the other ends of the two load resistors are all connected to the power supply.

[0081] Both the positive data serialization circuit and the negative data serialization circuit are connected to the clock generation and matching circuit. The clock generation and matching circuit generates a clock signal, which is transmitted to the positive data serialization circuit and the negative data serialization circuit of the data serialization circuit.

[0082] The clock signal generated by the clock generation and matching circuit is used to perform clock matching with the serialized data in the data serialization circuit.

[0083] The high-speed interface transmitter circuit provided by this invention includes: at least one set of data serialization circuits, at least one set of equalization drive circuits, a clock generation and matching circuit, and two load resistors; the clock generation and matching circuit is connected to the data serialization circuit, and the clock signal generated by the clock generation and matching circuit is used to perform clock matching with the serialized data in the data serialization circuit, so that the clock signal and the serialized data in the data serialization circuit are accurately matched, thereby greatly improving data performance, reducing the jitter of the output of the serialization circuit, thereby increasing the opening and improving system performance.

[0084] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0085] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0086] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0087] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0088] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0089] Please see Figure 2 , Figure 2 This invention provides a schematic diagram of a high-speed interface transmitter circuit structure. The high-speed interface transmitter circuit includes: at least one set of data serialization circuits 1, at least one set of equalization drive circuits 2, a clock generation and matching circuit 3, and two load resistors R. T Each data serialization circuit 1 includes a positive data serialization circuit 1P and a negative data serialization circuit 1N for forming differential signals; each equalization drive circuit 2 includes a positive equalization drive circuit 2P and a negative equalization drive circuit 2N; the output terminal of the positive data serialization circuit 1P is connected to the input terminal of the positive equalization drive circuit 2P; the output terminal of the negative data serialization circuit 1N is connected to the input terminal of the negative equalization drive circuit 2N.

[0090] The output terminals of the equalization drive circuit 2 are connected to two load resistors R. T One end is connected as the output terminal Dout of the high-speed interface transmitter circuit; two load resistors R TThe other end of each circuit is connected to the power supply Vdd. Both the positive data serialization circuit 1P and the negative data serialization circuit 1N are connected to the clock generation and matching circuit 3. The clock generation and matching circuit 3 generates a clock signal, which is transmitted to the positive data serialization circuit 1P and the negative data serialization circuit 1N of the data serialization circuit 1. Specifically, the clock signal CK generated by the clock generation and matching circuit 3 is used for clock matching with the serialized data in the data serialization circuit 1.

[0091] It should be noted that the specific structure of the clock generation and matching circuit 3 is not limited in the embodiments of the present invention, as long as it can achieve the function of accurately matching with the serialized data, thereby reducing the jitter of the serialized data and increasing the eye opening. Specifically, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the specific structure of a high-speed interface transmitter circuit provided in an embodiment of the present invention. The clock generation and matching circuit 3 includes: a first buffer 31, a multi-phase clock signal generator 32, a clock delay unit 33, and a bias signal generator 34.

[0092] The first buffer 31 has an input terminal that receives the clock input signal CLK IN and delays it. Its output terminal is connected to the input terminal of the multiphase clock signal generator 32. The multiphase clock signal generator 32 generates a multiphase clock CK based on a preset phase difference between sampling clocks. Its output terminal is connected to the synchronization circuit 12 in the positive data serialization circuit 1P and the negative data serialization circuit 1N. The output terminal of the multiphase clock signal generator 32 is also connected to a clock delay unit 33. The clock delay unit 33 is connected to a bias signal generator 34 and receives the bias signal V. ctrl Control and input the delayed clock signal to the selector 13 of the positive data serialization circuit 1P and the negative data serialization circuit 1N.

[0093] In this embodiment of the invention, a clock signal CK is generated by a multiphase clock signal generator 32. At this time, the clock signal CK can be synchronized with the data in the synchronization circuit 12 in the serialized data, and then accurately matched with the transmission of serialized data in the selector 13, thereby reducing jitter during data transmission, increasing the opening, and improving system performance.

[0094] Please see Figure 4 , Figure 4 This is a schematic diagram of a clock delay structure provided in an embodiment of the present invention; the specific structure of the clock delay 33 that achieves precise matching between the clock signal and serialized data in this embodiment includes:

[0095] Second buffer 331, third buffer 332, fourth buffer 333, fifth buffer 334, sixth buffer 335, seventh buffer 336, eighth buffer 337, ninth buffer 338, tenth buffer 339, eleventh buffer 3310 and first variable capacitor C331, second variable capacitor C332, third variable capacitor C333, fourth variable capacitor C334;

[0096] The second buffer 331, the third buffer 332, and the fourth buffer 333 are connected in series; the input terminal of the second buffer 331 receives the first clock input signal CK. in0 The output of the second buffer 331 is connected to one end of the first variable capacitor C331; the output of the third buffer 332 is connected to one end of the second variable capacitor C332; the other ends of the first variable capacitor C331 and the second variable capacitor C332 are both grounded; the output of the fourth buffer 333 outputs the first clock signal CK0.

[0097] The fifth buffer 334 and the sixth buffer 335 are connected in series; the input of the fifth buffer 334 receives the second clock input signal CK. in90 The output of the sixth buffer 335 outputs the second clock signal CK. 90 ;

[0098] The seventh buffer 336, the eighth buffer 337, and the ninth buffer 338 are connected in series; the input of the seventh buffer 336 receives the third clock input signal CK. in180 The output of the seventh buffer 336 is connected to one end of the third variable capacitor C333; the output of the eighth buffer 337 is connected to one end of the fourth variable capacitor C334; the other ends of the third variable capacitor C333 and the fourth variable capacitor C334 are both grounded; the output of the ninth buffer 338 outputs the third clock signal CK. 180 ;

[0099] The tenth buffer 339 and the eleventh buffer 3310 are connected in series; the input of the tenth buffer 339 receives the fourth clock input signal CK. in270 The eleventh buffer 3310 outputs the fourth clock signal CK. 270 .

[0100] In this embodiment, by adding buffers and variable capacitors in the clock path during the delay of different clock signals, the delays of multiple clock signals are made different. By adjusting the size of the buffers and the capacitance of the variable capacitors, the serialized data transmitted in the serialization circuit can be matched, thereby achieving precise matching between clock and data, greatly improving data performance, and significantly reducing the output jitter of the serialization circuit.

[0101] The serialization circuit that matches the clock signal delay process above is as follows: Figure 3 As shown, the data serialization circuit includes a random data generator 11, a synchronization circuit 12, and a selector 13 connected in sequence. The random data generator 11 generates parallel data, which is synchronized and sampled by the synchronization circuit 12. Then, the selector 13 samples the parallel data according to a sampling clock to generate multiple serial data sets. The serial data includes master-level serial data. The random data generator 11 and the synchronization circuit 12 can be implemented using existing known structures; this embodiment does not limit their implementation.

[0102] In practical applications, let's take the transmission of a four-level pulse amplitude modulation signal by a transmitter circuit as an example. Figure 3 As shown, the transmitted data is called master-level data DM. main Master-level data DM main After passing through the synchronization circuit, according to the master-level data DM main Generate front-end data DM with a positive or negative time difference from the main-end data. pre and subsequent data DM post When using a traditional integer architecture feedforward equalizer for equalization compensation, the multi-phase clock generation circuit drives and divides the input clock, so that the phase difference between the sampling clocks of the main stage data and the previous and subsequent stage data is 90°, that is, the phase difference between the sampling clocks of the main stage data and the previous and subsequent stage data is ±1UI.

[0103] like Figure 3 As shown, considering the need to generate pre-stage and post-stage data with positive and negative time differences based on the master-level data, three selectors are required. However, in practical applications, data with more time differences at each stage can also be generated, requiring more selectors. This invention does not limit the number of selectors. Four-bit parallel data, after passing through a synchronization circuit, obtains master-level data at a quarter speed, as well as pre-stage and post-stage data with time differences less than ±1 UI from the master-level data. Since it is four-bit parallel data, it needs to pass through a 4:1 selector to generate pre-stage serialized data, master-stage serialized data, and post-stage serialized data. If it is eight-bit parallel data, then an 8:1 selector is used. Similarly, other bit-level parallel data corresponds to corresponding selectors. It can be understood that the synchronization circuit first generates four-bit parallel master-level data, pre-stage data, and post-stage data, and then the selectors serialize the parallel data.

[0104] It should be noted that the high-speed interface transmitter circuit provided in this embodiment is not only suitable for non-return-to-zero code signal transmission, but also for multi-level pulse modulation signal transmission. In this embodiment, the high-speed interface transmitter circuit may include only one set of data serialization circuits and one set of equalization drive circuits. In other embodiments, it may also include two sets of data serialization circuits and two sets of equalization drive circuits. For example, the high 4 bits of parallel data are serialized and transmitted after passing through a synchronization circuit. Similarly, the transmission principle of the low 4 bits of parallel data is the same as that of the high 4 bits, which will be described in detail in subsequent embodiments.

[0105] In this embodiment, the data serialization circuit is optional, such as... Figure 5 The diagram shown is a schematic diagram of the selector structure provided in an embodiment of the present invention; in this embodiment, a 4:1 selector is used as an example for explanation.

[0106] The selector includes twelfth to eighteenth buffers and multiple clock switches.

[0107] The input terminals of the twelfth buffer 131, the thirteenth buffer 132, the fourteenth buffer 133, and the fifteenth buffer 134 are used to receive parallel data input signals. The output terminal of the twelfth buffer 131 is connected to the input terminal of the sixteenth buffer 135 through the first clock switch K1, and the output terminal of the thirteenth buffer 132 is connected to the input terminal of the sixteenth buffer 135 through the third clock switch K3. The output terminal of the fourteenth buffer 133 is connected to the input terminal of the seventeenth buffer 136 through another set of second clock switches K2, and the output terminal of the fifteenth buffer 134 is connected to the input terminal of the seventeenth buffer 136 through the first clock switch K1. The output terminal of the seventeenth buffer 136 is connected to the input terminal of the eighteenth buffer 137 through the fourth clock switch K4. The output terminal of the eighteenth buffer 137 serves as the output terminal Dout of the selector.

[0108] The first clock switch K1 receives the second clock signal CK. 90 Under the control of the second clock switch K2, the fourth clock signal CK is received. 270 Under control, the third clock switch K3 receives the third clock signal CK. 180 The control is achieved by the fourth clock switch K4 receiving the control signal CK0 from the first clock signal.

[0109] The selector provided in this embodiment of the invention, by adding a sixteenth buffer 135 and a seventeenth buffer 136, causes a delay in serial data during data serialization transmission. That is, the selector provided in this embodiment adopts a two-stage serialization structure with a differential clock CK. 270 With CK 90 Perform the first stage of serialization, differential clock CK 180Complete the second-level serialization with CK0.

[0110] In a serialization circuit, the timing relationship between the clock and data ensures the basic function of the circuit. Furthermore, the matching relationship between the second-stage clock and data determines the jitter of the final output data of the serializer. Precise clock-data matching minimizes output data jitter. Figure 1 As shown in the eye opening diagram, it can be seen that the clock generation and matching circuit provided in this embodiment of the invention can increase the eye opening, reduce jitter, and improve the system performance.

[0111] Furthermore, a variable capacitor is introduced as a buffer load in the clock generation and matching circuit to fine-tune the clock CK. 180 The delay with CK0 is used to match the transmission time required for the serialization switch selection process, thereby achieving precise matching between the clock and data, greatly improving data performance, and significantly reducing the output jitter of the serialization circuit.

[0112] It should be noted that in practical applications, besides the data output jitter caused by clock mismatch during data serialization, which can lead to a smaller eye opening, insufficient circuit bandwidth can also cause data jitter. Specifically, traditional transmitter equalization performs equalization calculations in the output driver circuit to optimize the chip's output signal quality and compensate for signal attenuation that may be caused by the chip's external packaging and wiring. However, when the data rate increases significantly, not only does the external signal quality of the chip deteriorate severely, but the internal circuit bandwidth of the chip also seriously restricts signal quality. Figure 3 In the transmitter circuit structure shown, the main-tap data is the actual transmitted data. Due to design requirements, the corresponding driver transistors in the drive circuit are usually selected to be larger in size. Therefore, the output load of the MUX in front of it will be increased, which will cause the rise and fall edges of the signal to slow down during signal transmission, and deteriorate the signal opening and jitter performance.

[0113] Based on this, another embodiment of the present invention also provides a logic feedforward equalization (logic FFE) technique for targeted compensation of main-level data attenuation. The basic principle is to add an adjustable driving branch to the data output terminals of the pre-tap and post-tap, which is directly connected to the data output terminal of the main-tap. According to the principle of de-emphasis feedforward equalization, the data tailing attenuation caused by inter-symbol interference is compensated, thereby improving the quality of the main-level data signal. Data jitter optimization is performed in advance before entering the equalization driving circuit to reduce data-related jitter (DCD). Figure 6 The given data frequency domain characteristics show that using logic feedforward equalization technology can effectively expand the circuit bandwidth, improve the edge characteristics of the rising and falling edges of the data, and enhance the data driving capability.

[0114] Please see Figure 7 , Figure 7 This is a schematic diagram of another high-speed interface transmitter circuit structure provided in an embodiment of the present invention. A logic equalization circuit is also provided within the data serialization circuit. Furthermore, in this embodiment, the high-speed interface transmitter circuit includes two sets of data serialization circuits: the upper set transmits the high 4 bits of data, and the lower set transmits the low 4 bits of data. The structures of both sets of data serialization circuits and the equalization drive circuit are identical.

[0115] The above data serialization circuit will be used as an example for explanation. Figure 3 Unlike the data serialization circuit shown, the data serialization circuit in the high-speed interface transmitter circuit provided in this embodiment also includes a logic equalization circuit 14, which is connected between the selector and the equalization drive circuit.

[0116] Please see Figure 8 , Figure 8 This is a schematic diagram of a logic equalization circuit structure provided in an embodiment of the present invention; wherein, the logic equalization circuit includes multiple logic equalization units connected in parallel; each logic equalization unit includes: a selection switch SW. m (where m takes the value 1, 2, 3...N), inverter 141 and logic gate circuit 142; wherein, selection switch SW m The inverter 141 is connected to its input terminal; the output terminal of the inverter 141 is connected to logic gate 142; logic gate 142 is used to receive the serial differential data DM from the previous stage. pre and subsequent serial differential data DM post and output master-level serial differential data DM main .

[0117] For details, please see Figure 8 The logic gate circuit includes: a first NAND gate 1421, a first NOR gate 1422, a second NAND gate 1423, and a second NOR gate 1424, as well as multiple transistors (T1, T2, T3, T4); the first terminals of the first NAND gate 1421 and the second NAND gate 1423 are both connected to the output terminal of the inverter 141; the second terminal of the first NAND gate 1421 and the first terminal of the first NOR gate 1422 are both used to receive the serial differential data DM from the previous stage. pre The second terminal of the second NAND gate 1423 and the first terminal of the second NOR gate 1424 are both used to receive the subsequent serial differential data DM. post The second terminals of the first NOR gate 1422 and the second NOR gate 1424 are both connected to the input terminal of the inverter 141.

[0118] Multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; the control terminal of the first transistor T1 is connected to the output terminal of the first NAND gate 1421; the control terminal of the second transistor T2 is connected to the output terminal of the first NOR gate 1422; the first terminal of the first transistor T1 is connected to the power supply; the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and is used to output the main stage serial differential data DM. main The second terminal of the second transistor T2 is grounded; the control terminal of the third transistor T3 is connected to the output terminal of the second NAND gate 1423; the control terminal of the fourth transistor T4 is connected to the output terminal of the second NOR gate 1424; the first terminal of the third transistor T3 is connected to the power supply; the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4 and is used to output the main stage serial differential data DM. main The second terminal of the fourth transistor T4 is grounded.

[0119] To enhance design integrity and improve technical flexibility, the logic equalization circuit provided in this embodiment is a logic equalization circuit with adjustable compensation capability, such as... Figure 8 As shown. By selecting different switches, different multiples of the drive unit can be selected. For example, SW0 and SW1 can be selected for selective conduction. After inputting the control signal, the single-multiplier drive unit and the double-multiplier drive unit are controlled respectively. The compensation intensity is adjusted according to the signal rate attenuation. In other embodiments of the present invention, the drive unit of the logic equalization circuit can be further extended to N bits according to actual application requirements.

[0120] The logic equalization circuit proposed in this invention is a master-level data logic equalization technology. Based on system-level design optimization, it uses internal data to achieve feedforward equalization optimization of master-level data, solving the problem of data attenuation within the chip, optimizing the rise and fall times of data edges, improving the signal quality within the chip, and enhancing the performance of internal system nodes. Furthermore, it can expand the circuit bandwidth, thereby reducing output signal jitter, increasing the system's openness, and optimizing system performance.

[0121] In another embodiment of the invention, the purpose of reducing output data jitter can also be achieved by extending the drive bandwidth. Please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of a high-speed interface transmitter circuit structure provided in an embodiment of the present invention;

[0122] and Figure 7 The difference is that the equalization drive circuit 21 in the high-speed interface transmitter circuit provided in this embodiment has a non-traditional structure. Each equalization drive circuit includes a positive equalization drive circuit and a negative equalization drive circuit. In this embodiment, the positive equalization drive circuit and the negative equalization drive circuit have the same structure, except that the input signal is a differential signal with opposite positive and negative signals.

[0123] This embodiment uses a positive equalization driving circuit as an example for explanation. The structure of the negative equalization driving circuit is the same as that of the positive equalization driving circuit, and this embodiment does not limit it.

[0124] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of the positive equalization driving circuit provided in an embodiment of the present invention; the positive equalization driving circuit specifically includes:

[0125] The circuit consists of a pre-stage equalization control circuit 211, a post-stage equalization control circuit 212, a main stage equalization control circuit 213, a first capacitor C1, and a second capacitor C2.

[0126] The pre-amplifier equalization control circuit 211 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8;

[0127] The main level equalization control circuit 213 includes a ninth transistor (shown in the upper left corner of module 213 in the figure), a tenth transistor (shown in the upper right corner of module 213 in the figure), an eleventh transistor (shown in the lower left corner of module 213 in the figure), and a twelfth transistor (shown in the lower right corner of module 213 in the figure);

[0128] The post-equalization control circuit 212 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16;

[0129] The control terminals of both the fifth transistor T5 and the sixth transistor T6 receive the bias voltage input VB from the preceding stage. pre The first terminal of the fifth transistor T5 is used to connect to the first terminals of the ninth and thirteenth transistors T13, and is also used to connect to a load resistor R. T One end is connected, that is, node ON, which serves as an output terminal of the equalization drive circuit;

[0130] The first terminal of the sixth transistor T6 is used to connect to the first terminals of the tenth and fourteenth transistors T14, and is also used to connect to another load resistor R. T One end is connected, namely node OP, which serves as the other output terminal of the equalization drive circuit;

[0131] The second terminal of the fifth transistor T5 is connected to the first terminal of the seventh transistor T7. The control terminal of the seventh transistor T7 is used to receive the negative differential data DM from the previous stage serial differential data. pre_N ;

[0132] The second terminal of the sixth transistor T6 is connected to the first terminal of the eighth transistor T8. The control terminal of the eighth transistor T8 is used to receive the positive differential data DM from the previous stage serial differential data. pre_P ;

[0133] The control terminals of both the ninth and tenth transistors receive the main stage bias voltage input VB. main The second terminal of the ninth transistor is connected to the first terminal of the eleventh transistor. The control terminal of the eleventh transistor is used to receive the positive differential data DM of the main stage serial differential data. main_P ;

[0134] The second terminal of the tenth transistor is connected to the first terminal of the twelfth transistor. The control terminal of the twelfth transistor is used to receive the negative differential data DM of the main stage serial differential data. main_N ;

[0135] The control terminals of both the thirteenth transistor T13 and the fourteenth transistor T14 receive the subsequent bias voltage input VB. post The second terminal of the thirteenth transistor T13 is connected to the first terminal of the fifteenth transistor T15. The control terminal of the fifteenth transistor T15 is used to receive the negative differential data DM of the subsequent serial differential data. post_N ;

[0136] The second terminal of the fourteenth transistor T14 is connected to the first terminal of the sixteenth transistor T16. The control terminal of the sixteenth transistor T16 is used to receive the positive differential data DM of the subsequent serial differential data. post_P ;

[0137] The second terminal of the seventh transistor T7, the second terminal of the eighth transistor T8, the eleventh transistor, the twelfth transistor, the fifteenth transistor T15, and the second terminal of the sixteenth transistor T16 are all grounded;

[0138] One end of the first capacitor C1 is connected to the second end of the tenth transistor, and the other end of the first capacitor C1 is connected to the control terminal of the eleventh transistor.

[0139] One end of the second capacitor C2 is connected to the second terminal of the ninth transistor, and the other end of the second capacitor C2 is connected to the control terminal of the twelfth transistor.

[0140] The equalization drive circuit (MSB combiner) provided in this embodiment adopts a current-mode output drive method. When the output load resistor RT is fixed, the bias current of the input transistor pair determines the output signal amplitude. The pre-tap and post-tap data are used for output equalization and are therefore connected in opposite phase to the main-tap data output. The MSB combiner and LSM combiner work together to generate the final modulation pulse, i.e., the transmitted PAM4 data (NRZ data can also be generated depending on the data encoding method). This embodiment differs from previous embodiments in that it introduces a pair of capacitors connected between the gate and drain of the input differential pair transistors. Their function is to provide a fast output signal establishment path, thereby accelerating the output signal establishment process, effectively increasing the overall bandwidth of the drive circuit, improving the circuit's drive load capacity, significantly optimizing the eye opening and jitter performance of the output signal eye diagram, and achieving system optimization. In other words, by accelerating the establishment of the drive circuit output signal through the cross-connected capacitors, the circuit bandwidth performance is effectively improved without increasing additional current overhead, which can effectively optimize the chip output signal quality.

[0141] In another embodiment of the invention, it may also be as follows: Figure 11 As shown, Figure 11 This is a schematic diagram of another high-speed interface transmitter circuit structure provided in an embodiment of the present invention. The high-speed transmitter circuit structure provided in this embodiment includes the clock generation and matching circuit and the equalization drive circuit, which are the same structures provided in the embodiments of the present invention. However, the data serialization circuit has not been improved and includes the structure in the prior art. No additional logic equalization circuit has been added.

[0142] That is, the high-speed interface transmitter circuit provided in this embodiment of the invention enables precise matching between data and clock through clock generation and matching circuit, thereby reducing jitter of output signal; in addition, the cross capacitors are used to accelerate the establishment of output signal of the circuit, effectively improving the circuit bandwidth performance, which can also reduce jitter of output signal, increase the opening, and thus improve system performance.

[0143] In summary, this invention, based on system-level design, proposes a series of internal bandwidth expansion and jitter optimization techniques for transmitter chips, including master-level data logic equalization, serialization timing matching, and drive bandwidth expansion. These techniques address shortcomings in existing transmitter chip circuit designs, optimizing the design from the signal source and significantly improving transmitter data jitter performance, thereby increasing communication speed. The proposed techniques are of significant value for the design of high-speed serial transmitter chips exceeding 100Gbps. They not only increase transmission rates by expanding bandwidth but also optimize internal data transmission jitter through signal matching, effectively improving signal transmission quality. Furthermore, they possess good design compatibility, applicable not only to NRZ and PAM4 data transmission modes but also extending to high-speed analog circuit design, optimizing key internal designs of high-speed mixed-signal chips.

[0144] Based on the same inventive concept, the present invention also provides a high-speed interface transmitter chip, which includes the high-speed interface transmitter circuit described in any of the above embodiments.

[0145] In another embodiment of the present invention, as one possible implementation, Figure 12 A schematic diagram of the structure of the electronic device provided in the embodiment of the present invention is shown below, such as... Figure 12 As shown, the above-mentioned electronic device 100 also includes a processor 101 that communicates with the memory 102.

[0146] In some cases, such as Figure 11 As shown, the memory 102 and processor 101 included in the above-mentioned electronic device 100 can be integrated with communication interfaces and other devices, and packaged into a chip to form a chip used in electronic devices.

[0147] Compared with the prior art, the beneficial effects of the electronic device provided in the embodiments of the present invention are the same as those of the memory, and will not be repeated here.

[0148] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0149] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0150] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high speed interface transmitter circuit, characterized by include: At least one set of data serialization circuits, at least one set of equalization drive circuits, a clock generation and matching circuit, and two load resistors; Each group of data serialization circuits includes a positive data serialization circuit and a negative data serialization circuit for forming differential signals; each group of equalization drive circuits includes a positive equalization drive circuit and a negative equalization drive circuit. The output terminal of the positive data serialization circuit is connected to the input terminal of the positive equalization driving circuit; the output terminal of the negative data serialization circuit is connected to the input terminal of the negative equalization driving circuit. The output terminals of the equalization drive circuit are all connected to one end of the two load resistors, serving as the output terminals of the high-speed interface transmitter circuit; the other ends of the two load resistors are all connected to the power supply. Both the positive data serialization circuit and the negative data serialization circuit are connected to the clock generation and matching circuit. The clock generation and matching circuit generates a clock signal, which is transmitted to the positive data serialization circuit and the negative data serialization circuit of the data serialization circuit. The clock signal generated by the clock generation and matching circuit is used to perform clock matching with the serialized data in the data serialization circuit.

2. The high-speed interface transmitter circuit of claim 1, wherein, The clock generation and matching circuit includes: a first buffer, a multi-phase clock signal generator, a clock delay unit, and a bias signal generator; The input terminal of the first buffer is used to receive a clock input signal and to delay the clock input signal. The output of the first buffer is connected to the input of the multiphase clock signal generator; the multiphase clock signal generator is used to generate a multiphase clock based on the preset phase difference between sampling clocks. The output of the multiphase clock signal generator is connected to the synchronization circuit in the positive data serialization circuit and the negative data serialization circuit. The output of the multiphase clock signal generator is also used to connect to the clock delayer. The clock delay unit is connected to the bias signal generator, receives bias signal control, and inputs a delayed clock signal to the selector of the positive data serialization circuit and the negative data serialization circuit.

3. The high-speed interface transmitter circuit of claim 2, wherein, The clock delay includes: Second buffer, third buffer, fourth buffer, fifth buffer, sixth buffer, seventh buffer, eighth buffer, ninth buffer, tenth buffer, eleventh buffer and first variable capacitor, second variable capacitor, third variable capacitor, fourth variable capacitor; The second buffer, the third buffer, and the fourth buffer are connected in series; the input terminal of the second buffer receives a first clock input signal; the output terminal of the second buffer is connected to one end of the first variable capacitor; the output terminal of the third buffer is connected to one end of the second variable capacitor; the other ends of the first variable capacitor and the other ends of the second variable capacitor are both grounded; the output terminal of the fourth buffer outputs the first clock signal. The fifth buffer and the sixth buffer are connected in series; the input terminal of the fifth buffer receives the second clock input signal, and the output terminal of the sixth buffer outputs the second clock signal. The seventh buffer, the eighth buffer and the ninth buffer are connected in series; an input end of the seventh buffer receives a third clock input signal; an output end of the seventh buffer is connected with one end of the third variable capacitor; an output end of the eighth buffer is connected with one end of the fourth variable capacitor; the other end of the third variable capacitor and the other end of the fourth variable capacitor are grounded; an output end of the ninth buffer outputs a third clock signal; The tenth buffer and the eleventh buffer are connected in series; an input end of the tenth buffer receives a fourth clock input signal, and an output end of the eleventh buffer outputs a fourth clock signal.

4. A high-speed interface transmitter circuit according to any one of claims 1-3, characterized in that, The positive data serialization circuit and the negative data serialization circuit are identical in structure and each comprises: a random data generator, a synchronization circuit and a selector connected in series; The random data generator generates parallel data, the data is synchronized and sampled by the synchronization circuit, and the parallel data is sampled by the selector to generate a plurality of serial data according to a sampling clock.

5. The high-speed interface transmitter circuit of claim 4, wherein, The data serialization circuit further comprises a logic equalization circuit; the logic equalization circuit is connected between the selector and the equalization driving circuit; The logic equalization circuit comprises a plurality of logic equalization units connected in parallel; Each logic equalization unit comprises a selection switch, an inverter and a logic gate circuit; The selection switch is connected with the input end of the inverter; The output end of the inverter is connected with the logic gate circuit; The logic gate circuit is used for receiving front-stage serial differential data and rear-stage serial differential data and outputting main-stage serial differential data.

6. The high-speed interface transmitter circuit of claim 5, wherein, The logic gate circuit comprises a first NAND gate, a first NOR gate, a second NAND gate, a second NOR gate and a plurality of transistors; The first end of the first NAND gate and the second NAND gate is connected with the output end of the inverter; The second end of the first NAND gate and the first end of the first NOR gate are used for receiving the front-stage serial differential data; The second end of the second NAND gate and the first end of the second NOR gate are used for receiving the rear-stage serial differential data; The second end of the first NOR gate and the second NOR gate is connected with the input end of the inverter; The plurality of transistors comprises a first transistor, a second transistor, a third transistor and a fourth transistor; The control end of the first transistor is connected with the output end of the first NAND gate; the control end of the second transistor is connected with the output end of the first NOR gate; the first end of the first transistor is connected with a power supply; the second end of the first transistor is connected with the first end of the second transistor and is used for outputting the main-stage serial differential data; and the second end of the second transistor is grounded; The control end of the third transistor is connected with the output end of the second NAND gate; the control end of the fourth transistor is connected with the output end of the second NOR gate; the first end of the third transistor is connected with the power supply; the second end of the third transistor is connected with the first end of the fourth transistor and is used for outputting the main-stage serial differential data; and the second end of the fourth transistor is grounded.

7. The high-speed interface transmitter circuit of any of claims 1-3, 5, 6, wherein, The positive equalization driving circuit and the negative equalization driving circuit receive opposite differential signals, and the positive equalization driving circuit specifically comprises: a front-stage equalization control circuit, a rear-stage equalization control circuit, a main-stage equalization control circuit and a first capacitor and a second capacitor; the front-stage equalization control circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; the main-stage equalization control circuit comprises a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; the rear-stage equalization control circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; control ends of the fifth transistor and the sixth transistor receive a front-stage bias voltage input; a first end of the fifth transistor is connected with first ends of the ninth transistor and the thirteenth transistor, and is connected with one end of a first load resistor; a first end of the sixth transistor is connected with first ends of the tenth transistor and the fourteenth transistor, and is connected with one end of a second load resistor; a second end of the fifth transistor is connected with a first end of the seventh transistor, and a control end of the seventh transistor is used for receiving negative differential data of front-stage serial differential data; a second end of the sixth transistor is connected with a first end of the eighth transistor, and a control end of the eighth transistor is used for receiving positive differential data of front-stage serial differential data; control ends of the ninth transistor and the tenth transistor receive a main-stage bias voltage input; a second end of the ninth transistor is connected with a first end of the eleventh transistor, and a control end of the eleventh transistor is used for receiving positive differential data of main-stage serial differential data; a second end of the tenth transistor is connected with a first end of the twelfth transistor, and a control end of the twelfth transistor is used for receiving negative differential data of main-stage serial differential data; control ends of the thirteenth transistor and the fourteenth transistor receive a rear-stage bias voltage input; a second end of the thirteenth transistor is connected with a first end of the fifteenth transistor, and a control end of the fifteenth transistor is used for receiving negative differential data of rear-stage serial differential data; a second end of the fourteenth transistor is connected with a first end of the sixteenth transistor, and a control end of the sixteenth transistor is used for receiving positive differential data of rear-stage serial differential data; second ends of the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor and the sixteenth transistor are grounded; one end of the first capacitor is connected with the second end of the tenth transistor, and the other end of the first capacitor is connected with the control end of the eleventh transistor; one end of the second capacitor is connected with the second end of the ninth transistor, and the other end of the second capacitor is connected with the control end of the twelfth transistor.

8. The high-speed interface transmitter circuit of claim 1, wherein, The data serialization circuit comprises two groups in parallel, and the number of the equalization driving circuits is also two groups.

9. A high speed interface transmitter chip, characterized by The high-speed interface transmitter circuit comprises the high-speed interface transmitter circuit according to any one of claims 1-8.

10. An electronic device, comprising: The high-speed interface transmitter chip comprises the high-speed interface transmitter circuit according to claim 9.

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