Phase Locked Loop with Sampling Circuit

Abstract

The present invention is a phase-locked loop having a sampling circuit. The phase-locked loop includes a voltage-controlled oscillator for generating a phase-locked output signal, whose oscillation frequency is controlled by a control signal; a phase detector for generating a phase signal, which represents the phase difference between the phase-locked output signal and a reference signal; a loop filter that receives the phase signal; a switch; and a sampling circuit that receives the control signal of the voltage-controlled oscillator through the switch and generates a code representing the control signal accordingly.

Description

Technical Field

[0001] The present invention relates to a phase-locked loop, and more particularly to a phase-locked loop capable of quickly locking phase. Background Art

[0002] A phase-locked loop (PLL) is a control system whose output signal phase is related to the input signal phase. After a period of time, the phase-locked loop can lock the phases of the output signal and the input signal.

[0003] Phase-locked loops are widely used in various applications. For example, in monitoring applications with limited power supply (such as battery-powered), an ultra-low power sensor design is adopted. However, traditional phase-locked loops cannot quickly lock phase to save power. In addition, the traditional phase-locked loop design is always on, while the monitoring application with limited power supply is only turned on when movement is detected. Therefore, the traditional always-on phase-locked loop wastes the precious power of the monitoring application with limited power supply.

[0004] Therefore, it is urgent to propose a novel mechanism to overcome the deficiencies of traditional phase-locked loops. Summary of the Invention

[0005] In view of the above, one of the objectives of the embodiments of the present invention is to provide a phase-locked loop that can be turned off and quickly turned on to save power.

[0006] According to an embodiment of the present invention, a phase-locked loop includes a voltage-controlled oscillator, a phase detector, a loop filter, a switch, and a sampling circuit. The voltage-controlled oscillator is used to generate a phase-locked output signal, and its oscillation frequency is controlled by a control signal. The phase detector is used to generate a phase signal representing the phase difference between the phase-locked output signal and a reference signal. The loop filter receives the phase signal. The sampling circuit receives the control signal of the voltage-controlled oscillator through the switch and generates a code representing the control signal accordingly.

[0007] Preferably, the loop filter includes a low-pass filter.

[0008] Preferably, the switch has a first terminal connected to the input node of the voltage-controlled oscillator, a second terminal for directly connecting the input node of the voltage-controlled oscillator to the output contact of the loop filter, and a third terminal for connecting the input node of the voltage-controlled oscillator to the output node of the sampling circuit.

[0009] Preferably, the phase detector includes: a frequency divider for dividing the frequency of the phase-locked output signal to generate a divided frequency signal; and a phase-frequency detector that receives the divided frequency signal to determine the phase difference between the reference signal and the divided frequency signal.

[0010] Preferably, the phase detector further includes: a charge pump that outputs positive and negative current pulses to the loop filter.

[0011] Preferably, the sampling circuit includes: an analog-to-digital converter that switches to receive the control signal and converts the control signal in analog form into the encoded signal in digital form; a storage device for storing the encoded signal in digital form; and a digital-to-analog converter for converting the encoded signal in digital form into a sampling control signal, which is provided to the voltage-controlled oscillator via the switch.

[0012] Preferably, the storage device includes an S-type latch.

[0013] Preferably, the phase detector and the analog-to-digital converter are turned on by an active first enabling signal, the voltage-controlled oscillator is turned on by an active second enabling signal, and the digital-to-analog converter is turned on when both the second enabling signal and the inverted first enabling signal are active.

[0014] Preferably, when the first enabling signal is active, the switch directly connects the voltage-controlled oscillator to the output node of the loop filter but disconnects from the digital-to-analog converter; when the first enabling signal is inactive, the switch connects the voltage-controlled oscillator to the output node of the digital-to-analog converter but disconnects from the loop filter.

[0015] Preferably, when the first enabling signal and the second enabling signal are active, phase locking is performed to finally generate the phase-locked output signal with a stable frequency, and the analog-to-digital converter converts the control signal in analog form into the encoded signal in digital form and stores it in the storage device.

[0016] Preferably, when the first enabling signal and the second enabling signal are inactive, the phase detector, the analog-to-digital converter, the digital-to-analog converter, and the voltage-controlled oscillator are turned off.

[0017] Preferably, when the first enabling signal is inactive and the second enabling signal is active, the digital-to-analog converter provides the sampling control signal to the voltage-controlled oscillator to generate the phase-locked output signal with a stable frequency.

[0018] By the above technical solutions, the present invention has at least the following advantageous effects: The phase-locked loop with the sampling circuit of the present invention can be turned off and quickly turned on to save power. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A block diagram showing the phase-locked loop according to an embodiment of the present invention.

[0020] Figure 2 ILLUSTRATION Figure 1 A detailed block diagram of the phase-locked loop.

[0021] Figure 3 Illustrate the timing diagrams of the first enabling signal and the second enabling signal.

[0022]

Description of Main Component Symbols

[0023] 100: Phase Locked Loop 11: Voltage Controlled Oscillator

[0024] 12: Phase Detector 121: Frequency Divider

[0025] 122: Phase Frequency Detector 123: Charge Pump

[0026] 13: Loop Filter 14: Sampling Circuit

[0027] 141: Analog-to-Digital Converter 142: Storage Device

[0028] 143: Digital-to-Analog Converter REF: Reference Signal

[0029] Vp: Phase Signal SW: Switch

[0030] Ctr: Control Signal PLL_out: Phase Locked Output Signal

[0031] Loop_en: First Enabling Signal VCO_en: Second Enabling Signal

[0032] t1~t6: Time Detailed Implementation Manner

[0033] Figure 1 Show the block diagram of the phase locked loop (PLL) 100 according to an embodiment of the present invention. The phase locked loop 100 of this embodiment may include a voltage controlled oscillator (VCO) 11 for generating a phase locked output signal PLL_out, whose oscillation frequency is controlled by a control signal Ctr. The phase locked loop 100 may include a phase detector 12 for generating a phase signal Vp, which represents the phase difference between the phase locked output signal PLL_out and the reference signal REF. The phase locked loop 100 may include a loop filter 13 (such as a low-pass filter), which receives the phase signal Vp of the phase detector 12.

[0034] According to one of the features of this embodiment, the phase locked loop 100 may include a sampling circuit 14, which receives the control signal Ctr of the voltage controlled oscillator 11 through a switch SW, so as to generate a code representing the control signal Ctr. In this embodiment, the switch SW (such as a single-pole double-throw switch) has a first terminal connected to the input node of the voltage controlled oscillator 11 (i.e., the control signal Ctr), which can be switched to be directly connected to the output contact of the loop filter 13 (through the second terminal), or switched to be connected to the output node of the sampling circuit 14 (through the third terminal).

[0035] Figure 2 Exemplification Figure 1 Detailed block diagram of the phase-locked loop 100 shown in the figure. In this embodiment, the phase detector 12 may include a frequency divider 121 for dividing the frequency of the phase-locked output signal PLL_out, thereby generating a divided signal. The phase detector 12 may include a phase-frequency detector 122 that receives the reference signal REF and the divided signal (from the frequency divider 121) and determines the phase difference between the two. The phase detector 12 may include a charge pump 123 that, as a bipolar switched current source, can output positive and negative current pulses to the loop filter 13.

[0036] In this embodiment, the sampling circuit 14 may include an analog-to-digital converter (ADC) 141 that switches to receive the control signal Ctr (of the voltage-controlled oscillator 11) and converts the (analog) control signal Ctr into a digital code. The sampling circuit 14 may include a storage device 142 for storing the digital code (from the analog-to-digital converter 141). In one embodiment, the storage device 142 may include a latch or a flip-flop, such as an S-type latch. The sampling circuit 14 may include a digital-to-analog converter (DAC) 143 for converting the digital code (stored in the storage device 142) into a sampling control signal, which may be provided to the voltage-controlled oscillator 11 via the switch SW.

[0037] According to one of the features of this embodiment, as Figure 2 shown, the phase detector 12 (i.e., the frequency divider 121, the phase-frequency detector 122, and the charge pump 123) and the analog-to-digital converter 141 can be turned on by an active (e.g., "1") first enable signal Loop_en. The voltage-controlled oscillator 11 can be turned on by an active (e.g., "1") second enable signal VCO_en. And when the inverted first enable signal Loop_en* and the second enable signal VCO_en are both active (e.g., "1"), the digital-to-analog converter 143 can be turned on. When the first enable signal Loop_en is active, the switch SW directly connects the voltage-controlled oscillator 11 to the output node of the loop filter 13 but disconnects it from the digital-to-analog converter 143. Conversely, when the first enable signal Loop_en is inactive (e.g., "0"), the switch SW connects the voltage-controlled oscillator 11 to the output node of the digital-to-analog converter 143 but disconnects it from the loop filter 13.

[0038] Figure 3 Illustrate the timing diagrams of the first enabling signal Loop_en and the second enabling signal VCO_en. When operating the phase-locked loop 100, when the first enabling signal Loop_en is active (e.g., "1"), the switch SW directly connects the voltage-controlled oscillator 11 to the output node of the loop filter 13. At the same time, the phase detector 12 and the analog-to-digital converter 141 are turned on, and the digital-to-analog converter 143 is turned off.

[0039] When the first enabling signal Loop_en and the second enabling signal VCO_en are active (e.g., "1"), during, for example, t1 to t2, the phase-locked loop 100 performs phase locking. After a period of time, a phase-locked output signal PLL_out with a stable frequency is finally generated. At this time, the analog-to-digital converter 141 converts the (analog) control signal Ctr into a digital code and stores it in the storage device 142.

[0040] When the first enabling signal Loop_en becomes inactive (e.g., "0"), during, for example, t2 to t3 or t3 to t4, the switch SW connects the voltage-controlled oscillator 11 to the output node of the digital-to-analog converter 143. At the same time, the analog-to-digital converter 141 and the phase detector 12 are turned off.

[0041] When the first enabling signal Loop_en and the second enabling signal VCO_en are inactive (e.g., "0"), during, for example, t2 to t3, the phase detector 12, the analog-to-digital converter 141, the digital-to-analog converter 143, and the voltage-controlled oscillator 11 are turned off.

[0042] When the first enabling signal Loop_en is inactive and the second enabling signal VCO_en is active, during, for example, t3 to t4, the voltage-controlled oscillator 11 and the digital-to-analog converter 143 are turned on. The digital-to-analog converter 143 can provide a sampling control signal to the voltage-controlled oscillator 11, which can quickly generate a phase-locked output signal PLL_out with a stable frequency, just as in the previous case at time t2.

[0043] According to the above embodiment, the entire phase-locked loop 100 performs phase locking only during a period (e.g., t1 to t2). The digital code equal to the control signal Ctr (converted by the analog-to-digital converter 141) can be stored (in the storage device 142). After that, the phase-locked loop 100 can be turned off. When a clock is needed (e.g., during t5 to t6), only the voltage-controlled oscillator 11 and the digital-to-analog converter 143 need to be turned on to quickly obtain the phase-locked output signal PLL_out.

[0044] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A phase-locked loop with a sampling circuit, characterized in that, Comprising: A voltage-controlled oscillator for generating a phase-locked output signal, whose oscillation frequency is controlled by a control signal; A phase detector for generating a phase signal, which represents the phase difference between the phase-locked output signal and a reference signal; A loop filter that receives the phase signal; A switch; And A sampling circuit that receives the control signal of the voltage-controlled oscillator through the switch, and accordingly generates a code representing the control signal; The sampling circuit comprises: An analog-to-digital converter that switches to receive the control signal and converts the control signal in analog form into the code in digital form; A storage device for storing the code in digital form; and A digital-to-analog converter for converting the code in digital form into a sampling control signal, which is provided to the voltage-controlled oscillator through the switch; During the power-saving mode, power supply to the voltage-controlled oscillator, the phase detector, and the sampling circuit is stopped. At the end of the power-saving mode, only the voltage-controlled oscillator and the digital-to-analog converter are turned on, and the phase-locked output signal can be obtained according to the code.

2. The phase-locked loop with a sampling circuit according to claim 1, characterized in that, The loop filter includes a low-pass filter.

3. The phase-locked loop with a sampling circuit according to claim 1, wherein, The switch has a first terminal connected to the input node of the voltage-controlled oscillator; a second terminal for directly connecting the input node of the voltage-controlled oscillator to the output contact of the loop filter; and a third terminal for connecting the input node of the voltage-controlled oscillator to the output node of the sampling circuit.

4. The phase-locked loop with a sampling circuit according to claim 1, characterized in that, The phase detector comprises: A frequency divider for dividing the frequency of the phase-locked output signal, thereby generating a divided signal; and A phase-frequency detector that receives to determine the phase difference between the reference signal and the divided signal.

5. The phase-locked loop with a sampling circuit according to claim 4, wherein, The phase detector further comprises: A charge pump that outputs positive and negative current pulses to the loop filter.

6. The phase-locked loop with a sampling circuit according to claim 1, wherein The storage device includes an S-type latch.

7. The phase-locked loop with a sampling circuit according to claim 1, wherein The phase detector and the analog-to-digital converter are turned on by an active first enabling signal, the voltage-controlled oscillator is turned on by an active second enabling signal, and when both the second enabling signal and the inverted first enabling signal are active, the digital-to-analog converter is turned on.

8. The phase-locked loop having a sampling circuit according to claim 7, wherein, When the first enabling signal is active, the switch directly connects the voltage-controlled oscillator to the output node of the loop filter, but disconnects from the digital-to-analog converter; when the first enabling signal is inactive, the switch connects the voltage-controlled oscillator to the output node of the digital-to-analog converter, but disconnects from the loop filter.

9. The phase-locked loop with a sampling circuit according to claim 7, wherein, When the first enabling signal and the second enabling signal are active, phase locking is performed to finally generate the phase-locked output signal with a stable frequency, and the analog-to-digital converter converts the control signal in analog form into the code in digital form and stores it in the storage device.

10. The phase-locked loop with a sampling circuit according to claim 7, wherein, When the first enabling signal and the second enabling signal are inactive, the phase detector, the analog-to-digital converter, the digital-to-analog converter, and the voltage-controlled oscillator are turned off.

11. The phase-locked loop with a sampling circuit according to claim 7, wherein, When the first enabling signal is inactive and the second enabling signal is active, the digital-to-analog converter provides the sampling control signal to the voltage-controlled oscillator to generate the phase-locked output signal with a stable frequency.

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