Beamforming Unit and Digital Beamforming Method with Reconfigurable Interconnection between Array Elements

Abstract

The present invention relates to a beamforming unit and a digital beamforming method with reconfigurable inter-element interconnection. The beamforming unit in the present invention includes an instruction parsing module, a weight caching module, a beam synchronization module, an amplitude-phase correction module, a weight complex multiplication module, a beam synthesis module, and an input / output interface; the digital beamforming method with reconfigurable inter-element interconnection in the present invention uses the above beamforming unit, and a digital beamforming system is composed of a plurality of distributed beamforming units, and each beamforming unit supports beamforming through data interconnection between elements. The present invention ingeniously utilizes the element channel layout, connects adjacent channels through reconfigurable interconnection and completes digital beamforming, supports minimizing the transmission distance of high-speed digital signals, reduces the driving ability of high-speed digital signals, and thus can reduce the system power consumption.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and particularly relates to a beamforming unit and a digital beamforming method with reconfigurable interconnection between array elements. Background Art

[0002] Phased array technology is a technology that realizes the electronic scanning beam pointing by controlling the phase of each array antenna. Phased array beamforming methods include analog beamforming (ABF) and digital beamforming (DBF) technologies. Compared with analog beamforming, digital beamforming has many advantages such as being easier to implement multi-beams, having low sidelobes, being convenient for channel amplitude-phase error calibration and adaptive interference cancellation, etc., and is the mainstream technical solution for current wireless signal transmission.

[0003] The principle of digital beamforming technology is as Figure 1 shown (taking receiving digital beamforming as an example). Its basic principle is to digitize each channel, perform amplitude-phase correction on each channel in the digital domain, multiply by the weight value W n representing the beam angle in the complex domain, and then perform complex multiplication on the data of each channel and add them to synthesize a path of beam data.

[0004] The mathematical model of digital beamforming is expressed as:

[0005]

[0006] where D represents the finally formed beam, D n is the complex baseband signal of each channel, and W n is the beam weighting coefficient corresponding to each channel.

[0007] In current design solutions, the ADC / DAC that completes channel digitization is an independent chip, and all amplitude-phase correction, weight complex multiplication, and multi-channel synthesis of beamforming are implemented in another beamforming processor chip, such as in an FPGA. High-speed signal lines and high-speed connectors are required between the ADC / DAC and the FPGA. An N-star connection mode is formed between the N high-speed data channels in a sub-array and the beamforming processor. The traditional digital beamforming system architecture is as Figure 2 shown. This digital beamforming architecture has the following limitations:

[0008] 1. The high-speed data signal traces between chips are relatively long, requiring strong signal driving capabilities, which ultimately leads to additional system power consumption overhead.

[0009] 2. In addition, a series of problems such as signal integrity (SI) will be introduced due to the interconnection of high-speed signal lines through connectors. Additional equalization and pre-emphasis processing need to be done inside the chip to ensure signal integrity, further increasing the system power consumption and cost.

[0010] 3. The processing capabilities of FPGAs or dedicated beamforming processor chips are limited. Each chip can only handle beamforming complex multiplication and synthesis operations for a limited number of channels. When the number of array channels is large, multiple FPGA chips or multiple dedicated beamforming processor chips are required to form a tree-shaped synthesis network, resulting in an increase in system cost and limiting the market penetration of digital phased arrays. Summary of the Invention

[0011] In view of the above problems, the present invention discloses a digital beamforming method based on reconfigurable interconnection between array elements.

[0012] Technical Solution of the Present Invention:

[0013] One aspect of the present invention provides a beamforming unit, which includes an instruction parsing module, a weight caching module, a beam synchronization module, an amplitude-phase correction module, a weight complex multiplication module, a beam synthesis module, and an input-output interface;

[0014] The instruction parsing module is connected to the host computer instruction input port, the amplitude-phase correction module, the weight caching module, and the host computer instruction output port;

[0015] The weight caching module is connected to the instruction parsing module and the beam synchronization module;

[0016] The beam synchronization module is connected to the weight caching module, the weight complex multiplication module, and the beam synthesis module;

[0017] The amplitude-phase correction module is connected to the unit interface, the weight complex multiplication module, and the instruction parsing module;

[0018] The weight complex multiplication module is connected to the amplitude-phase correction module, the beam synchronization module, and the beam synthesis module;

[0019] The beam synthesis module is connected to the previous-stage beam synthesis input port, the beam synthesis output port of this unit, the weight complex multiplication module, and the beam synchronization module.

[0020] Furthermore, the instruction parsing module receives instructions input by the host computer. These instructions include channel correction data and beam instructions. The instruction parsing module parses out the channel correction values according to the known protocol format and outputs them to the amplitude-phase correction module, and parses out the beam instructions and outputs them to the weight caching module; after buffering the instructions input by the host computer for driving, the instruction parsing module directly outputs them to the instruction parsing module of the next-stage beamforming unit.

[0021] Furthermore, the weight cache module supports initializing during startup to store all beam point weights at once. In this mode, the weight cache module is a RAM module, and a weight lookup table is generated in the RAM module. Subsequently, the weight of the current beam point can be output to the beam synchronization module according to the beam point index number of the beam command.

[0022] Furthermore, the weight cache module is a module for storing data, including flash, RRAM, or MRAM. The instruction parsing module parses out consecutive beam weights and caches them in the weight cache module. In this mode, the weight cache module is in a FIFO mode and outputs the current beam weight to the beam synchronization module.

[0023] Furthermore, the beam synchronization module realizes multi-level beam synthesis data synchronization and marks the current beam weight.

[0024] Furthermore, when the beamforming unit receives beamforming:

[0025] The weight complex multiplication module for receiving beamforming performs complex multiplication on the received data and the beam weight, and simultaneously inherits the beam synchronization mark and passes the complex multiplication result and the beam synchronization mark to the beam synthesis module;

[0026] The synchronous synthesis module, according to the beam synchronization mark, adds and synthesizes the complex multiplication result of this unit and the beam synthesis result of the previous stage with the same beam synchronization mark. It forms a data frame structure with the inherited beam synchronization mark and the synthesized data and outputs it to the next-stage beamforming unit.

[0027] Furthermore, when the beamforming unit transmits beamforming:

[0028] For transmit beamforming, the beam synthesis module distributes data, that is, the input of the weight complex multiplication module of each beamforming unit is the same beam data;

[0029] After distributing the data, it simultaneously passes the beam synchronization mark of the beam synchronization module and outputs the data to the input of the weight complex multiplication module;

[0030] The weight complex multiplication module performs complex multiplication on the beam point weight of the beam synchronization module and the beam data, and outputs the result to the amplitude-phase correction module;

[0031] The amplitude-phase correction module performs channel amplitude-phase correction according to the channel correction value and outputs it to the DAC of the channel to complete channel digitization.

[0032] On the other hand, the present invention provides a digitally reconfigurable beamforming method between array elements. Using the above beamforming unit, a digital beamforming system is composed of a plurality of distributed beamforming units, and each beamforming unit supports beamforming through data interconnection between array elements.

[0033] Advantages of the present invention:

[0034] The present invention ingeniously utilizes the array element channel layout, completes digital beamforming by reconfigurable interconnection of adjacent channels, supports minimizing the transmission distance of high-speed digital signals, reduces the driving ability of high-speed digital signals, and thus can reduce system power consumption.

[0035] In addition, the present invention can reduce the complexity of system board-level wiring, reduce the processing and debugging costs of sub-array components, and at the same time, the present invention supports reconfigurable interconnection of commands and data between array elements at the array level.

[0036] Furthermore, the scale of each beamforming unit of the present invention is very small, which is very convenient for integration with the front-end ADC / DAC, including but not limited to chip integration or SIP package integration, etc., reduces the dependence of the system on expensive chips such as large-scale beamforming processors like FPGA, and reduces system costs. Description of the Drawings

[0037] Figure 1 is the schematic diagram of digital beamforming technology;

[0038] Figure 2 is the architecture of a traditional digital beamforming system;

[0039] Figure 3 is the serial daisy-chain connection diagram of beamforming units;

[0040] Figure 4 is a 16-channel receiving sub-array;

[0041] Figure 5 is a 48-element L-band transmitting sub-array board. Detailed Embodiments

[0042] Each beamforming unit in the present invention includes an instruction parsing module, a weight buffer module, a beam synchronization module, an amplitude-phase correction module, a weight complex multiplication module, a beam synthesis module, and an input-output interface. Among them, the instruction parsing module is connected to the host computer instruction input port, the amplitude-phase correction module, the weight buffer module, and the host computer instruction output port; the weight buffer module is connected to the instruction parsing module and the beam synchronization module; the beam synchronization module is connected to the weight buffer module, the weight complex multiplication module, and the beam synthesis module; the amplitude-phase correction module is connected to the unit interface, the weight complex multiplication module, and the instruction parsing module; the weight complex multiplication module is connected to the amplitude-phase correction module, the beam synchronization module, and the beam synthesis module; the beam synthesis module is connected to the previous-stage beam synthesis input port, the beam synthesis output port of this unit, the weight complex multiplication module, and the beam synchronization module.

[0043] Furthermore, the instruction parsing module receives the instructions input by the host computer. The instructions include channel correction data and beam instructions. The instruction parsing module parses out the channel correction value according to the known protocol format and outputs it to the amplitude-phase correction module, and parses out the beam instructions and outputs them to the weight buffer module. After buffering the host computer instructions for driving, the instruction parsing module directly outputs them to the instruction parsing module of the next-stage beamforming module, that is, the host computer instructions form a serial daisy-chain connection among the beamforming units.

[0044] The weight buffer module supports initializing at startup to store all beam position weights at one time. In this way, the weight buffer module can be a RAM module, and a weight lookup table is generated in the RAM. Subsequently, the weight of the current beam position can be output to the beam synchronization module according to the beam position index number of the beam instruction. The weight buffer module can also be any module that can store and read weights, such as flash, RRAM, MRAM, etc., which are modules that can store data. In form, it can be embedded or non-embedded; it can also be that the instruction parsing module parses out continuous beam weights and caches them in the weight buffer module. In this mode, the weight buffer module is in a FIFO mode and outputs the current beam weight to the beam synchronization module.

[0045] The beam synchronization module realizes the synchronization of multi-stage beam synthesis data, and marks the current beam weight. The marking method can be but is not limited to a timestamp or a beam position index, etc., to prevent the subsequent pipelined synthesis module from combining different beam data.

[0046] Furthermore, the beamforming unit can be a receiving beamforming or a transmitting beamforming.

[0047] The weight complex multiplication module of the receive beamforming performs complex multiplication on the received data and the beam weights, inherits the beam synchronization flag at the same time, and passes the complex multiplication result and the beam synchronization flag to the beam synthesis module; the synchronization synthesis module, according to the beam synchronization flag, adds and synthesizes the complex multiplication result of this unit and the beam synthesis result with the same beam synchronization flag input from the previous stage, forms a data frame structure with the inherited beam synchronization flag and the synthesized data, and outputs it to the next-stage beamforming unit. The data frame transmission methods between adjacent beam synthesis modules include but are not limited to parallel data interfaces, parallel LVDS differential pairs, or serial high-speed interfaces such as SERDES interfaces, etc.

[0048] For transmit beamforming, the beam synthesis module distributes the data, that is, the input of the weight complex multiplication module of each beamforming unit is the same beam data. After distributing the data, the beam synchronization flag of the beam synchronization module is passed at the same time, and the data is output to the input of the weight complex multiplication module; the weight complex multiplication module performs complex multiplication on the beam position weights and the beam data of the beam synchronization module, and the result is output to the amplitude-phase correction module; the amplitude-phase correction module performs channel amplitude-phase correction according to the channel correction value and outputs it to the DAC of the channel to complete channel digitization.

[0049] A digital beamforming method based on reconfigurability between array elements in the present invention, the digital beamforming system is composed of N distributed beamforming units, and each beamforming unit supports beamforming through data interconnection between array elements. A special case is serial daisy-chain connection, such as Figure 3 shown.

[0050] Embodiment 1:

[0051] The technical solution of the present invention will be specifically described with a 16-channel receive sub-array. A 16-channel receive sub-array is composed of 4 receive channel chips (Rx chips). Each Rx chip contains 4 receive channels. Each receive channel converts the analog / RF signal into a digital signal by an ADC, and generates an orthogonal I / Q complex signal through digital down-conversion DDC. The above two parts are standard receive circuits, and the present invention will not elaborate here.

[0052] The host computer instructions and the beam synthesis results of the 4 Rx chips are serially connected through a daisy chain. The host computer instruction sends the amplitude-phase correction coefficient of each channel. The instruction parsing module identifies whether it is the channel correction coefficient corresponding to this chip. If it is the corresponding channel correction coefficient, it is saved; if it is not the corresponding channel, it is ignored. In this way, during the startup initialization correction stage, the distribution of the correction coefficient of each channel is completed.

[0053] In this embodiment, the beam weights of each channel are sent in real time by the host computer. The interval between each beam jump is 1 ms. The weights corresponding to the current beam positions are assigned to each channel through serial host computer instructions. The total data volume of the channel weights for each beam position of 16 channels is 16 * 2 * 16 = 512 bit. Considering redundant characters such as address resolution and weight synchronization markers, it is calculated as 1 Kbit. Assuming that parallel LVDS is used to transmit the host computer instructions and the LVDS data rate is 500 Mbps, it takes 200 ns to assign all beam weights, which is much less than the beamforming complex multiplication and beam synthesis operation time.

[0054] The beam synchronization module marks the current beam position information and adds the timestamp information to form a data frame header. The frame header can adopt the following frame structure:

[0055] Frame start bit Timestamp Beam point position index Weight coefficient 10000111 T＝0 X = 13 Y = 9 16b

[0056] The beam synchronization module inputs the frame data to the weight complex multiplication module. The weight complex multiplication module extracts the weight coefficients from the frame data and performs complex multiplication with the channel correction data output by the amplitude-phase correction module to obtain the channel beam data, and adds the beam synchronization marker information to form a frame structure data for adding and synthesizing with the previous stage complex multiplication result.

[0057] Since the multi-channel data beam synthesis is performed by serial addition, as shown in this embodiment, 16 levels of pipelining are required to complete the 16-channel final beam synthesis. To ensure the beam data synchronization between multiple channels, each beam synthesis addition is added to the complex multiplication result with the same timestamp and the same beam position.

[0058] In this embodiment, there are a total of 4 receiving Rx chips. The beam synthesis data between the chips is transmitted through high-speed serial SERDES. In a sub-array board, the distance between adjacent Rx chips can be roughly determined by the antenna element arrangement. For example, the vacuum wavelength of a 3 GHz signal is 10 cm, and the antenna element spacing is half wavelength, i.e., 5 cm. Considering the PCB dielectric constant, the length of the high-speed SERDES signal line between two Rx chips does not exceed 5 cm, which can reduce the power consumption overhead such as equalization pre-emphasis of the SERDES interface, and at the same time, it is easier to ensure signal integrity.

[0059] In terms of the sub-array layout, all host computer instructions, beam synthesis inputs / outputs are connected serially to adjacent chips, and the PCB traces are more concise, reducing the difficulty of PCB design and debugging. See Figure 4 .

[0060] Embodiment 2:

[0061] Taking a 48-element L-band transmitting sub-array board as an example to illustrate the method of reconfigurable digital beamforming between array elements.

[0062] AsFigure 5 As shown, an L-band transmitting subarray board consists of 48 array elements. The DACs of the two integrated digital beamforming units are one chip 1, and 24 transmitting chips (Tx chips) are used on the subarray board.

[0063] Each chip integrates the digital beamforming unit based on reconfigurable inter-element interconnection described in the present invention. Therefore, the subarray board is divided into 6 beam distribution regions 2. The previous-stage DBF beamforming board sends beam data to the 6 functional regions through the connector 3 at the middle position of the subarray board.

[0064] One Tx chip in each beam distribution region receives the beam data and completes the beam distribution transfer among 4 chips within the region, as shown by the black arrows in each region in the attached drawing. Each channel of each chip completes complex multiplication and channel correction, and is transmitted through DUC and DAC to complete the channel beamforming transmission function. This process is the reverse process of the 4Rx chip in Embodiment 1 and will not be elaborated here.

Claims

1. A beamforming unit, characterized in that: It includes an instruction parsing module, a weight caching module, a beam synchronization module, an amplitude-phase correction module, a weight complex multiplication module, a beam synthesis module, and an input / output interface; The instruction parsing module is connected to the host computer instruction input port, the amplitude-phase correction module, the weight caching module, and the host computer instruction output port; The weight caching module is connected to the instruction parsing module and the beam synchronization module; The beam synchronization module is connected to the weight caching module, the weight complex multiplication module, and the beam synthesis module; The amplitude-phase correction module is connected to the unit interface, the weight complex multiplication module, and the instruction parsing module; The weight complex multiplication module is connected to the amplitude-phase correction module, the beam synchronization module, and the beam synthesis module; The beam synthesis module is connected to the pre-stage beam synthesis input port, the beam synthesis output port of this unit, the weight complex multiplication module, and the beam synchronization module; The instruction parsing module receives the instructions input by the host computer. These instructions include channel correction data and beam instructions. The instruction parsing module parses out the channel correction value according to the known protocol format and outputs it to the amplitude-phase correction module, and parses out the beam instructions and outputs them to the weight caching module; after buffering the instructions input by the host computer, the instruction parsing module directly outputs them to the instruction parsing module of the next-stage beamforming unit; The beam synchronization module realizes the synchronization of multi-stage beam synthesis data and marks the current beam weights; When the beamforming unit receives beamforming: The weight complex multiplication module that receives beamforming performs complex multiplication on the received data and the beam weights, and at the same time inherits the beam synchronization mark and passes the complex multiplication result and the beam synchronization mark to the beam synthesis module; The synchronization synthesis module, according to the beam synchronization mark, adds and synthesizes the complex multiplication result of this unit and the beam synthesis result with the same beam synchronization mark input from the previous stage, forms a data frame structure with the inherited beam synchronization mark and the synthesized data, and outputs it to the next-stage beamforming unit; When the beamforming unit transmits beamforming: For transmit beamforming, the beam synthesis module distributes the data, that is, the input of the weight complex multiplication module of each beamforming unit is the same beam data; After distributing the data, it simultaneously transfers the beam synchronization mark of the beam synchronization module and outputs the data to the input of the weight complex multiplication module; The weight complex multiplication module performs complex multiplication on the beam position weights of the beam synchronization module and the beam data, and outputs the result to the amplitude-phase correction module; The amplitude-phase correction module performs channel amplitude-phase correction according to the channel correction value and outputs it to the DAC of the channel to complete channel digitization.

2. The beamforming unit according to claim 1, wherein: The weight caching module supports power-on initialization to store all beam position weights at one time. In this way, the weight caching module is a RAM module, and a weight lookup table is generated in the RAM module. Subsequently, the weight of the current beam position can be output to the beam synchronization module according to the beam position index number of the beam instruction.

3. The beamforming unit according to claim 1, wherein: The weight cache module is a module for storing data; the continuous beam weights are parsed by the instruction parsing module and cached in the weight cache module. In this mode, the weight cache module is in a FIFO mode and outputs the current beam weight to the beam synchronization module.

4. A method for reconfigurable digital beamforming between array elements, which uses a beamforming unit according to any one of claims 1 to 3, and a digital beamforming system is constituted by a plurality of distributed beamforming units as described above. Each beamforming unit supports beamforming through data interconnection between array elements.

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