Self-detection circuit system, self-detection chip and circuit system self-detection method

Abstract

The present invention discloses a self-detection circuit system, comprising: a chip, including a first chip pin and a second chip pin; a first detection circuit, including a power supply terminal, a detection resistor and a first switch, the power supply terminal is sequentially connected to the first chip pin through the detection resistor and the first switch; a second detection circuit, including a second switch and a chip ground terminal, the second chip pin is connected to the chip ground terminal through the second switch; a voltage sampling circuit, one end is connected to the power supply terminal through the detection resistor, and the other end is connected to the chip ground terminal; and a circuit board, including a chip fixture and a third switch, the chip fixture is provided with a first circuit board pin and a second circuit board pin, the first circuit board pin is connected to the second circuit board pin through the third switch; a controller, controlling the third switch and communicating with the chip; wherein, the chip is received in the fixture, and the chip pins are connected to the corresponding circuit board pins, with a simple structure and good detection effect. The present invention also discloses a self-detection chip and a self-detection method for the circuit system.

Description

Technical Field

[0001] The present invention relates to the field of chip detection, and in particular to a self-detection circuit system capable of self-detection, a self-detection chip in the self-detection circuit system, and a method for self-detecting a line system based on the self-detection circuit system. Background Art

[0002] With the development of science and technology, more and more electronic devices have entered people's lives. As the core component of electronic devices, the functionality and stability of chips determine whether electronic devices can meet people's actual usage requirements, and the research on chips has received more and more attention.

[0003] During the manufacturing process, multi-pin chips generally need to perform CP (chip probe) tests on their wafers and FT (final test) tests on the packaged chips. In the CP test, signals are applied through the probes on the test fixture to the PAD pins of the wafer chip, and then the functions and performances of the chip are tested. In the FT test, the chip is placed in the test fixture and a certain pressure is applied to the chip to make the PIN pins of the chip contact well with the pins of the test fixture, and then the functions and performances of the chip are tested. During use, whether the pins are in good contact is also a necessary condition to ensure the normal function of the electronic device.

[0004] Currently, for the connection detection of chip pins, the conventional method is to detect through external detection devices or instruments, which consumes time and manpower. Summary of the Invention

[0005] The present invention aims to at least solve one of the technical problems in the related art to some extent. For this purpose, the present invention provides a self-detection circuit system capable of autonomously detecting the connection state, a self-detection chip in the self-detection circuit system, and a method for self-detecting a line system based on the self-detection circuit system.

[0006] An embodiment of the present invention provides a self-detection circuit system, including:

[0007] A chip, the chip includes:

[0008] A first chip pin and a second chip pin;

[0009] A first detection circuit, including a power supply terminal, a detection resistor, and a first switch, the power supply terminal is sequentially connected to the first chip pin through the detection resistor and the first switch;

[0010] A second detection circuit, including a second switch and a chip ground terminal, the second chip pin is connected to the chip ground terminal through the second switch;

[0011] A voltage sampling circuit, one end of the voltage sampling circuit is connected to the power supply terminal through the detection resistor, and the other end is connected to the chip ground terminal;

[0012] A circuit board, the circuit board includes a chip fixture and a third switch, the chip fixture is provided with a first circuit board pin and a second circuit board pin, and the first circuit board pin is connected to the second circuit board pin through the third switch; and,

[0013] A controller, which controls the third switch on the circuit board and communicates with the chip;

[0014] Wherein, the chip is received in the fixture, the first chip pin is connected to the first circuit board pin, and the second chip pin is connected to the second circuit board pin.

[0015] Preferably, the chip further includes a first GPIO circuit and a second GPIO circuit, the first GPIO circuit is connected to the first chip pin, and the second GPIO circuit is connected to the second chip pin.

[0016] Preferably, the chip further includes a third chip pin and a third detection circuit, the third detection circuit includes a fourth switch and a chip ground terminal, and the third chip pin is connected to the chip ground terminal through the fourth switch;

[0017] The circuit board further includes a fifth switch, the fixture is further provided with a third circuit board pin, the first circuit board pin is further connected to the third circuit board pin through the fifth switch, the third chip pin is connected to the third circuit board pin, and the controller controls the fifth switch on the circuit board to communicate with the chip.

[0018] Preferably, the chip further includes a third GPIO circuit, and the third GPIO circuit is connected to the third chip pin.

[0019] Preferably, the first GPIO circuit is in a high impedance state when the first switch is turned on, and can be configured as an output or an input or a high impedance state when the first switch is turned off, the second GPIO circuit is in a high impedance state when the second switch is turned on, and can be configured as an output or an input or a high impedance state when the second switch is turned off, and the third GPIO circuit is in a high impedance state when the fourth switch is turned on, and can be configured as an output or an input or a high impedance state when the fourth switch is turned off.

[0020] An embodiment of the present invention further provides a self-detecting chip, including:

[0021] A first chip pin and a second chip pin;

[0022] The first detection circuit includes a power supply terminal, a detection resistor, and a first switch. The power supply terminal is sequentially connected to the first chip pin through the detection resistor and the first switch.

[0023] The second detection circuit includes a second switch and a chip ground terminal. The second chip pin is connected to the chip ground terminal through the second switch; and,

[0024] The voltage sampling circuit, one end of the voltage sampling circuit is connected to the power supply terminal through the detection resistor, and the other end is connected to the chip ground terminal.

[0025] Preferably, the self-detection chip further includes a first GPIO circuit and a second GPIO circuit. The first GPIO circuit is connected to the first chip pin, and the second GPIO circuit is connected to the second chip pin.

[0026] Preferably, the self-detection chip further includes a third chip pin and a third detection circuit. The third detection circuit includes a fourth switch and a chip ground terminal. The third chip pin is connected to the chip ground terminal through the fourth switch.

[0027] Preferably, the self-detection chip further includes a third GPIO circuit, and the third GPIO circuit is connected to the third chip pin.

[0028] An embodiment of the present invention further provides a circuit system self-detection method. The circuit system self-detection method is applied to the self-detection circuit system as described above. The circuit system self-detection method includes:

[0029] The controller controls the first GPIO circuit and the second GPIO circuit of the chip to output a high resistance.

[0030] The controller controls the first switch, the second switch of the chip, and the third switch of the circuit board to conduct.

[0031] Detect the voltage difference across the voltage sampling unit.

[0032] Determine that the voltage difference is less than a preset threshold, and output a normal contact detection result for the first chip pin and the second chip pin; or, determine that the voltage difference is not less than the preset threshold, and output an abnormal contact detection result for the first chip pin and the second chip pin.

[0033] The controller controls the first switch, the second switch of the chip, and the third switch of the circuit board to disconnect.

[0034] And / or, the circuit system self-detection method includes:

[0035] Control the first GPIO circuit and the third GPIO circuit of the chip to output a high resistance.

[0036] Turn on the first switch and the fourth switch of the chip and the fifth switch of the circuit board;

[0037] Detect the voltage difference across the voltage sampling unit;

[0038] Determine that the voltage difference is less than the preset threshold, and output the detection result that the contact between the first chip pin and the third chip pin is normal; or, determine that the voltage difference is not less than the preset threshold, and output the detection result that the contact between the first chip pin and the third chip pin is abnormal;

[0039] Turn off the first switch and the fourth switch of the chip and the fifth switch of the circuit board.

[0040] In the above self-detection circuit system and self-detection chip of the present invention, by setting a first detection circuit and a second detection circuit in the chip, after the chip is connected to the circuit board, the detection circuit, the chip pins, and the circuit board pins form a complete series circuit, and then the voltage at the voltage detection points of the first detection circuit and the second detection circuit is collected respectively. The impedance detection is realized by detecting the voltage difference and further judging the range of the voltage difference. When the voltage difference is small, it indicates that the contact impedance between the corresponding chip pin and the circuit board pin is small and does not affect the normal function; the above self-detection chip and self-detection circuit system have a simple structure and good detection effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope of the present invention.

[0042] Figure 1 is a schematic diagram of the frame structure of the self-detection circuit system provided by the embodiment of the present invention;

[0043] Figure 2 is a schematic diagram of the frame structure of the self-detection circuit system provided by another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The following will describe in detail the embodiments of the present invention, and the examples of the embodiments are shown in the drawings. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0045] The following will describe in detail the embodiment of the horizontal calibration method according to the present invention with reference to the drawings.

[0046] An embodiment of the present invention provides a self-detection circuit system, which is applied to a test system of an electronic device (such as a navigation device, a smart set-top box, a computer device, a server, a mobile phone, etc.). The self-detection circuit system 200 includes a chip and a circuit board. The chip can be a positioning chip, an audio-video chip, a communication chip, a power chip, a driving chip, a decoding chip, etc. It can be understood that after the chip is assembled on the circuit board, the above specific functions are realized. The chip and the circuit board perform self-detection through the solution of the embodiment of the present invention. After the detection is normal, it enters the working state normally.

[0047] Please refer to Figure 1 , an embodiment of the present invention provides a self-detection circuit system 300, including:

[0048] A chip 100, the chip 100 includes:

[0049] A first chip pin 10 and a second chip pin 15;

[0050] A first detection circuit 20, including a power supply terminal 21, a detection resistor 22 and a first switch 23. The power supply terminal 21 is sequentially connected to the first chip pin 10 through the detection resistor 22 and the first switch 23;

[0051] A second detection circuit 30, including a second switch 31 and a chip ground terminal 32. The second chip pin 15 is connected to the chip ground terminal 32 through the second switch 31;

[0052] A voltage sampling circuit 40. One end of the voltage sampling circuit 40 is connected to the power supply terminal 21 through the detection resistor 22, and the other end is connected to the chip ground terminal 32;

[0053] A circuit board 200, the circuit board includes a chip fixture 201 and a third switch 202. The chip fixture 201 is provided with a first circuit board pin 203 and a second circuit board pin 204. The first circuit board pin 203 is connected to the second circuit board pin 204 through the third switch 202; and,

[0054] A controller 250, which controls the third switch 202 on the circuit board 200 and communicates with the chip 100;

[0055] Wherein, the chip 100 is received in the fixture 201, the first chip pin 10 is connected to the first circuit board pin 203, and the second chip pin 15 is connected to the second circuit board pin 204.

[0056] Specifically, the controller 250 controls the third switch 202 on the circuit board 200 and communicates with the chip 10, including: the controller 250 directly communicates with the chip 100 first and then controls the third switch 202 to conduct or turn off, or the controller 250 directly controls the third switch 202 to conduct or turn off first and then communicates with the chip 100.

[0057] In this embodiment, the chip 100 is housed in the fixture 201, and the chip pins of the chip 100 are correspondingly connected to the circuit board pins of the fixture 201, and a contact impedance is generated accordingly. Specifically, the power supply terminal 21, the detection resistor 22, the first switch 23, the first chip pin 10, the contact impedance Rx1, the first circuit board pin 203, the third switch 202, the second circuit board pin 204, the contact impedance Rx2, the second chip pin 15, the second switch 31, and the chip ground terminal 32 are sequentially connected to form a series circuit; the voltage sampling circuit 40 detects the voltage difference between the second end of the detection resistor 22 and the chip ground terminal 32. If the voltage difference is less than the preset threshold, the contact impedance Rx1 + Rx2 is small, that is, the chip pins and the circuit board pins are in good contact, otherwise the contact is poor.

[0058] Generally, when the values of the contact impedances Rx1 and Rx2 are 0 to 0.5 ohms, the contact is good; when the values are 0.5 to 2 ohms, the contact is considered poor but does not affect the chip function, only the chip performance is affected; when the values are 2 ohms to infinity, the contact is considered poor, not only the chip performance is affected, but some functions may also fail. Generally, when Rx1 + Rx2 < 1 ohm, the contact is good.

[0059] Generally, the resistance value of the detection resistor 22 can be set to 100 to 200 ohms.

[0060] Further, the chip further includes a first GPIO circuit 50 and a second GPIO circuit 55. The first GPIO circuit 50 is connected to the first chip pin 10, and the second GPIO circuit 55 is connected to the second chip pin 15. In this embodiment, the chip pins are actually GPIO pins, and the power supply terminal 21 can also be the power supply of the GPIO circuit, such as 3.3V, 1.8V, 5V, etc.

[0061] Please refer to Figure 2 , preferably, the chip 100 further includes a third chip pin 60 and a third detection circuit 70. The third detection circuit 70 includes a fourth switch 71 and a chip ground terminal 72. The third chip pin 60 is connected to the chip ground terminal 72 through the fourth switch 71.

[0062] The circuit board 200 further includes a fifth switch 205. The fixture 201 is further provided with a third circuit board pin 206. The first circuit board pin 203 is also connected to the third circuit board pin 206 through the fifth switch 205. The third chip pin 60 is connected to the third circuit board pin 206. The controller 250 controls the fifth switch 205 on the circuit board 200 to communicate with the chip 100.

[0063] The controller 250 directly communicates with the chip 100 first and then controls the fifth switch 205 to conduct or turn off; or the controller 250 directly controls the fifth switch 205 to conduct or turn off first and then communicates with the chip 100.

[0064] In this embodiment, the chip 100 is received in the fixture 201. The chip pins of the chip 100 are correspondingly connected to the circuit board pins of the fixture 201, and a contact impedance is generated accordingly. Specifically, the power supply terminal 21, the detection resistor 22, the first switch 23, the first chip pin 10, the contact impedance Rx1, the first circuit board pin 203, the third switch 202, the second circuit board pin 204, the contact impedance Rx2, the second chip pin 15, the second switch 31, and the chip ground terminal 32 are sequentially connected to form a first series circuit; the power supply terminal 21, the detection resistor 22, the first switch 23, the first chip pin 10, the contact impedance Rx1, the first circuit board pin 203, the fifth switch 205, the third circuit board pin 206, the contact impedance Rx3, the third chip pin 60, the fourth switch 71, and the chip ground terminal 72 are sequentially connected to form a series circuit, where the chip ground terminal 72 is actually the same as the chip ground terminal 32. The voltage sampling circuit 40 detects the voltage difference between the second end of the detection resistor 22 and the second ground terminal 31. If the voltage difference is less than a preset threshold, the contact impedances Rx1 and Rx3 are small, that is, the contact between the chip pins and the circuit board pins is good; otherwise, the contact is poor.

[0065] In this embodiment, the third chip pin 60, the third detection circuit 70, the fifth switch 205, and the third circuit board pin 206 are correspondingly set as a group. It can be understood that the chip 100 has three chip pins. In other embodiments, according to the different numbers of pins of the chip 100, for example, if the chip 100 has four chip pins, correspondingly, the third chip pin 60, the third detection circuit 70, the fifth switch 205, and the third circuit board pin 206 are correspondingly set as two groups; for example, if the chip 100 has five chip pins, correspondingly, the third chip pin 60, the third detection circuit 70, the fifth switch 205, and the third circuit board pin 206 are correspondingly set as three groups; and so on. In this way, multiple other pins similar to the third chip pin 60, the third detection circuit 70, the fifth switch 205, and the third circuit board pin 206 are set.

[0066] Further, the chip 100 further includes a third GPIO circuit 80, and the third GPIO circuit 80 is connected to the third chip pin 60.

[0067] Further, the first GPIO circuit 50 is in a high-impedance state when the first switch 23 is turned on, and can be configured as an output or an input or a high-impedance state when the first switch 23 is turned off; the second GPIO circuit 55 is in a high-impedance state when the second switch 31 is turned on, and can be configured as an output or an input or a high-impedance state when the second switch 31 is turned off; the third GPIO circuit 80 is in a high-impedance state when the fourth switch 71 is turned on, and can be configured as an output or an input or a high-impedance state when the fourth switch 71 is turned off.

[0068] It can be understood that for the above self-detection circuit system 300, the chip 100 therein can be disassembled from the circuit board 200 and assembled onto another circuit board to implement the same detection scheme.

[0069] An embodiment of the present invention further provides a self-detection chip, including:

[0070] A first chip pin 10 and a second chip pin 15;

[0071] A first detection circuit 20, including a power supply terminal 21, a detection resistor 22, and a first switch 23, and the power supply terminal 21 is sequentially connected to the first chip pin 10 through the detection resistor 22 and the first switch 23;

[0072] A second detection circuit 30, including a second switch 31 and a chip ground terminal 32, and the second chip pin 15 is connected to the chip ground terminal 32 through the second switch 31; and,

[0073] A voltage sampling circuit 40, one end of the voltage sampling circuit 40 is connected to the power supply terminal 21 through the detection resistor 22, and the other end is connected to the chip ground terminal 32.

[0074] Further, the chip further includes a first GPIO circuit 50 and a second GPIO circuit 55. The first GPIO circuit 50 is connected to the first chip pin 10, and the second GPIO circuit 55 is connected to the second chip pin 15.

[0075] Further, the chip 100 further includes a third chip pin 60 and a third detection circuit 70. The third detection circuit 70 includes a fourth switch 71 and a chip ground terminal 72. The third chip pin 60 is connected to the chip ground terminal 72 through the fourth switch 71.

[0076] Further, the chip 100 further includes a third GPIO circuit 80. The third GPIO circuit 80 is connected to the third chip pin 60.

[0077] It can be understood that the embodiments of the present invention also provide a detection method based on the above self-detection circuit system. The circuit system self-detection method includes:

[0078] The controller controls the first GPIO circuit and the second GPIO circuit of the chip to output a high resistance;

[0079] The controller controls the first switch, the second switch of the chip and the third switch of the circuit board to conduct;

[0080] Detect the voltage difference between the two ends of the voltage sampling unit;

[0081] Determine that the voltage difference is less than a preset threshold, and output a normal detection result for the contact between the first chip pin and the second chip pin; or, determine that the voltage difference is not less than the preset threshold, and output an abnormal detection result for the contact between the first chip pin and the second chip pin;

[0082] The controller controls the first switch, the second switch of the chip and the third switch of the circuit board to disconnect;

[0083] And / or, the circuit system self-detection method includes:

[0084] Control the first GPIO circuit and the third GPIO circuit of the chip to output a high resistance;

[0085] Control the first switch, the fourth switch of the chip and the fifth switch of the circuit board to conduct;

[0086] Detect the voltage difference between the two ends of the voltage sampling unit;

[0087] Determine that the voltage difference is less than a preset threshold, and output the detection result that the contact between the first chip pin and the third chip pin is normal; or, determine that the voltage difference is not less than the preset threshold, and output the detection result that the contact between the first chip pin and the third chip pin is abnormal;

[0088] Control the disconnection of the first switch and the fourth switch of the chip and the fifth switch of the circuit board.

[0089] In this embodiment, according to the above self-detection circuit system, the first detection circuit and the second detection circuit can be selectively turned on for detection, or the first detection circuit and the third detection circuit can be turned on for detection; or the first detection circuit and the second detection circuit can be turned on for detection first, and then the first detection circuit and the third detection circuit can be turned on for detection.

[0090] In the above self-detection chip and self-detection circuit system of the present invention, by setting a first detection circuit and a second detection circuit in the chip, after the chip is connected to the circuit board, the detection circuit, the chip pins, and the circuit board pins form a complete series circuit, and then the voltage at the voltage detection points of the first detection circuit and the second detection circuit is collected respectively. The impedance detection is realized by detecting the voltage difference and further judging the range of the voltage difference. When the voltage difference is small, it indicates that the contact impedance between the corresponding chip pin and the circuit board pin is small and does not affect the normal function; the above self-detection chip and self-detection circuit system have a simple structure and good detection effect.

[0091] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A self-detection circuit system, characterized in that, including: a chip, the chip including: a first chip pin and a second chip pin; a first detection circuit, including a power supply terminal, a detection resistor and a first switch, the power supply terminal being connected to the first chip pin through the detection resistor and the first switch in sequence; a second detection circuit, including a second switch and a chip ground terminal, the second chip pin being connected to the chip ground terminal through the second switch; a voltage sampling circuit, one end of the voltage sampling circuit being connected to the power supply terminal through the detection resistor, and the other end being connected to the chip ground terminal; a circuit board, the circuit board including a chip fixture and a third switch, the chip fixture being provided with a first circuit board pin and a second circuit board pin, the first circuit board pin being connected to the second circuit board pin through the third switch; and, a controller, controlling the third switch on the circuit board and communicating with the chip; wherein, the chip is received in the fixture, the first chip pin is connected to the first circuit board pin, and the second chip pin is connected to the second circuit board pin.

2. The self-detection circuit system according to claim 1, wherein The chip further includes a first GPIO circuit and a second GPIO circuit, the first GPIO circuit being connected to the first chip pin, and the second GPIO circuit being connected to the second chip pin.

3. The self-detection circuit system according to claim 2, wherein The chip further includes a third chip pin and a third detection circuit, the third detection circuit including a fourth switch and a chip ground terminal, the third chip pin being connected to the chip ground terminal through the fourth switch; the circuit board further includes a fifth switch, the fixture is further provided with a third circuit board pin, the first circuit board pin is further connected to the third circuit board pin through the fifth switch, the third chip pin is connected to the third circuit board pin, and the controller controls the fifth switch on the circuit board.

4. The self-detection circuit system according to claim 3, wherein The chip further includes a third GPIO circuit, the third GPIO circuit being connected to the third chip pin.

5. The self-detection circuit system according to claim 4, wherein The first GPIO circuit is in a high impedance state when the first switch is turned on, and can be configured as an output or an input or a high impedance state when the first switch is turned off, and the second GPIO circuit is in a high impedance state when the second switch is turned on; it can be configured as an output or an input or a high impedance state when the second switch is turned off; the third GPIO circuit is in a high impedance state when the fourth switch is turned on, and can be configured as an output or an input or a high impedance state when the fourth switch is turned off.

6. A self-detecting chip, characterized in that, including: a first chip pin and a second chip pin; a first detection circuit, including a power supply terminal, a detection resistor and a first switch, the power supply terminal being connected to the first chip pin through the detection resistor and the first switch in sequence; a second detection circuit, including a second switch and a chip ground terminal, the second chip pin being connected to the chip ground terminal through the second switch; and, a voltage sampling circuit, one end of the voltage sampling circuit being connected to the power supply terminal through the detection resistor, and the other end being connected to the chip ground terminal.

7. The self-testing chip according to claim 6, wherein It further includes a first GPIO circuit and a second GPIO circuit, the first GPIO circuit being connected to the first chip pin, and the second GPIO circuit being connected to the second chip pin.

8. The self-testing chip according to claim 7, wherein It further includes a third chip pin and a third detection circuit. The third detection circuit includes a fourth switch and a chip ground terminal, and the third chip pin is connected to the chip ground terminal through the fourth switch.

9. The self-testing chip according to claim 8, wherein It further includes a third GPIO circuit, and the third GPIO circuit is connected to the third chip pin.

10. A self-detection method for a circuit system, characterized in that, The circuit system self-detection method is applied to the self-detection circuit system according to any one of claims 2-5. The circuit system self-detection method includes: The controller controls the first GPIO circuit and the second GPIO circuit of the chip to output high resistance. The controller controls the first switch and the second switch of the chip and the third switch of the circuit board to conduct. Detect the voltage difference across the voltage sampling unit. Determine that the voltage difference is less than a preset threshold, and output a normal contact detection result for the first chip pin and the second chip pin; or, determine that the voltage difference is not less than the preset threshold, and output an abnormal contact detection result for the first chip pin and the second chip pin. The controller controls the first switch and the second switch of the chip and the third switch of the circuit board to disconnect. And / or, the circuit system self-detection method includes: Control the first GPIO circuit and the third GPIO circuit of the chip to output high resistance. Control the first switch and the fourth switch of the chip and the fifth switch of the circuit board to conduct. Detect the voltage difference across the voltage sampling unit. Determine that the voltage difference is less than a preset threshold, and output a normal contact detection result for the first chip pin and the third chip pin; or, determine that the voltage difference is not less than the preset threshold, and output an abnormal contact detection result for the first chip pin and the third chip pin. Control the first switch and the fourth switch of the chip and the fifth switch of the circuit board to disconnect.

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