A method and apparatus for MIPS architecture assembly instruction takeover

Abstract

The present application relates to the field of embedded system, in particular to a method and device for taking over MIPS architecture assembly instruction. Mainly include: initializing original instruction linked list, obtaining instruction to be taken over; obtaining jump address of user instruction according to secondary jump table; modifying instruction to be taken over in instruction list according to jump address of user instruction; executing instruction in instruction linked list according to modified instruction linked list. The method can ensure normal operation of source program after user program is implanted, and solve normal jump logic of program after any instruction of the program is taken over.

Description

[Technical Field]

[0001] This invention relates to the field of embedded systems, and in particular to a method and apparatus for taking over assembly instructions in a MIPS architecture. [Background Technology]

[0002] During the execution of system instructions or applications, some functions may fail to meet user needs. In practice, to ensure the normal operation of the system, it may be impossible or difficult to completely replace the original system or source program. In this case, only the instructions that fail to meet user needs can be replaced with the instructions required by the user; this process is called instruction takeover.

[0003] In typical software systems, existing instructions can be replaced with user-required instructions through a system-provided instruction takeover interface. However, the MIPS instruction architecture currently does not offer a direct method for instruction takeover.

[0004] Therefore, how to overcome the shortcomings of existing technologies and solve the problem of instruction takeover in the MIPS instruction architecture is a problem to be solved in this technical field. [Summary of the Invention]

[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention solves the problem that instruction takeover cannot be performed in the MIPS assembly instruction architecture.

[0006] The embodiments of the present invention adopt the following technical solutions:

[0007] In a first aspect, the present invention provides a method for taking over assembly instructions in a MIPS architecture, specifically comprising: initializing the original instruction list and obtaining the instructions to be taken over; obtaining the jump address of the user instruction according to the second-level jump table; modifying the instructions to be taken over in the instruction list according to the jump address of the user instruction; and executing the instructions in the instruction list according to the modified instruction list.

[0008] Preferably, obtaining the jump address of the user instruction specifically includes: obtaining address information from all secondary jump tables required by the current process, wherein the address information includes at least one or more of the following: corresponding symbol information, the module in which it is located, and the jump address; combining the address information into a secondary jump table address linked list; and obtaining the jump address of the user instruction based on the secondary jump table address linked list.

[0009] Preferably, the instructions to be taken over in the instruction list are modified, specifically including: replacing the instructions to be taken over in the instruction chain with the corresponding jump instructions, the jump address of the jump instructions being the jump address of the user instructions; and inserting a no-operation instruction after the jump instructions.

[0010] Preferably, the jump address specifically includes: calculating the start address and end address of the jump address based on the start address of the module where the user instruction is located and the size of the storage space occupied by the user instruction.

[0011] Preferably, the instruction to be taken over in the instruction chain is replaced with the corresponding jump instruction, which specifically includes: generating the instruction node corresponding to the user instruction based on the user instruction information; and replacing the instruction node corresponding to the instruction to be taken over in the instruction list with the node corresponding to the user instruction.

[0012] Preferably, when there is a branch jump instruction in the instruction chain, and the jump position of the branch jump instruction is the instruction following the instruction to be taken over, the method further includes: modifying the jump address of all the branch jump instructions to the address of the instruction following the instruction to be taken over in the secondary jump table.

[0013] Preferably, executing instructions in the instruction chain includes: executing to the instruction node where the replaced instruction to be taken over is located according to the instruction chain; jumping to the instruction template corresponding to the user instruction according to the jump address in the replaced instruction node for execution; and after the instruction in the instruction template is executed, jumping to the next instruction node in the instruction chain.

[0014] Preferably, the jump to the instruction template corresponding to the user instruction for execution further includes: before the jump, saving the value of the register corresponding to the user instruction to memory; after execution, restoring the data saved to memory to the original memory.

[0015] Preferably, after executing the instruction chain to the instruction node where the replaced instruction to be taken over is located, the method further includes: determining whether the instruction node has been activated; if not, activating and executing the instruction node; if so, not activating the instruction node.

[0016] On the other hand, the present invention provides an apparatus for MIPS architecture assembly instruction takeover, specifically comprising at least one processor and a memory, wherein the at least one processor and the memory are connected via a data bus, the memory stores instructions executable by at least one processor, and the instructions, after being executed by the processor, are used to complete the MIPS architecture assembly instruction takeover method in the first aspect.

[0017] Compared with existing technologies, the beneficial effects of this invention are as follows: by replacing the actually executed instructions through instruction substitution and a two-level jump table, arbitrary user programs can be implanted into the existing MIPS instruction architecture to complete specified functions. This method can ensure the normal operation of the source program after the user program is implanted, while solving the problem of normal program jump logic after arbitrary instructions are taken over. [Attached Image Description]

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0019] Figure 1 A flowchart illustrating a method for handling assembly instructions in a MIPS architecture, as provided in this embodiment of the invention;

[0020] Figure 2 A flowchart illustrating another method for MIPS architecture assembly instruction takeover provided in this embodiment of the invention;

[0021] Figure 3 A flowchart illustrating another method for MIPS architecture assembly instruction takeover provided in this embodiment of the invention;

[0022] Figure 4 A flowchart illustrating another method for MIPS architecture assembly instruction takeover provided in this embodiment of the invention;

[0023] Figure 5 A flowchart illustrating another method for MIPS architecture assembly instruction takeover provided in this embodiment of the invention;

[0024] Figure 6 This is a schematic diagram of a device structure for MIPS architecture assembly instruction takeover provided in an embodiment of the present invention.

Detailed Implementation Methods

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] This invention is an architecture of a specific functional system. Therefore, the specific embodiments mainly describe the functional logic relationship of each structural module, and do not limit the specific software and hardware implementation methods.

[0027] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Example 1:

[0029] To meet this requirement, when the original program executes the instruction to be taken over, it needs to deviate from the original instruction's execution and instead perform the user-implemented specific function. To implant this user function, it's necessary to replace the specified assembly instructions in the function with jump instructions, redirecting the user to a user-specified address. Then, the program with the specific function is implanted at that address, thus completing the function replacement.

[0030] like Figure 1 As shown, the specific steps of the method for MIPS architecture assembly instruction takeover provided in this embodiment of the invention are as follows:

[0031] Step 101: Initialize the original instruction list and obtain the instructions to be taken over.

[0032] To replace the instruction that needs to be taken over, the instruction must first be located in the original program. In practice, to facilitate searching and subsequent instruction replacement and runtime management, the instructions in the original program can be organized into an instruction linked list. Each instruction node in the instruction linked list contains the instruction's source address, instruction length, the address of the instruction's second-level jump table, and the length of the second-level jump table address. After organizing the original instructions into an instruction list, the function instructions in the instruction list are parsed one by one to determine whether the current instruction is the one that needs to be taken over. If it is the instruction that needs to be taken over, it is modified and replaced according to step 103; if it is not the instruction that needs to be replaced, the next instruction is processed directly. Furthermore, if there is a function call in the original instructions, the corresponding instruction that needs to be replaced in the called function needs to be found and replaced based on the address of the called function. After traversing all instruction nodes in the instruction list, all instructions that need to be taken over in the original instructions can be obtained.

[0033] Step 102: Obtain the jump address of the user instruction based on the second-level jump table.

[0034] In the MIPS architecture, a set of assembly instructions that implements a specific function is stored using instruction templates. These templates, similar to function code, are placed in the code's text segment during compilation and are automatically loaded into memory for execution when the program jumps to the template. The address information in the instruction template uses general addresses; these general addresses need to be modified to specific addresses to actually perform the function of each instruction. Each instruction template is equivalent to an assembly function, passing specific parameters as needed during invocation. Instruction templates are stored in different modules, each module acting as a dynamic link library. For instruction takeover, the instructions to be taken over are redirected to the instruction template corresponding to the user instruction.

[0035] In this embodiment, instruction function redirection is achieved through a two-level jump table, thereby completing instruction replacement. By modifying the compilation and linking script, a named region, called a two-level jump table, is reserved within the text segment of each dynamic link library. Each two-level jump table stores the user instruction corresponding to the function or variable symbol name.

[0036] Furthermore, to facilitate the use of instruction addresses in the secondary jump table, this embodiment organizes all jump addresses in the secondary jump table into a secondary jump table address linked list. Each element in the secondary jump table address linked list represents an entry in the secondary jump table, that is, the address information corresponding to a user instruction template that needs to be jumped to. The starting address of the module where the secondary jump table is located is used as the starting address of the first instruction template in each secondary jump table; the ending address of the jump address is calculated based on the starting address of the module where the user instruction is located and the storage space occupied by the user instruction. For example, if the user instruction contains 48 assembly instructions, and since MIPS instructions are 32-bit 4-byte, each instruction template occupies a length of 192 bytes, the ending address of the jump address is the starting address of the module + 192. Since instruction templates of different entries in the module are stored consecutively, the ending address of the jump address of the previous instruction template is the starting address of the jump address of the next instruction template.

[0037] Based on the module name where the secondary jump table is located, the start address and end address of the jump address, the storage location of the user instruction can be determined, and the jump replacement of the user instruction can be completed.

[0038] like Figure 2 As shown, a two-level jump table address chain can be established through the following steps, and the jump address of the user instruction can be obtained through the two-level jump table address chain.

[0039] Step 201: Obtain the address information from all the second-level jump tables required by the current process.

[0040] To build a linked list of second-level jump table addresses, it's necessary to obtain the address information corresponding to all second-level jump tables used by the current process. First, traverse all symbols in the program, retrieving the address information corresponding to each symbol in the second-level jump table based on its name. The address information includes symbol address, size, the name of the module containing the second-level jump table, and the start and end addresses of the jumps. After obtaining the address information for each second-level jump table, it's necessary to organize this information into elements of the linked list. Each element records the module name, pre-defined area, start address, end address, available pre-defined area address, current element size, and the number of elements already used for each second-level jump table.

[0041] Step 202: Combine the information in the second-level jump table into a second-level jump table address linked list.

[0042] After obtaining the element corresponding to each second-level jump table, all elements can be combined into a linked list of second-level jump table addresses. In actual use, the structure of the linked list of second-level jump table addresses can contain three members: the number of second-level jump tables, the head pointer of the second-level jump table structure, and the tail pointer of the second-level jump table. After the structure is constructed and each element is initialized with zeros, the element corresponding to each second-level jump table obtained in step 201 can be added to the linked list.

[0043] Step 203: Obtain the address of the second-level jump table to be used based on the address chain of the second-level jump table.

[0044] After organizing the jump addresses corresponding to the second-level jump table into a linked list of second-level jump table addresses, by traversing and scanning the symbol names in the second-level jump table, all reserved addresses in the second-level jump table can be obtained, that is, the address where the user instruction used for replacement is located can be obtained.

[0045] Steps 201-203 complete the organization of the secondary jump table address chain, which facilitates the acquisition of user instruction addresses in subsequent steps.

[0046] Step 103: Modify the instructions to be taken over in the instruction list according to the jump address of the user instruction.

[0047] After finding the instruction to be taken over in the instruction chain, it can be done as follows: Figure 3 As shown, the instructions to be taken over in the instruction list are modified through the following steps.

[0048] Step 301: Replace the instruction to be taken over in the instruction chain with the corresponding jump instruction. The jump address of the jump instruction is the jump address of the user instruction.

[0049] In the method provided in this embodiment, the instruction to be taken over is changed into a jump instruction that jumps to the address of the user instruction by a jump instruction, thereby completing the instruction takeover and replacement. To implement the jump, the address information of the user instruction's secondary jump table needs to be obtained based on the instruction address and the module it resides in. Specifically, the jump instruction can use direct jump instructions such as the j instruction or jmp instruction, or conditional jump instructions such as jalr can be used to implement takeover only in certain scenarios, depending on actual needs. The jump address in the jump instruction is the jump instruction obtained in step 101.

[0050] When using an instruction list, the instruction node of the instruction to be taken over can be removed from the instruction list. Based on the user instruction information, a corresponding instruction node is generated for the user instruction. This instruction node is then inserted into the original position of the instruction to be taken over in the instruction list, replacing the corresponding instruction node in the instruction list with the node corresponding to the user instruction. Specifically, memory space is allocated for the instruction node of the jump instruction, and information such as the function name, instruction address, instruction length, address of the instruction's second-level jump table, and whether the instruction is active are copied and stored into the instruction node structure.

[0051] Furthermore, if the program logic still requires the execution of the instruction to be taken over, the instruction to be taken over can also be added to the instruction template of the user instruction; or, according to the execution order, the instruction to be taken over can be added to the second-level jump table of the user instruction. For example, if the instruction to be taken over is a write memory instruction, and the user needs to add a memory detection function before writing memory, the memory detection instruction and the write memory instruction can be placed in the instruction template of the user instruction for overall replacement; alternatively, the write memory instruction in the original instruction chain can be replaced with the memory detection instruction, and the write memory instruction can be copied to the corresponding entry in the second-level jump table where the memory detection instruction is located.

[0052] Step 302: Insert a no-operation instruction after the jump instruction.

[0053] Because the MIPS architecture CPU employs a 5-stage pipeline, branch delay slots are introduced for branch instructions to improve pipeline efficiency. This means that before executing a branch jump instruction, the instruction in the branch delay slot is executed first, followed by the branch jump instruction. Instruction takeover essentially replaces the instruction to be taken over with a jump statement, facilitating the integration of our functionality. In the MIPS architecture, to avoid altering the normal execution flow, a noop (no-op) instruction needs to be inserted at the position of the instruction following the one being taken over.

[0054] Through steps 301-302, the instructions that need to be taken over in the original instruction chain can be replaced with jump instructions pointing to the user instructions after takeover. When the execution reaches the position of the original instruction that needs to be taken over, it will automatically jump to the user instructions according to the normal execution flow, thus completing the instruction replacement.

[0055] Furthermore, in certain specific implementation scenarios, there may be one or more branch jump instructions in the original instruction chain, and the jump address of these branch jump instructions is the next instruction after the instruction to be taken over. In this embodiment, after inserting an empty statement according to step 302, the next jump instruction of the instruction to be jumped to in the original instruction chain becomes an empty instruction. If these branch jump instructions are not processed, an error of jumping to an empty instruction will occur. Therefore, it is also necessary to modify the jump address of all branch jump instructions to the address of the next instruction of the instruction to be taken over in the secondary jump table to ensure that the jump position of the original branch jump instructions is correct.

[0056] Step 104: Execute the instructions in the modified instruction list.

[0057] After replacing the instructions in the instruction chain, execution can be performed according to the instruction chain.

[0058] Specifically, such as Figure 4 As shown, the execution of instructions in the instruction chain can be completed through the following steps. The following process is consistent with the general instruction execution process under the MIPS architecture, so automatic instruction takeover can be achieved after the instruction chain replacement is completed.

[0059] Step 401: Execute the instruction node containing the replaced instruction to be taken over according to the instruction chain.

[0060] For instructions in the instruction chain that do not require takeover, the execution follows the normal procedure, executing the instructions in the chain until the original takeover location is reached, which is the location of the replaced takeover instruction.

[0061] Step 402: Based on the jump address in the replaced instruction node, jump to the instruction template corresponding to the user instruction for execution.

[0062] When execution reaches the location of the replaced instruction to be taken over, since the instruction to be taken over has been replaced with a jump instruction that jumps to the location of the user instruction, the jump instruction is executed. Based on the jump address in the jump instruction, a jump is performed, which, according to the secondary jump table, leads to the instruction template corresponding to the user instruction. The user then completes the required function according to the instruction template.

[0063] Step 403: After the instruction in the instruction template is executed, jump to the next instruction node in the instruction chain.

[0064] In this embodiment, the parts of the original instruction chain that do not need to be replaced are retained. Only the instructions that need to be taken over at the nodes containing the user instructions are replaced with the corresponding jump instructions. After jumping to the user instruction according to the instruction chain and executing it, the execution flow can be followed normally, jumping back to the instruction list and continuing execution. This achieves the effect of taking over and replacing only a part of the functional modules without affecting the original program flow.

[0065] Through steps 401-403, based on the replaced instruction list, runtime instruction takeover is completed. User instructions are automatically used to replace the instructions to be taken over without affecting the original program flow, thus completing instruction takeover.

[0066] Furthermore, in order to ensure that the data in each register is correct during program execution, it is necessary to save the context before running user instructions by saving the values ​​of the registers corresponding to the user instructions to memory; and after running user instructions, it is necessary to restore the context by restoring the data saved to memory to the original memory.

[0067] Specifically, such as Figure 5 As shown, steps 401-403 need to be expanded into the following steps.

[0068] Step 501: Execute the instruction node containing the replaced instruction to be taken over according to the instruction chain.

[0069] Step 502: Save the register values ​​related to the user instruction into the data memory.

[0070] Step 503: Based on the jump address in the replaced instruction node, jump to the instruction template corresponding to the user instruction for execution;

[0071] Step 504: After the instruction in the instruction template is executed, the register value saved in the data memory is retrieved and restored to the relevant register.

[0072] Step 505: Jump to the next instruction node in the instruction chain.

[0073] Through steps 501-505, the execution state of the program was saved and restored during takeover, thus avoiding the impact of jumps during takeover on the original program flow.

[0074] Furthermore, in this embodiment, instruction replacement and instruction execution are performed separately. The corresponding user instruction can be replaced before each execution, or it can be replaced once and executed multiple times. Steps 101-103 only preprocess and replace the instruction chain; no specific instruction is executed. Execution only occurs in step 104 based on the modified instruction chain. After replacing the instruction node to be taken over in the original instruction chain, an activation flag can be set on that instruction node. At this point, the replaced instruction node has not yet been activated for execution, so the flag's activation state is negative. In step 401 or 501, after executing the instruction chain to the location of the replaced instruction to be taken over, it is determined whether the instruction has been activated. If the flag's activation state is negative, it means the instruction to be replaced has been replaced but not activated for execution; the instruction is then activated and executed. If it is positive, it indicates that the replaced instruction has already been executed; the instruction is not activated.

[0075] The method for intercepting assembly instructions in the MIPS architecture provided in this embodiment creates a two-level jump table, parses the instructions that need to be replaced in the original instruction chain, performs preprocessing and user instruction replacement, so that when the original program runs to the instruction that needs to be intercepted, it can automatically jump to the two-level jump table to execute the user-implemented function. This method can achieve the interception and jump of arbitrary instructions, and can ensure the normal execution and logical jump of the program after interception, providing a new approach to instruction interception for embedded systems based on the MIPS architecture.

[0076] Example 2:

[0077] Based on the MIPS architecture assembly instruction takeover method provided in Embodiment 1, this embodiment provides a practical application example to more clearly illustrate the technical solution. In MIPS systems, the number of bytes varies across different CPU architectures. For simplicity, this embodiment uses a common 32-bit MIPS CPU architecture as an example. This embodiment only describes the specific functional processing procedure of one function; if there is a need to replace similar logical judgment instructions, a similar method can be used.

[0078] In a specific scenario, the source code statements of the original functional module are as follows. The user needs to add a memory check statement before the write memory statements.

[0079]

[0080]

[0081] The memory write statements that need to be replaced in this function are:

[0082] int a

[10] ;

[0083] memset(a,0,sizeof(a));

[0084] a[0] = 1;

[0085] The function of this group of memory write statements is to first allocate an integer array a with 10 members, then clear the memory of array a, and then assign the value 1 to the first member a[0].

[0086] According to step 101, initialize the original instruction list. The original instruction list of the assembly instructions corresponding to this group of statements is as follows. For the sake of simplicity, only the statements related to this scheme are listed below, and each statement corresponds to an instruction node.

[0087] Item 1: 0x0043d80c addiu sp,sp,-72

[0088] Item 2: 0x0043d810 sw ra,68(sp)

[0089] Item 3: 0x0043d814 sw s8,64(sp)

[0090] Item 4: 0x0043d818 move s8,sp

[0091] Item 5: 0x0043d81c lui gp,0x62

[0092] Item 6: 0x0043d820 addiu gp,gp,21088

[0093] Item 7: 0x0043d824 sw gp,16(sp)

[0094] Item 8: 0x0043d828 addiu v0,s8,24

[0095] Article 9: 0x0043d82c move a0,v0

[0096] Item 10: 0x0043d830 move a1,zero

[0097] Item 11: 0x0043d834 li a2,40

[0098] Item 12: 0x0043d838 lw v0,-28900(gp)

[0099] Item 13: 0x0043d83c move t9,v0

[0100] Item 14: 0x0043d840 jalr t9

[0101] Article 15: 0x0043d844 move at,at

[0102] Item 16: 0x0043d848 lw gp,16(s8)

[0103] Item 17: 0x0043d84c li v0,1

[0104] Item 18: 0x0043d850 sw v0,24(s8)

[0105] Item 19: 0x0043d854 lui v0,0x5e

[0106] Item 20: 0x0043d858 addiu v1,v0,26476

[0107] Analyzing the instructions in the original instruction chain, we can see that the second and third instructions correspond to the statement `int a

[10] `; the seventh and eighth instructions correspond to the statement `memset(a,0,sizeof(a))`; and the 18th and 19th instructions correspond to the statement `a[0]=1`. In this embodiment, the memory detection statement and the memory write statement are stored in the same instruction template. When modifying or replacing, the above instructions are directly replaced with jump instructions that jump to the corresponding instruction template.

[0108] According to step 102, based on the actual compilation situation, a second-level jump table is established for this embodiment. After establishing the second-level jump table, the second-level jump table name of the user instruction corresponding to the write memory instruction to be replaced is obtained as "MemcheckJumpTableEntryBegin_0". The jump start address of the first instruction template is MemcheckJumpTableEntryBegin_0. The start addresses of subsequent instruction templates are calculated according to the end address of the previous instruction template. For example, the instruction 2 has 48 assembly instructions in the instruction template of the second-level jump table. Since MIPS instructions are 4 bytes, each instruction template occupies a length of 192 bytes. Therefore, the jump address corresponding to the 7th instruction is 0+192, and the jump address of the 18th instruction is calculated in the same way.

[0109] After calculating the jump address of each statement, the original instruction list is modified according to step 103. The node content corresponding to each instruction to be replaced in the original instruction list is replaced with the corresponding jump statement. The assembly instruction list after replacement is as follows.

[0110] Item 1: 0x0043d80c addiu sp,sp,-72

[0111] Item 2: 0x0043d810 j 0x6613e0<MemcheckJumpTableEntryBegin_0>

[0112] Item 3: 0x0043d814 nop

[0113] Item 4: 0x0043d818 move s8,sp

[0114] Item 5: 0x0043d81c lui gp,0x62

[0115] Item 6: 0x0043d820 addiu gp,gp,21088

[0116] Item 7: 0x0043d824 j 0x6614a0<MemcheckJumpTableEnt ryBegin_0+192>

[0117] Item 8: 0x0043d828 nop

[0118] Article 9: 0x0043d82c move a0,v0

[0119] Item 10: 0x0043d830 move a1,zero

[0120] Item 11: 0x0043d834 li a2,40

[0121] Item 12: 0x0043d838 lw v0,-28900(gp)

[0122] Item 13: 0x0043d83c move t9,v0

[0123] Item 14: 0x0043d840 jalr t9

[0124] Article 15: 0x0043d844 move at,at

[0125] Item 16: 0x0043d848 lw gp,16(s8)

[0126] Item 17: 0x0043d84c li v0,1

[0127] Item 18: 0x0043d850 j 0x661560<MemcheckJumpTableEnt ryBegin_0+384>

[0128] Item 19: 0x0043d854 nop

[0129] Item 20: 0x0043d858 addiu v1,v0,26476

[0130] In the replaced instruction list above, instructions 2 and 3 are replaced with jump statements to the corresponding jump addresses in the second-level jump table MemcheckJumpTableEntryBegin_0 and no-op instructions (nop); instructions 7 and 8, as well as instructions 18 and 19, have the same effect. By executing the replaced instruction list above, the original write memory instruction can be modified into a memory check + write memory instruction in the instruction template corresponding to the user instruction, without affecting the execution of other parts of the original instruction list.

[0131] Furthermore, in practical scenarios, if there are branch jump statements that jump to the 3rd, 8th, and 19th statements in the original instruction chain, it is also necessary to change the jump position of the corresponding branch jump statements to avoid jumping to empty statements and ensure the logical correctness of the source program.

[0132] Furthermore, as in steps 501-505, the instruction template of the secondary jump table MemcheckJumpTableEntryBegin_0 also includes instructions for saving the data context and restoring the context.

[0133] Taking the third memory assignment statement a[0] = 1 as an example, after adding save and restore context, the instruction chain list of write memory instructions and preprocessing analysis and replacement instructions is as follows through disassembling the second-level jump table MemcheckJumpTableEntryBegin_0.

[0134] Item 1: 0x00661560 addiu sp,sp,-128

[0135] Item 2: 0x00661564 sw ra,16(sp)

[0136] Item 3: 0x00661568 sw s8,20(sp)

[0137] Item 4: 0x0066156c sw a0,24(sp)

[0138] Item 5: 0x00661570 sw a1,28(sp)

[0139] Item 6: 0x00661574 sw a2,32(sp)

[0140] Item 7: 0x00661578 sw a3,36(sp)

[0141] Item 8: 0x0066157c sw v0,40(sp)

[0142] Item 9: 0x00661580 sw v1,44(sp)

[0143] Item 10: 0x00661584 sw gp,48(sp)

[0144] Article 11: 0x00661588 move a0,s8

[0145] Item 12: 0x0066158c li a1,0

[0146] Article 13: 0x00661590 li a2,24

[0147] Item 14: 0x00661594 lui v0,0x5c

[0148] Item 15: 0x00661598 addi v0,v0,-5940

[0149] Item 16: 0x0066159c jalr v0

[0150] Article 17: 0x006615a0 move at,at

[0151] Item 18: 0x006615a4 lw ra,16(sp)

[0152] Item 19: 0x006615a8 lw s8,20(sp)

[0153] Item 20: 0x006615ac lw a0,24(sp)

[0154] Item 21: 0x006615b0 lw a1,28(sp)

[0155] Item 22: 0x006615b4 lw a2,32(sp)

[0156] Item 23: 0x006615b8 lw a3,36(sp)

[0157] Item 24: 0x006615bc lw v0,40(sp)

[0158] Item 25: 0x006615c0 lw v1,44(sp)

[0159] Item 26: 0x006615c4 lw gp,48(sp)

[0160] Item 27: 0x006615c8 addiu sp,sp,128

[0161] Item 28: 0x006615cc sw v0,24(s8)

[0162] Item 29: 0x006615d0 lui v0,0x5e

[0163] Item 30: 0x006615d4 addiu v1,v0,26476

[0164] Item 31: 0x006615d8 j 0x43d858<asontest+76>

[0165] The instruction statement 1 obtains the instruction template after the jump; the instructions 2 to 15 correspond to step 502, saving the runtime environment register value; the instruction statement 16 corresponds to step 503, jumping to the user-replaced instruction for execution, first executing the user-added memory detection statement; the instructions 17 to 27 correspond to step 504, retrieving and restoring the register value; the instructions 28 and 29 correspond to the step of executing the memory assignment operation a[0]=1. Since the instructions 28 and 29 in the second-level jump table are the original instructions 18 and 19 before the instruction replacement, that is, the memory assignment statements to be replaced. According to the above instruction template, after copying the original memory copy statement to be replaced into the second-level jump table, after executing the user-implanted memory detection function program, the actual memory assignment operation can continue to be executed. Therefore, whether it is direct function replacement or function addition, it can be ensured that the implanted jump and processing functions do not affect the normal operation of the original program.

[0166] The 30th instruction jumps to the next instruction in the original instruction list, executing the subsequent `printf` statement. This corresponds to step 505. After executing the specific function of the user instruction, the process returns to the original instruction list to continue executing its subsequent functions.

[0167] As can be seen from the examples in this method, the method for intercepting MIPS architecture assembly instructions provided in Example 1 can ensure the normal operation of the program while intercepting arbitrary instructions and implanting user functions. This solves the current problem of being unable to intercept MIPS architecture instructions.

[0168] Example 3:

[0169] Based on the MIPS architecture assembly instruction takeover method provided in Embodiments 1 and 2 above, the present invention also provides an apparatus for implementing the above method, such as... Figure 6 The diagram shown is a schematic representation of the device architecture according to an embodiment of the present invention. The device in this embodiment, which utilizes MIPS architecture assembly instructions, includes one or more processors 11 and a memory 12. Figure 6 Take a processor 11 as an example.

[0170] Processor 11 and memory 12 can be connected via a bus or other means. Figure 6 Taking the example of a connection between China and Israel via a bus.

[0171] The memory 12 serves as a non-volatile computer-readable storage medium for the MIPS architecture assembly instruction takeover method. It can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the MIPS architecture assembly instruction takeover method in Embodiments 1 and 2. The processor 11 executes various functional applications and data processing of the MIPS architecture assembly instruction takeover device by running the non-volatile software programs, instructions, and modules stored in the memory 12, thereby implementing the MIPS architecture assembly instruction takeover method in Embodiments 1 and 2.

[0172] Memory 12 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 12 may optionally include memory remotely located relative to processor 11, which can be connected to processor 11 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0173] The program instructions / modules are stored in memory 12. When executed by one or more processors 11, they perform the MIPS architecture assembly instruction takeover method described in Embodiments 1 and 2 above, for example, executing the above-described... Figures 1-5 The steps shown.

[0174] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0175] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for handling assembly instructions in a MIPS architecture, characterized in that: Initialize the original instruction list and obtain the instructions to be taken over; Obtain the jump address of the user instruction based on the second-level jump table; Based on the jump address of the user instruction, modify the instructions to be taken over in the instruction list; the modification of the instructions to be taken over in the instruction list specifically includes: replacing the instructions to be taken over in the instruction chain with the corresponding jump instructions, the jump address of the jump instructions being the jump address of the user instruction; inserting a no-operation instruction after the jump instructions; The step of replacing the instruction to be taken over in the instruction chain list with the corresponding jump instruction specifically includes: generating an instruction node corresponding to the user instruction based on the user instruction information; and replacing the instruction node corresponding to the instruction to be taken over in the instruction list with the node corresponding to the user instruction. Execute the instructions in the modified instruction list; The execution of instructions in the instruction chain specifically includes: executing the instruction node where the replaced instruction to be taken over is located according to the instruction chain; jumping to the instruction template corresponding to the user instruction according to the jump address in the replaced instruction node for execution; and after the instruction in the instruction template is executed, jumping to the next instruction node in the instruction chain. After executing the instruction node containing the replaced instruction according to the instruction chain, the process further includes: determining whether the instruction node has been activated; if not, activating and executing the instruction node; if so, not activating the instruction node.

2. The method for handling MIPS architecture assembly instructions according to claim 1, characterized in that, The step of obtaining the jump address for the user instruction specifically includes: Obtain the address information from all second-level jump tables required by the current process. The address information must include at least one or more of the following: the corresponding symbol information, the module in which it is located, and the jump address. Combine the address information into a two-level jump table address linked list; Obtain the jump address of the user instruction based on the address chain of the second-level jump table.

3. The method for handling MIPS architecture assembly instructions according to claim 1, characterized in that, The jump address specifically includes: Calculate the start and end addresses of the jump address based on the starting address of the module where the user instruction is located and the size of the storage space occupied by the user instruction.

4. The method for handling MIPS architecture assembly instructions according to claim 1, characterized in that, When a branch jump instruction exists in the instruction chain, and the jump position of the branch jump instruction is the instruction following the instruction to be taken over, it also includes: Modify the jump address of all the aforementioned branch jump instructions to the address of the next instruction to be taken over in the second-level jump table.

5. The method for handling MIPS architecture assembly instructions according to claim 1, characterized in that, The step of jumping to the instruction template corresponding to the user instruction for execution also includes: Before performing a jump, the value of the register corresponding to the user instruction is saved to memory; After execution, the data saved in the memory will be restored to the original memory.

6. A device for taking over assembly instructions in a MIPS architecture, characterized in that: The method includes at least one processor and a memory, which are connected via a data bus. The memory stores instructions that can be executed by the at least one processor, and the instructions, when executed by the processor, are used to perform the method of MIPS architecture assembly instruction takeover as described in any one of claims 1-5.

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