Memory testing method, device, equipment and storage medium

Abstract

The present disclosure provides a memory testing method, device, equipment and storage medium, which relate to the field of semiconductor technology. The method includes: obtaining the CPU accessible space of the memory to be tested; obtaining the GPU accessible space of the memory to be tested; driving the CPU to run a test program based on the CPU accessible space to access the memory to be tested through the memory to be tested bus, wherein when the CPU runs the test program, the GPU controls the GPU to access the memory to be tested through the memory to be tested bus based on the GPU accessible space. The method implements a stress test on the memory with a high access load, and enhances the effect of the memory test.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory testing method, device, equipment and readable storage medium. Background Art

[0002] As semiconductor process size continues to shrink, the scale of integrated circuit design is getting larger and larger, and highly complex integrated circuit products are facing increasingly severe challenges such as high reliability and high quality. Dynamic Random Access Memory (DRAM) is an internal memory that directly exchanges data with the Central Processing Unit (CPU). It can be read and written at any time. For example, Low Power Double Data Rate SDRAM (LPDDR) is often used in System-on-a-chip (SoC) in some handheld devices such as mobile phones and tablets. Therefore, system-level stress testing of LPDDR and other memories is very important.

[0003] In the related art, the access test of the memory is performed by running the test software on the operating system, but the load degree of the memory access is low during the test, and the effect of the stress test is poor.

[0004] As described above, how to improve the load of memory stress testing has become an urgent problem to be solved.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0006] The purpose of the present disclosure is to provide a memory test, device, equipment and readable storage medium, which can improve the load of memory stress testing at least to a certain extent.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a memory testing method is provided, comprising: obtaining a central processing unit accessible space of a memory to be tested; obtaining a graphics processor accessible space of the memory to be tested; driving the central processing unit to run a test program based on the central processing unit accessible space to access the memory to be tested through a memory to be tested bus, wherein when the central processing unit runs the test program, the graphics processor is controlled to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space.

[0009] According to an embodiment of the present disclosure, when the central processing unit runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space includes: the central processing unit and the graphics processor serially access the memory to be tested through the memory to be tested bus.

[0010] According to an embodiment of the present disclosure, the memory under test bus is an advanced extensible interface protocol bus including a predetermined transmission channel; the central processing unit and the graphics processor serially access the memory under test through the memory under test bus, including: the central processing unit and the graphics processor serially access the memory under test through the predetermined transmission channel according to the test program.

[0011] According to an embodiment of the present disclosure, when the central processing unit runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space includes: the central processing unit controlling the graphics processor to access the memory to be tested in a predetermined access manner according to the test program based on an open programming language.

[0012] According to one embodiment of the present disclosure, when the central processing unit runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space includes: the central processing unit controlling the graphics processor to access the memory to be tested in a predetermined access manner according to the test program through an open graphics program interface.

[0013] According to one embodiment of the present disclosure, the memory to be tested is a low-power internal memory; accessing the memory to be tested through the memory to be tested bus includes: the central processing unit accessing the low-power internal memory via the memory to be tested bus via a memory controller; when the central processing unit runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space, includes: the graphics processor accessing the low-power internal memory via the memory controller through the memory to be tested bus.

[0014] According to another aspect of the present disclosure, a memory testing system is provided, comprising a central processing unit and a graphics processing unit, wherein: the central processing unit is used to run a test program based on the allocated central processing unit accessible capacity to access a memory to be tested, wherein when the central processing unit runs the test program, the graphics processing unit controls the graphics processing unit to access the memory to be tested based on the allocated graphics processing unit accessible capacity; and the graphics processing unit is used to access the memory to be tested based on the graphics processing unit accessible capacity.

[0015] According to another aspect of the present disclosure, a memory testing device is provided, comprising: a test preparation module, used to obtain a central processing unit accessible space of a memory to be tested; to obtain a graphics processor accessible space of the memory to be tested; and a test running module, used to drive the central processing unit to run a test program based on the central processing unit accessible space, so as to access the memory to be tested through a memory to be tested bus, wherein when the central processing unit runs the test program, the graphics processor is controlled to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space.

[0016] According to another aspect of the present disclosure, a device is provided, comprising: a memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor implements any of the above methods when executing the executable instructions.

[0017] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, and when the executable instructions are executed by a processor, any of the above methods is implemented.

[0018] The memory testing method provided by the embodiment of the present disclosure drives the central processing unit to run a test program based on the central processing unit accessible space to access the memory to be tested through the memory to be tested bus. When the central processing unit runs the test program, the graphics processor is controlled to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space, thereby achieving a stress test with a high access load on the memory and enhancing the effect of the memory test.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0021] Figure 1 A schematic diagram showing a system structure in an embodiment of the present disclosure.

[0022] Figure 2 A flow chart of a memory testing method in an embodiment of the present disclosure is shown.

[0023] Figure 3 A flow chart of another memory testing method in an embodiment of the present disclosure is shown.

[0024] Figure 4 according to Figures 1 to 3 A memory test flow chart is shown.

[0025] Figure 5 A diagram showing an architecture of a memory test implementation platform according to an exemplary embodiment.

[0026] Figure 6 The invention is a block diagram showing a memory testing device according to an exemplary embodiment.

[0027] Figure 7 A schematic structural diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The accompanying drawings are only schematic illustrations of the disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0029] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, devices, steps, etc. may be adopted. In other cases, well-known structures, methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0030] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The symbol " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0031] In this disclosure, unless otherwise clearly specified and limited, terms such as "connection" should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0032] In the related art, the test of LPDDR in the system segment can be divided into three levels. The first level is the memory built-in self test (Mbist) module included in the memory controller on the SoC. Mbist can perform some state-level tests on the memory. The test of DRAM is solidified by the SoC itself and has poor configurability. The second level is the universal boot loader (Uboot) level. The test software at this level has good scalability and can test the entire memory array space. However, such a test generally requires the original support of the SoC and the development degree of the SoC manufacturer. Moreover, since it runs on the SoC, its processing speed is limited by the size of the static random access memory (SRAM) of the SoC. The third level is the test of the Android / Linux system base class. The test at this level is closer to the user's applicable method. The scalability and diversity of the test software are very good, but it cannot cover the entire memory space because the Android / Linux system itself needs to occupy a large part of the memory space.

[0033] There are two types of stress tests for Android / Linux bases: one is to test at the Android native layer, and the other is to use image software such as 3Dmark. Both software testing methods have certain defects. The input and output (IO) access of the native layer test cannot be fully loaded, and the 3Dmark software itself is used to test the graphics processing unit (GPU) instead of the memory, so the relevant memory test algorithm is not implemented, and the memory IO access cannot be fully loaded.

[0034] Therefore, the present disclosure provides a memory testing method, which drives the central processing unit to run a test program based on the central processing unit accessible space to access the memory to be tested through the memory bus to be tested, and when the central processing unit runs the test program, controls the graphics processor to access the memory to be tested through the memory bus to be tested based on the graphics processor accessible space, thereby achieving a stress test with a high access load on the memory and enhancing the effect of the memory test.

[0035] Figure 1 An exemplary system architecture 10 to which the memory testing method or memory testing apparatus of the present disclosure may be applied is shown.

[0036] like Figure 1 As shown, the system architecture 10 may include a central processing unit (CPU) 102 and a graphics processing unit (GPU) 104, and may also include a memory bus 106 and a memory controller 108. The various parts of the system architecture 10 are described below.

[0037] The central processing unit 102 can be used to run a test program based on the allocated central processing unit accessible capacity to access the memory to be tested, wherein when the central processing unit runs the test program, the graphics processing unit is controlled to access the memory to be tested based on the allocated graphics processing unit accessible capacity. The memory (such as memory) testing method performed by the CPU is a test performed by directly accessing the memory, and the entire test program can be directly run on the CPU. The CPU can operate the GPU through a universal interface of an open graphics program (Open Graphics Library, OpenGL) or an open programming language (Open Computing Language, OpenCL), and the test code run by the CPU uses this universal interface to control the GPU to access the memory, and converts the CPU's memory test pattern (pattern) into the GPU's image processing logic, so that the GPU's test pattern is consistent with the CPU.

[0038] In some embodiments, for example, the CPU test items can be divided into three aspects, the first aspect is the array test, the second aspect is the IO test, and the third aspect is the state switching test. The array test is mainly to see if there are some hardware errors (hard fail) in the array, such as detecting whether a byte jump (bitflip) occurs, etc. The IO test can be divided into two types. The first is the stress test of the command mode (Command line), such as detecting whether input and output address jumps occur, etc.; the second is the stress test of the data bus mode (DQ bus line), such as detecting whether a data transmission jump occurs, etc. The DQ bus line test is the main stress test item. The state switching test can be divided into two test items, the first is the switch wait (suspend) test, and the second is the restart (reboot) test.

[0039] The graphics processor 104 can be used to access the memory to be tested based on the accessible capacity of the graphics processor. The GPU memory test method is an indirect test method. The GPU itself will not directly run the test code. The test code is run on the CPU. Through the CPU's operation, the GPU is given instructions for image processing, and the GPU will access the memory to perform related operations.

[0040] The memory bus 106, the central processing unit 102 accesses the low-power internal memory through the memory bus 106 to be tested via the memory controller; the graphics processing unit 104 accesses the low-power internal memory through the memory bus 106 to be tested via the memory controller. Whether the GPU or the CPU accesses the memory alone, there is a problem of bus allocation, that is, a part will be reserved for the other party, and the memory bus 106 cannot be fully occupied. The joint testing method of GPU and CPU can maximize the pressure on the memory test.

[0041] The memory controller 108 may be, for example, a memory controller, which is used for data exchange between the CPU and / or GPU and the memory to be tested, and can be used to obtain the maximum memory capacity, memory type and speed, data width, etc. of the memory controlled by it. A universal memory controller may be used for DDR memories of different generations and models. For example, when the memory to be tested is a low power internal memory (LPDDR), an enhanced universal DDR memory controller may be used.

[0042] Figure 2 FIG. 1 is a flow chart of a memory testing method according to an exemplary embodiment. Figure 2 The method shown may be applied to the system 10 described above, for example.

[0043] refer to Figure 2, the method 20 provided in the embodiment of the present disclosure may include the following steps.

[0044] In step S202, the CPU-accessible space of the memory to be tested is obtained. The memory may include internal memory and external memory. The internal memory may include registers, cache memory and main memory (usually referred to as memory), and the external memory may include hard disk, floppy disk, CD-ROM, etc. The internal memory has a small capacity and a fast speed, and is usually used to temporarily store the data and programs currently being executed; the external memory has a large capacity and a slow speed, and is usually used to store data and programs for a long time or permanently. The test method in this application can be used for various memories, and is not limited here.

[0045] In step S204, the GPU-accessible space of the memory to be tested is obtained.

[0046] In some embodiments, for example, when the memory to be tested is a memory, before running the test program, memory information such as the address, data volume, rate, etc. that can be passed can be obtained, and memory can be allocated to the CPU and GPU respectively, and the capacity and address of the memory to be tested that can be accessed by the CPU and GPU can be set respectively. The CPU accessible capacity can be obtained according to the capacity of the memory to be tested, and the GPU accessible capacity can be obtained according to the capacity of the memory to be tested, and the corresponding memory addresses can be allocated respectively.

[0047] In step S206, the central processor is driven to run the test program based on the central processor accessible space to access the memory to be tested through the memory to be tested bus, wherein the central processor controls the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space when running the test program. The address access mode of the CPU can be converted into the large block address access mode of the GPU DMA (Direct Memory Access) mapping through the conversion interface to achieve the conversion of the test logic.

[0048] In some embodiments, for example, the central processing unit controls the graphics processing unit to access the memory to be tested in a predetermined access manner according to the test program based on an open programming language. The CPU can control the GPU to access the memory to be tested in a predetermined access manner according to the test program based on OpenCL. OpenCL is a working standard for writing programs on a heterogeneous parallel computing platform, which can map heterogeneous computing to computing devices such as CPU, GPU, FPGA (Field Programmable Gate Array). OpenCL provides an abstract model of the underlying hardware structure and can provide a general development application interface. General computing programs running on GPUs can be written through OpenCL without mapping their algorithms to application program interfaces for 3D graphics such as OpenGL or DirectX.

[0049] In other embodiments, for example, the CPU can control the GPU through the OpenGL interface to access the memory to be tested in a predetermined access mode according to the test program. OpenGL is a graphics application programming interface, including a software library that can access image hardware devices such as GPUs, etc., and the OpenGL interface can be implemented completely in software on a variety of different graphics hardware systems. GPU hardware developers need to provide implementations that meet the OpenGL specification. These implementations are usually called "drivers" and are used to translate the application interface commands defined by OpenGL into GPU instructions.

[0050] According to the method provided in the embodiment of the present disclosure, by using the CPU and GPU to access the memory simultaneously for stress testing, the bus of the memory to be tested is occupied as fully as possible, thereby achieving a stress test with a high access load on the memory and enhancing the effect of the memory test.

[0051] Figure 3 FIG. 1 is a flow chart showing another memory testing method according to an exemplary embodiment. Figure 3 The method shown may be applied to the system 10 described above, for example.

[0052] refer to Figure 3 , the method 30 provided in the embodiment of the present disclosure may include the following steps.

[0053] In step S302, the CPU-accessible space of the memory to be tested is obtained.

[0054] In step S304, the GPU-accessible space of the memory to be tested is obtained.

[0055] Some specific implementations of steps S302 and S304 may refer to steps S202 and S204 and will not be described in detail here.

[0056] In step S306, the central processor is driven to run the test program based on the central processor accessible space to access the memory to be tested through the memory to be tested bus, wherein when the central processor runs the test program, the graphics processor is controlled to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space, and the central processor and the graphics processor serially access the memory to be tested through the memory to be tested bus. The memory to be tested bus may be an advanced extensible interface protocol bus including a predetermined transmission channel, and the central processor and the graphics processor serially access the memory to be tested through the predetermined transmission channel according to the test program.

[0057] In some embodiments, for example, the Advanced eXtensible Interface (AXI) bus includes five independent transmission channels, namely, a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel. When the CPU and GPU access memories such as LPDDR through the AXI bus, they access them in a serial manner, that is, they transmit them in sequence on a transmission channel. When the memory chip is configured with firmware, a portion may be reserved for each of the CPU and GPU, that is, if the memory is accessed for testing by the CPU or GPU respectively, a portion of the bus will remain unoccupied. By having the CPU and GPU simultaneously read and write to their respective memory spaces to access the memory at the same time, the AXI bus clock can be fully occupied to maximize the IO test of the memory.

[0058] According to the method provided by the embodiment of the present disclosure, by using the CPU and GPU to access the memory simultaneously for stress testing, the bus of the memory to be tested is occupied as much as possible, thereby maximizing the memory stress test and enhancing the effect of the memory test.

[0059] Figure 4 is based on Figures 1 to 3 A memory test flow chart is shown in FIG. Figure 4 As shown, after the process starts (S402), the relevant information of the memory is first obtained (S404), and then memory space is allocated to the CPU according to the memory information (S406), and memory space is allocated to the GPU (S408); after the memory allocation is completed, the joint test of the CPU and GPU is triggered (S410), and then the test result is checked (S412). After the test result indicates that the test is completed, the next memory test is performed (S414), and the process returns to step S402.

[0060] Figure 5 FIG. 1 is a diagram showing an architecture of a memory test implementation platform according to an exemplary embodiment. Figure 5As shown, taking Android base as an example, the Android application (Application, APP) can be used to call the driver of the native layer to implement memory testing. . The overall implementation is divided into three parts. The first part is the main control application 502 of the Android application layer, which is the overall control place of the entire test. The second part is to realize the conversion of the GPU test program. The GPU test conversion 508 converts the CPU test mode into the GPU operation process using the OpenCL interface 510. The third part is the CPU test engine 506 running the CPU's own test program. Since the second and third parts are both in the native layer of Android, both parts need external interfaces to be given to the main control of the first part to call. The main control application 502 controls the second and third parts to perform related operations through the relevant application interface. The native layer can also include a configuration file 504, a recording engine 512, etc. Due to the need to retain debugging and test results, the test needs to save the test record (log), and the log can be retained in the Android / data file through the recording engine 512.

[0061] Figure 5 The implementation in this requires Android root user (root) permissions to be implemented and developer mode to be turned on.

[0062] like Figure 5 As shown, taking Linux base as an example, you can directly use Linux APP to access the virtual address space, use the page lock (page lock) method of the Linux page mapping 516 of the kernel layer to test, or use APP to call the Linux underlying driver (kernel mode drive) 514 of the kernel layer to complete the memory test.

[0063] Figure 6 FIG. 1 is a block diagram of a memory testing device according to an exemplary embodiment. Figure 6 The device shown can be applied to the system 10 described above, for example.

[0064] refer to Figure 6 , the device 60 provided by the embodiment of the present disclosure may include a test preparation module 602 and a test running module 604 .

[0065] The test preparation module 602 may be used to obtain the CPU-accessible space of the memory to be tested; and obtain the GPU-accessible space of the memory to be tested.

[0066] The test running module 604 can be used to drive the central processor to run a test program based on the central processor accessible space to access the memory to be tested through the memory to be tested bus, wherein when the central processor runs the test program, it controls the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space.

[0067] The test running module 604 can also be used to drive the CPU and the GPU to serially access the memory under test through the memory under test bus. The memory under test bus is an advanced extensible interface protocol bus including a predetermined transmission channel.

[0068] The test running module 604 may also be used to drive the CPU and the GPU to serially access the memory to be tested through a predetermined transmission channel according to the test program.

[0069] The test running module 604 may also be used to drive the CPU to control the GPU to access the memory to be tested in a predetermined access manner according to the test program based on an open programming language.

[0070] The test running module 604 can also be used for the central processor to control the graphics processor through the open graphics program interface to access the memory to be tested in a predetermined access mode according to the test program.

[0071] The memory to be tested is a low-power internal memory.

[0072] The test running module 604 can also be used to drive the CPU to access the low-power internal memory through the memory bus to be tested via the memory controller; when the CPU runs the test program, it controls the GPU to access the low-power internal memory through the memory bus to be tested via the memory controller.

[0073] The specific implementation of each module in the device provided by the embodiment of the present disclosure can refer to the content of the above method, which will not be repeated here.

[0074] Figure 7 FIG. 1 is a schematic diagram showing the structure of an electronic device in an embodiment of the present disclosure. It should be noted that: Figure 7 The device shown is only an example of a computer system, which should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0075] like Figure 7As shown, the device 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 702 or the program loaded from the storage part 708 to the random access memory (RAM) 703, such as an executable test program to test the connected LPDDR. A graphics processing unit (GPU) 712 may also be included, and the CPU 701 may control the GPU to test the connected memory. In the RAM 703, various programs and data required for the operation of the device 700 are also stored. The CPU 701, the ROM 702, and the RAM 703 are connected to each other through the bus 704. The input / output (I / O) interface 705 is also connected to the bus 704. The CPU 701, the ROM 702, the RAM 703, the I / O 705, the GPU 712, etc. can be integrated on the Soc as needed.

[0076] The following components are connected to the I / O interface 705: an input section 706 including a keyboard, a mouse, etc.; an output section 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, a modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 710 as needed, so that a computer program read therefrom is installed into the storage section 708 as needed.

[0077] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 709, and / or installed from a removable medium 711. When the computer program is executed by a central processing unit (CPU) 701, the above-mentioned functions defined in the system of the present disclosure are executed.

[0078] It should be noted that the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0079] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0080] The modules involved in the embodiments described in the present disclosure may be implemented by software or hardware. The modules described may also be set in a processor, for example, it may be described as: a processor includes a test preparation module and a test running module. The names of these modules do not constitute a limitation on the modules themselves in some cases, for example, the test preparation module may also be described as a "module for obtaining memory allocation parameters from a connected terminal".

[0081] As another aspect, the present disclosure also provides a computer-readable medium, which may be included in the device described in the above embodiment; or may exist independently without being assembled into the device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by a device, the device includes: obtaining the CPU accessible space of the memory to be tested; obtaining the graphics processor accessible space of the memory to be tested; driving the CPU to run a test program based on the CPU accessible space to access the memory to be tested through the memory to be tested bus, wherein when the CPU runs the test program, the graphics processor is controlled to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space.

[0082] The exemplary embodiments of the present disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A memory testing method, characterized in that: include: Acquiring a CPU-accessible space of the memory to be tested, including obtaining the CPU-accessible capacity according to the capacity of the memory to be tested, and obtaining an address at which the CPU can access the memory to be tested; Acquiring a graphics processor-accessible space of the memory to be tested, including obtaining the graphics processor-accessible capacity according to the capacity of the memory to be tested, and obtaining an address at which the graphics processor can access the memory to be tested; Driving the central processor to run a test program based on the central processor accessible space to access the memory to be tested through a memory to be tested bus, wherein when the central processor runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space, comprises: The central processing unit and the graphics processing unit serially access the memory under test through the memory under test bus, and the memory under test bus is an advanced extensible interface protocol bus including a predetermined transmission channel.

2. The method according to claim 1, characterized in that The central processing unit and the graphics processor serially access the memory to be tested through the memory to be tested bus, comprising: The central processing unit and the graphics processing unit serially access the memory to be tested through the predetermined transmission channel according to the test program.

3. The method according to claim 1, characterized in that When the central processor runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space comprises: The central processing unit controls the graphics processor to access the memory to be tested in a predetermined access manner according to the test program based on an open programming language.

4. The method according to claim 1, characterized in that: When the central processor runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space comprises: The central processing unit controls the graphics processor to access the memory to be tested in a predetermined access mode according to the test program through an open graphics program interface.

5. The method according to any one of claims 1 to 4, characterized in that: The memory to be tested is a low-power internal memory; The accessing the memory to be tested through the memory to be tested bus comprises: The central processing unit accesses the low-power internal memory via the memory controller through the memory bus to be tested; When the central processor runs the test program, controlling the graphics processor to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space comprises: The graphics processor accesses the low-power internal memory via the memory controller through the memory bus to be tested.

6. A memory testing system, characterized in that: Includes a central processing unit and a graphics processing unit, including: The central processor is used to run a test program based on the allocated central processor accessible capacity to access the memory to be tested, wherein when the central processor runs the test program, the graphics processor is controlled to access the memory to be tested based on the allocated graphics processor accessible capacity; the central processor and the graphics processor serially access the memory to be tested through the memory to be tested bus, and the memory to be tested bus is an advanced extensible interface protocol bus including a predetermined transmission channel; The graphics processor is used to access the memory to be tested based on the accessible capacity of the graphics processor; Wherein, obtaining the CPU-accessible space of the memory to be tested includes obtaining the CPU-accessible capacity according to the capacity of the memory to be tested, and obtaining the address at which the CPU can access the memory to be tested; Acquiring the graphics processor accessible space of the memory to be tested includes obtaining the graphics processor accessible capacity according to the capacity of the memory to be tested, and obtaining the address of the memory to be tested accessible by the graphics processor.

7. A memory testing device, characterized in that: include: A test preparation module, used for obtaining the CPU-accessible space of the memory to be tested, including obtaining the CPU-accessible capacity according to the capacity of the memory to be tested, and obtaining the address of the memory to be tested accessible by the CPU; Acquiring a graphics processor-accessible space of the memory to be tested, including obtaining the graphics processor-accessible capacity according to the capacity of the memory to be tested, and obtaining an address at which the graphics processor can access the memory to be tested; A test running module is used to drive the central processing unit to run a test program based on the central processing unit accessible space to access the memory to be tested through a memory to be tested bus, wherein when the central processing unit runs the test program, the graphics processor is controlled to access the memory to be tested through the memory to be tested bus based on the graphics processor accessible space, including: the central processing unit and the graphics processor serially access the memory to be tested through the memory to be tested bus, and the memory to be tested bus is an advanced extensible interface protocol bus including a predetermined transmission channel.

8. A device comprising: A memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor implements the method according to any one of claims 1 to 5 when executing the executable instructions.

9. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that: When the executable instructions are executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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