Display device supporting variable frame mode

Abstract

The present invention relates to a display apparatus supporting a variable frame mode. The display apparatus can support a variable frame mode, and the display apparatus can include a display panel including a plurality of pixels, a data driver providing a data voltage to the plurality of pixels, a gate driver providing a gate signal to the plurality of pixels, and a controller controlling the data driver and the gate driver. At this time, when operating in the variable frame mode, the controller can control a size of a sensing initialization voltage applied to the pixels based on a value of a frame rate.

Description

Technical Field

[0001] This invention relates to a display device, and more particularly to a display device supporting a variable frame mode and a driving method for the display device. Background Technology

[0002] Typically, display devices display (or refresh) images at a predetermined frame rate of 60Hz or higher. However, the frame rate rendered by the host processor (e.g., graphics processing unit (GPU) or graphics card) that provides frame data to the display device may not match the refresh rate of the display device. This frame rate mismatch can be particularly severe when the host processor provides frame data for game images that are being rendered in a complex manner, and this mismatch can result in tearing of borders in the images displayed on the display device.

[0003] To prevent such tearing, variable frame modes (e.g., Free-Sync mode, G-Sync mode) have been developed, where the host processor changes the blanking intervals in each frame to provide frame data to the display device at a variable frame rate. Display devices supporting these variable frame modes can prevent tearing by displaying (or refreshing) images in sync with the variable frame rate.

[0004] However, in display devices operating in variable frame mode, when displaying low grayscale images on the display panel, in high frequency regions (i.e., when the frame rate is high), in blank areas, brightness may decrease and image quality may degrade due to leakage current, LED on-slew, etc. Summary of the Invention

[0005] One object of the present invention is to provide a display device that can improve image quality in a variable frame mode.

[0006] Another object of the present invention is to provide a driving method for a display device that can improve image quality in a variable frame mode.

[0007] However, the technical problem to be solved by the present invention is not limited to the above-mentioned technical problem. The present invention can be extended in various ways without departing from the idea and concept of the present invention.

[0008] To achieve an objective of the present invention, a display device according to an embodiment of the present invention can support a variable frame mode and may include: a display panel including a plurality of pixels; a data driver providing data voltages to the plurality of pixels; a gate driver providing gate signals to the plurality of pixels; and a controller controlling the data driver and the gate driver. In this case, when operating in the variable frame mode, the controller can control the magnitude of the sensing initialization voltage applied to the pixels based on the frame rate value.

[0009] In one embodiment, when operating in the variable frame mode, the controller can control the sensing initialization voltage to a first voltage level in the interval where the display panel is driven at a first frame rate, and control the sensing initialization voltage to a second voltage level higher than the first voltage level in the interval where the display panel is driven at a second frame rate higher than the first frame rate.

[0010] In one embodiment, the system may further include a power supply voltage generation circuit to generate the sensing initialization voltage. During the interval where the display panel is driven at the first frame rate, the controller may provide a first voltage control signal to the power supply voltage generation circuit to control the power supply voltage generation circuit to generate the sensing initialization voltage at the first voltage level. Furthermore, during the interval where the display panel is driven at the second frame rate, the controller may provide a second voltage control signal to the power supply voltage generation circuit to control the power supply voltage generation circuit to generate the sensing initialization voltage at the second voltage level.

[0011] In one embodiment, the power supply voltage generation circuit can generate a first reference voltage according to the first voltage control signal, and generate a second reference voltage higher than the first reference voltage according to the second voltage control signal. The data driver controls the magnitude of the data voltage applied to the pixel based on the first reference voltage and the second reference voltage.

[0012] In one embodiment, the data voltage may have a larger magnitude in the interval where the display panel is driven at the first frame rate compared to the interval where the display panel is driven at the second frame rate.

[0013] In one embodiment, the power supply voltage generation circuit can generate a first power supply voltage applied to the pixel, and control the magnitude of the first power supply voltage applied to the pixel based on the first voltage control signal and the second voltage control signal.

[0014] In one embodiment, the first power supply voltage may have a larger magnitude in the interval during which the display panel is driven at the first frame rate compared to the interval during which the display panel is driven at the second frame rate.

[0015] In one embodiment, the controller can determine whether to operate in the variable frame mode in each frame.

[0016] In one embodiment, the controller may include: a valid time counter that counts the input clock signal during a valid interval to generate a valid count signal; and a blank time counter that counts the input clock signal during a blank interval to generate a blank count signal. In this case, the controller can determine whether to operate in the variable frame mode based on the valid count signal and the blank count signal.

[0017] In one embodiment, the controller can determine whether to operate in the variable frame mode by receiving the start signal of the variable frame mode through the inter-integrated circuit (I2C) interface.

[0018] To achieve another objective of the present invention, a driving method for a display device according to an embodiment of the present invention may include the following steps: determining whether to operate in the variable frame mode; when operating in the variable frame mode, controlling the magnitude of the sensing initialization voltage applied to the pixel based on the frame rate value; and displaying an image based on the sensing initialization voltage.

[0019] In one embodiment, the feature is that, in the step of controlling the magnitude of the sensing initialization voltage, when operating in the variable frame mode, the sensing initialization voltage is controlled to a first voltage level in the interval where the display panel is driven at a first frame rate, and the sensing initialization voltage is controlled to a second voltage level higher than the first voltage level in the interval where the display panel is driven at a second frame rate higher than the first frame rate.

[0020] In one embodiment, the feature is that, in the step of controlling the magnitude of the sensing initialization voltage, during the interval in which the display panel is driven at the first frame rate, a first voltage control signal is provided to the power supply voltage generation circuit to control the power supply voltage generation circuit to generate the sensing initialization voltage at the first voltage level, and during the interval in which the display panel is driven at the second frame rate, a second voltage control signal is provided to the power supply voltage generation circuit to control the power supply voltage generation circuit to generate the sensing initialization voltage at the second voltage level.

[0021] In one embodiment, the method may further include the following steps: generating a first reference voltage based on the first voltage control signal, generating a second reference voltage higher than the first reference voltage based on the second voltage control signal, and controlling the magnitude of the data voltage applied to the pixel based on the first reference voltage and the second reference voltage.

[0022] In one embodiment, the data voltage may have a larger magnitude in the interval where the display panel is driven at the first frame rate compared to the interval where the display panel is driven at the second frame rate.

[0023] In one embodiment, the method may further include the following steps: generating a first power supply voltage applied to the pixel, and controlling the magnitude of the first power supply voltage applied to the pixel based on the first voltage control signal and the second voltage control signal.

[0024] In one embodiment, the first power supply voltage may have a larger magnitude in the interval where the display panel is driven at the first frame rate compared to the interval where the display panel is driven at the second frame rate.

[0025] In one embodiment, in the step of determining whether to operate in the variable frame mode, it can be determined in each frame whether to operate in the variable frame mode.

[0026] In one embodiment, the step of determining whether to operate in the variable frame mode may include the following steps: counting the input clock signal during a valid interval to generate a valid count signal; and counting the input clock signal during a blank interval to generate a blank count signal. In this case, the determination of whether to operate in the variable frame mode can be based on the valid count signal and the blank count signal.

[0027] In one embodiment, in the step of determining whether to operate in the variable frame mode, the determination of whether to operate in the variable frame mode can be made by receiving the start signal of the variable frame mode through the interface between integrated circuits (I2C).

[0028] According to embodiments of the present invention, the display device and the driving method of the display device can, when operating in a variable frame mode, increase the sensing initialization voltage applied to each pixel in a frame interval driven at a higher frame rate, thereby shortening the voltage charging time of the anode electrode, thereby preventing brightness reduction due to insufficient voltage charging of the anode electrode and improving image quality.

[0029] However, the effects of the present invention are not limited to those described above, and various extensions can be achieved without departing from the spirit and concept of the present invention. Attached Figure Description

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0031] Figure 2 It is shown Figure 1 The circuit diagram of the pixels.

[0032] Figure 3 It is shown Figure 2 Timing diagram of the input and output signals of the pixels.

[0033] Figure 4 This is a diagram illustrating an example of frame data input to a display device in a variable frame mode.

[0034] Figure 5 This is a timing diagram showing the input and output signals of a pixel when the sensing initialization voltage is controlled.

[0035] Figure 6 This is a flowchart illustrating a driving method for a display device according to an embodiment of the present invention.

[0036] Figure 7 This is a flowchart illustrating a driving method for a display device according to another embodiment of the present invention.

[0037] Figure 8 This is a block diagram illustrating an electronic device including a display device according to an embodiment of the present invention.

[0038] Explanation of reference numerals in the attached figures

[0039] 100: Display device; 110: Display panel

[0040] 120: Data driver; 130: Gate driver

[0041] 140: Power supply voltage generation circuit 150: Controller Detailed Implementation

[0042] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements are omitted.

[0043] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention. Figure 2 It is shown Figure 1 The circuit diagram of the pixel. Figure 3 It is shown Figure 2 Timing diagram of the input and output signals of the pixels. Figure 4 This is a diagram illustrating an example of frame data input to a display device in a variable frame mode.

[0044] Reference Figure 1The display device 100 may include: a display panel 110 including a plurality of pixels PX; a data driver 120 providing data voltage VDATA to the plurality of pixels PX; a gate driver 130 providing gate signal GS to the plurality of pixels PX; a power supply voltage generation circuit 140 generating display panel driving voltages RV, VINIT, and ELVDD; and a controller 150 controlling the data driver 120, the gate driver 130, and the power supply voltage generation circuit 140.

[0045] The display panel 110 may include multiple data lines, multiple gate lines, and multiple pixels PX connected to the multiple data lines and the multiple gate lines. In one embodiment, each pixel PX may include a switching transistor and a capacitor connected to the switching transistor.

[0046] The data driver 120 can generate a data voltage VDATA based on the image data ODAT output from the controller 150 and the data control signal DCTRL, and provide the data voltage VDATA to multiple pixels PX. For example, the data control signal DCTRL may include an output data enable signal, a level start signal, and a load signal, but is not limited thereto. Additionally, the data driver 120 can receive a reference voltage (e.g., a gamma reference voltage) RV from the power supply voltage generation circuit 140. In this case, the data voltage VDATA can be generated based on the reference voltage RV. In one embodiment, the data driver 120 can be implemented using one or more integrated circuits (ICs). Furthermore, according to an embodiment, the data driver 120 can be directly mounted to the display panel 110, or connected to the display panel 110 in a tape carrier package (TCP) configuration. In another embodiment, the data driver 120 can be integrated into the periphery of the display panel 110.

[0047] The gate driver 130 can generate a gate signal GS based on a gate control signal GCTRL output from the controller 150, and provide the gate signal GS to multiple pixels PX. In one embodiment, the gate control signal GCTRL may include a frame start signal and a gate clock signal, but is not limited thereto. In one embodiment, the gate driver 130 can be implemented using an amorphous silicon gate (ASG) driver integrated in the periphery of the display panel 110. In another embodiment, the gate driver 130 can be implemented using more than one gate IC. Furthermore, according to embodiments, the gate driver 130 can be directly mounted to the display panel 110, or connected to the display panel 110 in a TCP configuration.

[0048] The power supply voltage generation circuit 140 can generate a reference voltage RV to be provided to the data driver 120. For example, the power supply voltage generation circuit 140 can receive an input voltage VIN from an external power supply, generate a reference voltage RV based on the input voltage VIN, and provide the reference voltage RV to the data driver 120. The data driver 120 can generate a data voltage VDATA based on the reference voltage RV provided from the power supply voltage generation circuit 140. For example, the data driver 120 can generate grayscale voltages (e.g., 256 grayscale voltages) corresponding to the entire grayscale level (e.g., 0-grayscale level to 255-grayscale level) based on the reference voltage RV, and provide the grayscale voltages corresponding to the grayscale levels indicated by the image data ODAT output from the controller 150 as the data voltage VDATA to multiple pixels PX. In one embodiment, the reference voltage RV may include a positive reference voltage and a negative reference voltage, and the data driver 120 can provide a positive data voltage VDATA to multiple pixels PX based on the positive reference voltage and a negative data voltage VDATA to multiple pixels PX based on the negative reference voltage. Furthermore, the power supply voltage generation circuit 140 can provide a sensing initialization voltage VINIT and a first power supply voltage ELVDD to multiple pixels PX. In one embodiment, the power supply voltage generation circuit 140 can also generate, based on the input voltage VIN, an analog drive voltage supplied to the data driver 120 and / or the controller 150, a common voltage supplied to the display panel 110, and a gate drive voltage (e.g., high gate voltage and low gate voltage) supplied to the gate driver 130. In another embodiment, the power supply voltage generation circuit 140 can be implemented using a power management integrated circuit (PMIC) disposed on a control board on which the controller 150 is disposed.

[0049] The controller (e.g., a timing controller (T-CON)) 150 can receive input image data IDAT and control signals CTRL from an external host processor (e.g., a graphics processing unit (GPU) or graphics card). In one embodiment, the input image data IDAT may be RGB data including red image data, green image data, and blue image data. Furthermore, in one embodiment, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The controller 150 can generate a gate control signal GCTRL, a data control signal DCTRL, and output image data ODAT based on the input image data IDAT and the control signal CTRL. The controller 150 can provide the data control signal DCTRL and the output image data ODAT to the data driver 120 to control the operation of the data driver 120, and provide the gate control signal GCTRL to the gate driver 130 to control the operation of the gate driver 130.

[0050] According to an embodiment of the present invention, the controller 150 can support a variable frame mode. In this mode, the host processor provides input image data IDAT to the display device 100 at a variable frame rate by changing the blank space in each frame interval. The controller 150 synchronizes the output image data ODAT with the variable frame rate and provides it to the data driver 120, thereby supporting the display (or refresh) of images at the variable frame rate. Furthermore, such a variable frame mode can be referred to as Free-Sync mode, G-Sync mode, etc.

[0051] For example, such as Figure 4 As shown, the period or frequency of the rendering 210, 220, 230 of the host processor (e.g., GPU or graphics card) may not be constant (especially when rendering game image data). The host processor can provide the input image data IDAT (i.e., frame data FD1, FD2, FD3) to the display device 100 in the variable frame mode by synchronizing it with the non-constant period or frequency of such rendering 210, 220, 230. That is, in the variable frame mode, each frame FP1, FP2, FP3 includes a constant valid interval AP1, AP2, AP3 with a constant time, but the host processor can change the time of the variable blank intervals BP1, BP2, BP3 of each frame FP1, FP2, FP3 to provide frame data FD1, FD2, FD3 to the display device 100 at a variable frame rate.

[0052] exist Figure 4In the example, when the second frame data FD2 is rendered at a frequency of approximately 240Hz in the first frame FP1 (210), the host processor can provide the first frame data FD1 to the display device 100 at a frame rate of approximately 240Hz. Furthermore, the host processor can output the second frame data FD2 during the effective interval AP2 of the second frame FP2 and continue the variable blank interval BP2 of the second frame FP2 until the rendering of the third frame data FD3 ends (220). Therefore, when the third frame data FD3 is rendered at a frequency of approximately 48Hz in the second frame FP2 (220), the host processor can increase the duration of the variable blank interval BP2 of the second frame FP2 to provide the second frame data FD2 to the display device 100 at a frame rate of approximately 48Hz. In the third frame FP3, when the fourth frame data FD4 is again rendered at a frequency of approximately 240Hz (230), the host processor can again provide the third frame data FD3 to the display device 100 at a frame rate of approximately 240Hz.

[0053] As described above, in the variable frame mode, each frame FP1, FP2, FP3 may include constant valid intervals AP1, AP2, AP3 with constant time independent of the variable frame rate, and variable blank intervals BP1, BP2, BP3 with variable time corresponding to the variable frame rate. For example, in the variable frame mode, as the frame rate decreases, the time of the variable blank intervals BP1, BP2, BP3 may increase. In the variable frame mode, the controller 150 may output the input image data IDAT received at the variable frame rate as output image data ODAT to the data driver 120 at the variable frame rate. Accordingly, the display device 100 supporting the variable frame mode can display the image synchronously with the variable frame rate, thereby preventing tearing due to frame rate mismatch.

[0054] Reference Figures 1 to 3 The pixel PX may include: a first thin-film transistor T1, which applies a first power supply voltage ELVDD to a second node N2 in response to a signal from a first node N1; a second thin-film transistor T2, which outputs a data voltage VDATA to the first node N1 in response to a first signal S1; a third thin-film transistor T3, which outputs a signal from the second node N2 to a sensing node in response to a second signal S2; a storage capacitor CS, including a first terminal connected to the first node N1 and a second terminal connected to the second node N2; and a light-emitting element EE, including a first electrode connected to the second node N2 and a second electrode to which a second power supply voltage ELVSS is applied.

[0055] Here, the second power supply voltage ELVSS can be lower than the first power supply voltage ELVDD. For example, the light-emitting element EE can be an organic light-emitting diode.

[0056] Additionally, during the sensing initialization step, the second signal S2 can be activated, causing the sensing initialization voltage VINIT to be applied to the second node N2.

[0057] like Figure 3 As shown, in sensing mode, the first signal S1 can be activated, thereby applying a data voltage VDATA to the first node N1 through the second thin-film transistor T2. In this case, the data voltage VDATA can be a sensing data voltage used to sense the threshold voltage of the first thin-film transistor T1.

[0058] The first thin-film transistor T1 can be turned on by the sensing data voltage applied to the first node N1 in the sensing mode and the sensing initialization voltage VINIT applied to the second node N2 in the sensing initialization step.

[0059] Furthermore, since the second signal S2 is also activated in the sensing mode, the third thin-film transistor T3 can be turned on, and the signal of the second node N2 is output to the sensing node through the third thin-film transistor T3.

[0060] An analog-to-digital converter can be arranged at the sensing node, and the signal of the second node N2 can be converted into a digital sensing signal by the analog-to-digital converter, so that the threshold voltage of the first thin-film transistor T1 is sensed.

[0061] Additionally, VA can be used to represent the voltage of the anode electrode of the light-emitting element EE. Before the initialization of the light-emitting element EE, due to the data voltage VDATA of the previous frame, the voltage VA of the anode electrode of the light-emitting element EE may have a level of ELVSS+VEL. Here, VEL represents the threshold voltage of the light-emitting element EE. A capacitor connected in parallel may be present in the light-emitting element EE. During the sensing initialization step, the voltage VA of the anode electrode of the light-emitting element EE may have the sensing initialization voltage VINIT. During the emitting step of the light-emitting element EE, the voltage VA of the anode electrode of the light-emitting element EE increases slowly.

[0062] Furthermore, since the blanking interval is variable in the variable frame mode, the duration of the blanking interval can be increased compared to the duration of the blanking interval in the general mode where the image is displayed at a constant frame rate. In this increased blanking interval, leakage current and the like can cause a decrease in brightness and a deterioration in image quality. To prevent image quality degradation due to leakage current and the like in such a variable blanking interval, when operating in the variable frame mode, the controller 150 according to an embodiment of the present invention can control the magnitude of the sensing initialization voltage VINIT applied to the plurality of pixels PX based on the frame rate value.

[0063] For example, compared to displaying medium or high grayscale images, when the display panel 110 displays a low grayscale image, the charging time for the parallel capacitor of the light-emitting element EE may be relatively longer. In particular, with an increased frame rate, since the display panel 110 is driven by a lower current, the parallel capacitor of the light-emitting element EE may not be fully charged, and the image quality may degrade. In the case of an increased frame rate and a relatively longer charging time for the parallel capacitor of the light-emitting element EE, the controller 150 can control the power supply voltage generation circuit 140 to increase the sensing initialization voltage VINIT. In one embodiment, the controller 150 can provide a voltage control signal VCS representing a desired voltage level to the power supply voltage generation circuit 140, thereby controlling the power supply voltage generation circuit 140 to increase the sensing initialization voltage VINIT to the desired voltage level. Accordingly, the decrease in brightness caused by the increased frame rate can be compensated by increasing the sensing initialization voltage VINIT.

[0064] Additionally, the controller 150 can change the reference voltage RV and the first power supply voltage ELVDD in response to an increase in the sensing initialization voltage VINIT. For example, when an image is displayed on the display panel 110 at a higher frame rate, the data voltage VDATA applied to each of the plurality of pixels PX can increase as the sensing initialization voltage VINIT increases. As another example, when an image is displayed on the display panel 110 at a higher frame rate, the first power supply voltage ELVDD applied to each of the plurality of pixels PX can increase as the sensing initialization voltage VINIT increases.

[0065] The following is for reference Figures 1 to 6 The operation of the display device 100 according to an embodiment of the present invention will be described.

[0066] Figure 5 This is a timing diagram showing the input and output signals of pixel PX when the sensing initialization voltage VINIT is controlled. Figure 6 This is a flowchart illustrating a driving method for a display device according to an embodiment of the present invention.

[0067] Reference Figure 5 and Figure 6 According to an embodiment of the present invention, the display device 100 determines whether to operate in the variable frame mode (step S310). When operating in the variable frame mode, it controls the magnitude of the sensing initialization voltage applied to the pixel based on the frame rate value (steps S320, S330) and displays an image based on the sensing initialization voltage (step S340).

[0068] In one embodiment, the display device 100 can determine whether to operate in the variable frame mode (step S310). At this time, when the display device 100 operates in the variable frame mode, the display device 100 can control the magnitude of the sensing initialization voltage applied to the pixel based on the frame rate value (steps S320, S330).

[0069] observe Figure 5 The controller 150 may not control the sensing initialization voltage VINIT when not operating in variable frame mode (NORMAL), given the voltage VA of the anode electrode. Conversely, when operating in variable frame mode (ADAPTIVESYNC), the controller 150 may control the sensing initialization voltage VINIT to a first voltage level during the interval where the display panel 110 is driven at a first frame rate (step S320). Furthermore, when operating in variable frame mode (ADAPTIVESYNC), the controller 150 may control the sensing initialization voltage VINIT to a second voltage level higher than the first voltage level during the interval where the display panel 110 is driven at a second frame rate higher than the first frame rate (step S330). For example, the controller 150 may provide a voltage control signal VCS indicating a desired voltage level to the power supply voltage generation circuit 140 to control the power supply voltage generation circuit 140 to increase the sensing initialization voltage VINIT to the desired voltage level.

[0070] Specifically, the power supply voltage generation circuit 140 can generate a sensing initialization voltage VINIT and transmit it to the display panel 110. At this time, the controller 150 can provide a first voltage control signal to the power supply voltage generation circuit 140 during the period when the display panel 110 is driven at the first frame rate to control the power supply voltage generation circuit 140 to generate the sensing initialization voltage VINIT to the first voltage level (e.g., 2V). Furthermore, the controller 150 can provide a second voltage control signal to the power supply voltage generation circuit 140 during the period when the display panel 110 is driven at the second frame rate to control the power supply voltage generation circuit 140 to generate the sensing initialization voltage VINIT to the second voltage level. At this time, the second voltage level can be higher than the first voltage level (e.g., 2V). The display panel 110 can drive pixels based on the sensing initialization voltage VINIT according to each frame rate, thereby displaying an image (operation S340).

[0071] Thus, when operating in variable frame mode, if the sensing initialization voltage VINIT applied to the pixel increases during the interval in which the display panel 110 is driven at the second frame rate, the capacitor connected in parallel to the light-emitting element EE can be charged quickly. As a result, brightness reduction due to insufficient charging of the anode electrode voltage VA can be prevented, and image quality can be improved.

[0072] Figure 7 This is a flowchart illustrating a driving method for a display device according to another embodiment of the present invention.

[0073] Reference Figure 7 According to an embodiment of the present invention, the display device 100 may determine whether to operate in the variable frame mode in each frame (steps S410, S420). When operating in the variable frame mode, the magnitude of the sensing initialization voltage applied to the pixel is controlled based on the frame rate value (steps S430, S440). The data voltage and the first power supply voltage are controlled to have a larger magnitude in the interval where the display panel 110 is driven at the first frame rate than in the interval where the display panel 110 is driven at the second frame rate (step S450). An image is displayed based on the sensing initialization voltage (step S460).

[0074] In one embodiment, the display device 100 can determine whether to operate in the variable frame mode in each frame (steps S410, S420). Specifically, the display device 100 can receive input data from an external device. The controller 150 can determine whether to operate in the variable frame mode in each frame based on the input data. For example, the controller 150 may include an effective time counter that counts the input clock signal during an effective interval to generate an effective count signal and a blank time counter that counts the input clock signal during a blank interval to generate a blank count signal. In this case, the controller 150 can determine whether to operate in the variable frame mode based on the effective count signal and the blank count signal. As another example, the controller 150 can receive the start signal of the variable frame mode through an inter-integrated circuit (I2C) interface to determine whether to operate in the variable frame mode. The controller 150 determines the variable frame mode as described above, so that the controller 150 can determine whether to control the magnitude of the sensing initialization voltage applied to the pixel in each frame.

[0075] In one embodiment, when the display device 100 operates in the variable frame mode, the display device 100 (e.g., controller 150) can control the magnitude of the sensing initialization voltage applied to the pixel based on the frame rate value (steps S430, S440).

[0076] When not operating in variable frame mode (NORMAL), the controller 150 may not control the sensing initialization voltage VINIT. In contrast, when operating in the variable frame mode (ADAPTIVE SYNC), the controller 150 can control the sensing initialization voltage VINIT to a first voltage level during the interval where the display panel 110 is driven at a first frame rate (step S430). Furthermore, when operating in the variable frame mode (ADAPTIVE SYNC), the controller 150 can control the sensing initialization voltage VINIT to a second voltage level higher than the first voltage level during the interval where the display panel 110 is driven at a second frame rate higher than the first frame rate (step S440). For example, the controller 150 may provide a voltage control signal VCS indicating a desired voltage level to the power supply voltage generation circuit 140 to control the power supply voltage generation circuit 140 to increase the sensing initialization voltage VINIT to the desired voltage level.

[0077] Specifically, the power supply voltage generation circuit 140 can generate a sensing initialization voltage VINIT and transmit it to the display panel 110. During the period when the display panel 110 is driven at the first frame rate, the controller 150 can provide a first voltage control signal to the power supply voltage generation circuit 140 to control the power supply voltage generation circuit 140 to generate the sensing initialization voltage VINIT to the first voltage level (e.g., 2V). Furthermore, during the period when the display panel 110 is driven at the second frame rate, the controller 150 can provide a second voltage control signal to the power supply voltage generation circuit 140 to control the power supply voltage generation circuit 140 to generate the sensing initialization voltage VINIT to the second voltage level. In this case, the second voltage level can be higher than the first voltage level (e.g., 2V).

[0078] In one embodiment, the display device 100 can control the data voltage and the first power supply voltage to have a larger size in the interval where the display panel 110 is driven at a second frame rate compared to the interval where the display panel 110 is driven at a first frame rate (step S450). When the image is displayed on the display panel 110 at a higher frame rate, the data voltage VDATA applied to each of the plurality of pixels PX can increase as the sensing initialization voltage VINIT increases. Furthermore, when the image is displayed on the display panel 110 at a higher frame rate, the first power supply voltage ELVDD applied to each of the plurality of pixels PX can increase as the sensing initialization voltage VINIT increases.

[0079] The power supply voltage generation circuit 140 can receive a first voltage control signal from the controller 150 to generate a first reference voltage, and receive a second voltage control signal from the controller 150 to generate a second reference voltage higher than the first reference voltage. The power supply voltage generation circuit 140 can transmit the first and second reference voltages to the data driver 120. At this time, the data driver 120 can control the magnitude of the data voltage applied to the pixel based on the first and second reference voltages. For example, when the display panel 110 is driven at a first frame rate, the data driver 120 can receive the first reference voltage from the power supply voltage generation circuit 140. When the display panel 110 is driven at a second frame rate, the data driver 120 can receive the second reference voltage from the power supply voltage generation circuit 140. In this case, compared to the range where the display panel 110 is driven at the first frame rate, the data voltage generated by the data driver 120 can have a larger magnitude in the range where the display panel 110 is driven at the second frame rate. That is, when the display panel 110 is driven at the second frame rate, causing the sensing initialization voltage VINIT applied to the pixel to increase, the data voltage VDATA applied to the pixel can be increased accordingly.

[0080] The power supply voltage generation circuit 140 can generate a first power supply voltage ELVDD applied to the pixel. At this time, the power supply voltage generation circuit 140 can receive a first voltage control signal and a second voltage control signal from the controller 150, and control the magnitude of the first power supply voltage ELVDD applied to the pixel based on these signals. For example, the power supply voltage generation circuit 140 can receive the first voltage control signal from the controller 150 when the display panel 110 is driven at a first frame rate. The power supply voltage generation circuit 140 can receive the second voltage control signal from the controller 150 when the display panel 110 is driven at a second frame rate. In this case, compared to the period when the display panel 110 is driven at the first frame rate, the first power supply voltage ELVDD generated by the power supply voltage generation circuit 140 can have a larger magnitude in the period when the display panel 110 is driven at the second frame rate. That is, when the display panel 110 is driven at the second frame rate, causing the sensing initialization voltage VINIT applied to the pixel to increase, the first power supply voltage ELVDD applied to the pixel can increase accordingly. The display panel 110 can drive the pixels to display an image based on the sensing initialization voltage VINIT, data voltage VDATA and first power supply voltage ELVDD according to each frame rate (step S460).

[0081] Thus, when operating in variable frame mode, as the sensing initialization voltage VINIT, data voltage VDATA, and first power supply voltage ELVDD applied to the pixels increase during the period when the display panel 110 is driven at the second frame rate, the capacitor connected in parallel to the light-emitting element EE can be charged rapidly. Therefore, the display device 100 can prevent brightness reduction due to insufficient charging of the anode electrode voltage VA and can improve image quality. As a result, in the display device 100 according to an embodiment of the present invention, brightness reduction due to frame rate changes in variable frame mode can be prevented.

[0082] Figure 8 This is a block diagram illustrating an electronic device including a display device according to an embodiment of the present invention.

[0083] Reference Figure 8 The electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include multiple ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0084] Processor 1110 can perform specific calculations or tasks. According to embodiments, processor 1110 can be a microprocessor, a central processing unit (CPU), or the like. Processor 1110 can be connected to other components via address bus, control bus, and data bus. According to embodiments, processor 1110 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0085] The memory device 1120 can store data required for the operation of the electronic device 1100. For example, memory device 1120 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and / or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), and mobile DRAM.

[0086] Storage device 1130 may include a solid-state drive (SSD), a hard disk drive (HDD), a compact disc read-only memory (CD-ROM), etc. Input / output device 1140 may include input structures such as a keyboard, keypad, touchpad, touch screen, mouse, etc., and output structures such as speakers, printers, etc. Power supply 1150 can supply the power required for the operation of electronic device 1100. Display device 1160 can be connected to other components via the bus or other communication links.

[0087] The display device 1160 can determine whether to operate in the variable frame mode at each frame. When operating in the variable frame mode, it controls the magnitude of the sensing initialization voltage applied to the pixels based on the frame rate value. It controls the data voltage and the first power supply voltage to have a larger magnitude compared to the interval where the display panel is driven at a first frame rate and the interval where the display panel is driven at a second frame rate, and displays the image based on the sensing initialization voltage. Accordingly, the display device 1160 can prevent brightness reduction due to insufficient charging of the anode electrode and can improve image quality. As a result, in the display device 1160 according to an embodiment of the present invention, brightness reduction due to frame rate changes in the variable frame mode can be prevented.

[0088] According to the embodiments, the electronic device 1100 may be any electronic device including the display device 1160, such as a digital television, a 3D television, a personal computer (PC), a home electronics device, a laptop computer, a tablet computer, a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0089] Industrial availability

[0090] This invention can be applied to any display device that supports variable frame mode and electronic devices including such display devices. For example, this invention can be applied to any electronic device including a display device, such as a television, digital television, 3D television, mobile phone, smartphone, tablet computer, laptop computer, personal computer, home electronics, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigator, etc.

[0091] Although the above description has been made with reference to embodiments of the present invention, those skilled in the art should understand that various modifications and alterations can be made to the present invention without departing from the spirit and concept of the invention as set forth in the claims.

Claims

1. A display device supporting a variable frame mode, characterized in that, include: The display panel includes multiple pixels; A data driver provides data voltage to the plurality of pixels; A gate driver provides gate signals to the plurality of pixels; The controller controls the data driver and the gate driver; as well as The power supply voltage generation circuit generates the sensing initialization voltage. When operating in the variable frame mode, the controller controls the magnitude of the sensing initialization voltage applied to the pixel based on the frame rate value. When operating in the variable frame mode, during the interval in which the display panel is driven at a first frame rate, the controller provides a first voltage control signal to the power supply voltage generation circuit to control the power supply voltage generation circuit to generate the sensing initialization voltage to a first voltage level. During the interval where the display panel is driven at a second frame rate higher than the first frame rate, the controller provides a second voltage control signal to the power supply voltage generation circuit to control the power supply voltage generation circuit to generate the sensing initialization voltage to a second voltage level higher than the first voltage level. The power supply voltage generation circuit generates a first reference voltage based on the first voltage control signal, and generates a second reference voltage higher than the first reference voltage based on the second voltage control signal. The data driver controls the magnitude of the data voltage applied to the pixel based on the first reference voltage and the second reference voltage, so that it has a larger magnitude in the range where the display panel is driven at the second frame rate than in the range where the display panel is driven at the first frame rate. The power supply voltage generation circuit generates a first power supply voltage applied to the pixel, and controls the magnitude of the first power supply voltage applied to the pixel based on the first voltage control signal and the second voltage control signal. When operating in the variable frame mode, if the sensing initialization voltage, the data voltage, and the first power supply voltage applied to the pixel increase during the interval in which the display panel is driven at the second frame rate, the capacitor included in the pixel and connected in parallel to the light-emitting element is charged in a manner that prevents a decrease in brightness due to insufficient charging of the anode electrode voltage.

2. The display device according to claim 1, characterized in that, The data voltage has a larger magnitude in the interval where the display panel is driven at the first frame rate compared to the interval where the display panel is driven at the second frame rate.

3. The display device according to claim 1, characterized in that, Compared to the range in which the display panel is driven at the first frame rate, the first power supply voltage has a larger magnitude in the range in which the display panel is driven at the second frame rate.

4. The display device according to claim 1, characterized in that, The controller determines in each frame whether to operate in the variable frame mode.

5. The display device according to claim 4, characterized in that, The controller includes: An effective time counter generates an effective count signal by counting the input clock signal during the effective interval; and A blank time counter generates a blank count signal by counting the input clock signal during blank intervals. The controller determines whether to operate in the variable frame mode based on the valid count signal and the blank count signal.

6. The display device according to claim 4, characterized in that, The controller receives the start signal of the variable frame mode through the interface between integrated circuits to determine whether to operate in the variable frame mode.

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