Magnetic random access memory

Abstract

The application provides a magnetic random access memory. When a write circuit provides a gradually increased line voltage and sets the line voltage to a bit line / source line of a selected cell, a voltage change of the bit line / source line is detected by a write detection circuit to form detection data. After the detection data is compared with to-be-written data, it is determined whether to turn off a write driver corresponding to a line of the selected cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory technology, and in particular to a magnetic random access memory and its write circuit architecture. BACKGROUND

[0002] In a write operation, a current from bit line to source line is applied to the MRAM to write the MTJ into a p state (low resistance state), or a current from source line to bit line is applied to the MRAM to write the MTJ into an ap state (high resistance state). Because this write current is large, it takes a long time, typically 10 nS-100 nS. In a read operation, a small current is needed and the time is short, typically 1 nS-10 nS. Therefore, it is very difficult to reduce the write current and write time of the MRAM. Moreover, the current write power of the MRAM is still large, the write current is high, and the energy waste is very large. For example, if a bit needs to be written to 1, there is a 50% chance that the bit is already a 1 and does not need to be written. However, the write circuit cannot know the previous state of the bit, so whether the previous state is 1 or 0, a common approach is to perform a write operation. In a statistical sense, half of the energy is wasted. Secondly, the write operation is to apply an electrical pulse to a bit, and the pulse must be maintained for a certain length of time to control the error rate within an acceptable range. For example, for a 1 megabit array in practice, the length of the write pulse may need to be 30 nanoseconds to control the error rate within one in a million, but in fact, within 10 nanoseconds, more than 90% of the bits have completed the write operation. However, randomly, there may be one in a million bits that need 30 nanoseconds to complete the write operation. The write circuit does not know the write time required by each bit, and can only extend the pulse time to the most conservative case. In this way, even for the vast majority of bits that need to be written, 2 / 3 or even more energy is wasted.

[0003] To reduce the write energy waste, there are two methods in the industry. One is to use a write state detection circuit as shown in US20180061466, which can detect the state of the written bit while performing the write operation, and terminate the write operation as soon as the state of the bit has reached the target value. Such a write state detection circuit can greatly reduce the write power consumption. The second is to add a read verification operation in the middle of the write operation as shown in US20120127788A1, which closes the write operation that has been successfully written, thereby achieving the purpose of saving write power consumption. However, detecting the state of the written bit while writing will require a certain proportion of MTJ to have a longer write time, affecting the overall write speed. The direct post-verification method in the write operation requires adding a read operation in the middle of the write operation, although the time of each read can be relatively short, but since the number of reads cannot be determined, the time of the write operation may be greatly increased. SUMMARY

[0004] To solve the above technical problems, the purpose of the present application is to provide a magnetic random access memory, which reduces the write power consumption and improves the write speed by setting a write detection circuit and its supporting mechanism in the write circuit.

[0005] The purpose of the present application and the solution to the technical problems are realized by adopting the following technical solutions.

[0006] According to the magnetic random access memory provided by the present application, it comprises a write circuit, a storage array, a row address decoder and a column address decoder, the row address decoder and the column address decoder respectively generate row address information and column address information to the storage array to select one or more selected units, and write the write data provided by the write circuit into the selected units. The write circuit comprises: a line voltage generator for generating a plurality of line voltages which are sequentially raised; a line write driver for generating a line setting voltage corresponding to the selected unit according to the data to be written, the line setting voltage being raised in potential according to the plurality of line voltages which are sequentially raised; a write detection circuit connected between the column address decoder and the line write driver, which detects the line setting voltage in real time during the execution of the write operation to obtain detection data, and compares the detection data with the data to be written to determine whether to close the line write driver corresponding to the selected unit.

[0007] The technical problems of the present application can also be further realized by adopting the following technical measures.

[0008] Optionally, it further comprises a timing controller for generating a timing signal, and the line voltage generator cooperates with the pulse of the timing signal to provide line voltages of different potentials.

[0009] Optionally, the line voltage generator and the line write driver are provided with a plurality of connection lines, the bit line voltage generator is connected to the timing controller to obtain the timing signal, and a corresponding connection line outputs a line voltage according to a pulse selection of the timing signal.

[0010] Optionally, the line voltage generator and the line write driver are provided with a plurality of connection lines, each connection line is provided with a corresponding switch, the write detector controls the on and off of each connection line according to a pulse timing of the timing signal, so that the line voltage generator provides a line voltage with a different potential according to a pulse timing of the timing signal.

[0011] Optionally, the line voltage generator and the line write driver are provided with a plurality of connection lines, each connection line is provided with a corresponding switch, the write detector controls the on and off of each connection line according to a pulse timing of the timing signal, so that the line voltage generator provides a line voltage with a different potential according to a pulse timing of the timing signal.

[0012] Optionally, the line voltage generator provides a line voltage with a potential at a previous pulse, which is lower than a potential of a line voltage provided at a next pulse; the write detection circuit obtains the detection data at the previous pulse, and compares the detection data with the to-be-written data at the next pulse.

[0013] Optionally, when there is more than one consistent data between the detection data and the to-be-written data, the line write driver of a selected unit matched with the consistent data is directly or indirectly controlled to be turned off by the detection circuit; the line write driver of a selected unit matched with an inconsistent data of a selected unit is executed to operate; when the detection data and the to-be-written data are determined to be consistent, no data is written and the write operation is ended.

[0014] Optionally, the write operation is a write 1 state, the line voltage generator is a bit line voltage generator, the line write driver is a bit line write driver, the line voltage is a bit line voltage, and the line setting voltage is a bit line setting voltage; the write operation is a write 0 state, the line voltage generator is a source line voltage generator, the line write driver is a source line write driver, the line voltage is a source line voltage, and the line setting voltage is a source line setting voltage. The above two configurations can be set alternatively or simultaneously.

[0015] The application reduces unnecessary write operations through the detection mechanism of the write circuit, compared with the ordinary MRAM write circuit. The application not only reduces write power consumption, but also improves the reliability of the MRAM unit. Second, compared with the existing write detection circuit method, the application uses a multi-stage write circuit design to gradually increase the write voltage to implement MRAM write operation, which can improve the write speed of MRAM. Third, due to the characteristics of MRAM unit write operation, most units can be completed quickly, and only a small part of the write time is relatively long; too high write voltage will affect the service life of the MRAM unit. Fourth, the method of the application can complete the write operation of most units at a lower voltage, improve the overall service life of the MRAM; a small part of the unit completes the write operation at a higher voltage, which has little effect on the overall service life of the MRAM. In summary, the application can effectively improve the write speed of the MRAM as a whole, shorten the write time, and reduce the write power consumption of the MRAM. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 Schematic diagram of an exemplary magnetic random access memory storage cell structure;

[0017] Figure 2 Schematic diagram of a magnetic tunnel junction structure in an exemplary magnetic random access memory storage cell;

[0018] Figure 3 Exemplary magnetic random access memory chip architecture diagram;

[0019] Figure 4 Write state detection circuit schematic diagram of US20180061466;

[0020] Figure 5 Read verification method schematic diagram of US20120127788A1;

[0021] Figure 6A Write circuit schematic diagram of the magnetic random access memory architecture of the embodiment of the application;

[0022] Figure 6B Write circuit schematic diagram of the magnetic random access memory architecture of the embodiment of the application;

[0023] Figure 6C Write circuit schematic diagram of the magnetic random access memory architecture of the embodiment of the application;

[0024] Figure 7 Magnetic random access memory chip architecture diagram of the embodiment of the application;

[0025] Figure 8 Timing diagram of the magnetic random access memory architecture of the embodiment of the application. DETAILED DESCRIPTION

[0026] The following descriptions of the embodiments are with reference to the accompanying drawings, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes only, and not for limiting the invention.

[0027] The accompanying drawings and descriptions are intended to be illustrative in nature, not restrictive. In the drawings, structurally similar units are denoted by the same reference numerals. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, but the invention is not limited thereto.

[0028] In the accompanying drawings, the configuration range of devices, systems, components, and circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when a component is referred to as being "on" another component, the component may be directly on the other component, or there may be an intermediate component present.

[0029] Additionally, in the specification, unless explicitly stated otherwise, the word "comprising" will be understood to mean including the stated component, but not excluding any other components. Furthermore, in the specification, "on" means located above or below the target component, and does not mean that it must be located on top based on the direction of gravity.

[0030] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, describes the specific implementation, structure, features, and effects of a magnetic random access memory architecture and its manufacturing method based on the present invention.

[0031] Figure 1 This is a schematic diagram illustrating an exemplary magnetic random access memory (MRM) storage cell structure. Figure 1 The diagram shows a schematic representation of a magnetic tunnel junction in low-resistance state 01 and high-resistance state 02. The magnetic random access memory (MRAM) includes a memory layer 03, a tunnel barrier layer 04, and a reference layer 05. Reading from the MRAM involves measuring the resistance of the magnetic tunnel junction 07 (MTJ). Writing to the magnetic tunnel junction 07 is also relatively simple using the newer STT-MRAM technology: a stronger current than that used for reading is applied through the magnetic tunnel junction 07 for the write operation. A bottom-up current sets the variable magnetization layer in an antiparallel direction to the fixed layer, while a top-down current sets it in a parallel direction.

[0032] Figure 2 This is a schematic diagram illustrating the magnetic tunnel junction structure in an exemplary magnetic random access memory (MRAM) storage cell. Figure 2As shown, the most basic magnetic random access memory (MRAM) cell consists of a magnetic tunnel junction (MTJ) and a MOSFET. The gate of the MOSFET is connected to the chip's word line, which controls whether the cell is turned on or off. The MTJ is connected in series with the MOSFET to the chip's bit line via vias (top / bottom electrodes), metal layers, and contact points. Read and write operations are performed on the bit line. Two memory cells share a single source line.

[0033] Figure 3 This is a schematic diagram of an exemplary magnetic random access memory (MRM) chip architecture. Figure 3 As shown, a magnetic random access memory (MRAM) chip consists of an array of one or more MRAM memory cells. Each array has several external circuits, such as: row address decoder: converts the received address into word line selection; column address decoder: converts the received address into bit line / source line selection; and read / write circuit: controls the read (measurement) and write (current application) operations on the bit line / source line and exchanges data with the outside.

[0034] As mentioned in the background section, there are two main methods used in the industry to reduce write power waste. One is to use a write status detection circuit, which can detect the status of the bit being written while performing the write operation. Once the status of the bit has reached the target value, the write operation is immediately terminated. Such a write status detection circuit can significantly reduce write power consumption. The second method is to add a read verification operation in the middle of the write operation, disabling successfully completed write operations, thereby saving write power consumption.

[0035] like Figure 4As shown, US20180061466 proposes a write state detection circuit. It proposes: 1. Adding a write state detection circuit in MRAM, when the written bit has reached the target state, the write operation is terminated in advance. 2. A reference cell is needed, with a reference resistance. 3. The write detection circuit compares the resistance of the written cell with the reference resistance to determine its state at that time. 4. The specific implementation method is to apply the same voltage to the reference cell as the written cell, and compare the potential at the same point on the write loop. The resistance of the written cell is different, which will inevitably cause the voltage division of the circuit to be different, causing the point on the detected point to change. Among them, 453 is the MTJ being written, T10 is the control MOS tube of this memory cell; 457 and T12 are reference cells; switches S1 and S2 select one to open and the other to close according to whether writing 0 or 1; the same voltage VDD is applied to the written cell and the reference cell; two write loops are connected to the written cell through T5, T3, T1 and a series of switches, and to the reference cell through T6, T4, T2 and a series of switches; The potentials of the two detection points n2 and n3 are input to the comparison control unit 420, which contains a comparator 421 and related logic to generate the control signals EN and ENb for early termination of the write operation.

[0036] As Figure 5 , US20120127788A1 proposes to add a read verification method in the write operation. This patent uses a verification pulse (VP1) to verify the write effect after the write pulse (WP1). If the write is successful, the corresponding write circuit is turned off. If the write is not successful, a second write pulse (WP2) and a verification pulse (VP2) are used, and the number of writes can be increased in turn until the desired result is obtained. This method can theoretically reduce the write time and reduce the write power consumption, but because of the verification time added in the middle of the write, the total write time will be increased.

[0037] Both solutions can reduce write power consumption to a certain extent, but both have certain shortcomings. The method proposed by US20180061466 patent will have a certain proportion of MTJ that needs a longer write time, affecting the overall write speed. The method proposed by US20120127788A1 patent needs to add a read operation in the middle of the write operation, although the time of each read can be relatively short, but because the number of reads cannot be determined, the time of the write operation may be greatly increased in the end.

[0038] Figure 6A 、 Figure 6B With Figure 6C respectively show the write circuit concept diagram of the magnetic random access memory architecture of the embodiments of the present application; Figure 7Figure 1 is a schematic diagram of a magnetic random access memory chip according to an embodiment of the present application. The magnetic random access memory includes a write circuit, a memory array, a row address decoder, and a column address decoder (formed by a plurality of column selection MUXs). The row address decoder and the column address decoder generate row address information and column address information, respectively, to the memory array to select one or more selected cells. The write circuit includes a line voltage generator, a line write driver, and a write detection circuit, which generate signals required by bit lines and source lines of magnetic tunnel junctions (MTJs).

[0039] In an embodiment of the present application, the line voltage generator generates a plurality of line voltages that are sequentially increased. The line write driver generates a line setting voltage corresponding to the selected cells according to the data to be written. The line setting voltage is increased in potential according to the plurality of line voltages that are sequentially increased. The write detection circuit is connected between the column address decoder and the line write driver. During execution of a write operation, the write detection circuit detects the line setting voltage in real time to obtain detection data, and compares the detection data with the data to be written to determine whether to turn off the line write driver corresponding to the selected cells.

[0040] Optionally, the line voltage generator is a bit line voltage generator, the line write driver is a bit line write driver, the line voltage is a bit line voltage, and the line setting voltage is a bit line setting voltage. Alternatively, the line voltage generator is a source line voltage generator, the line write driver is a source line write driver, the line voltage is a source line voltage, and the line setting voltage is a source line setting voltage. The above two configurations can be selectively set or simultaneously set.

[0041] Optionally, the write circuit is further connected to a timing controller. The timing controller is configured to provide a timing signal CLK. The line voltage generator is configured to provide line voltages with different potentials in cooperation with pulses of the timing signal.

[0042] Optionally, the line voltage generator and the line write driver are provided with a plurality of connection lines. The bit line voltage generator is connected to the timing controller to obtain the timing signal. The bit line voltage generator is configured to select a corresponding connection line to output a line voltage according to a pulse of the timing signal. Figure 6AAs shown, the bit line voltage generator has three output connection lines, which are respectively used to provide a set of bit line voltages VWBL1, VWBL2, and VWBL3 that increase in sequence. These connection lines are connected to the bit line write driver. In practice, only one connection line is the effective output at the same time, and which connection line is effective is determined according to the timing signal CLK. That is, the bit line write driver will generate the bit line setting voltage IO_BL and waveform required for the bit line of the magnetic tunnel junction MTJ based on the obtained bit line voltage, the data to be written DATA, and the write control signal WE. Similarly, the source line voltage generator has three output connection lines, which are respectively used to provide a set of source line voltages VWSL1, VWSL2, and VWSL3 that increase in sequence. These connection lines are connected to the source line write driver. In practice, only one connection line is the effective output at the same time, and which connection line is effective is determined according to the timing signal CLK. That is, the source line write driver will generate the source line setting voltage IO_SL and waveform required for the source line of the magnetic tunnel junction MTJ based on the obtained source line voltage, the data to be written DATA, and the write control signal WE. Among them, VWBl1 < VWBL2 < VWBL3, and VWSl1 < VWSL2 < VWSL3.

[0043] Optionally, the line voltage generator and the line write driver are provided with multiple connection lines, and each connection line is provided with a corresponding switch. The write detector controls the on and off of each connection line according to the pulse timing of the timing signal CLK, so that the line voltage generator provides line voltages with different potentials in cooperation with the pulse timing of the timing signal CLK. As Figure 6B shown, different from Figure 6A it, the bit line write driver of the MRAM has multiple connection lines for bit line voltages. Each connection line forms a path or an open circuit through switches B1, B2, and B3. In the same period, only one path is closed (conductive) each time. The source line write driver of the MRAM has multiple connection lines for source line voltages. Each connection line forms a path or an open circuit through switches S1, S2, and S3. In the same period, only one path is closed (conductive) each time. These switches are all controlled by the write detection circuit, and the write detection circuit switches the switches according to the pulse timing of the timing signal CLK.

[0044] Optionally, the line voltage generator and the line write driver are provided with a connection line. The bit line voltage generator is connected to the timing controller to obtain the timing signal, and switches the output line voltage according to the pulse of the timing signal. Further, the line voltage generator is provided with a plurality of voltage lines, and each voltage line has a switch at its output end. The bit line voltage generator controls the connection and disconnection of each voltage line and the connection line according to the pulse of the timing signal to switch the output line voltage.

[0045] As Figure 6C shown, different from the previous figure, there is a connection line for one of the bit line voltages of the MRAM bit line voltage generator. A plurality of voltage circuits are provided inside the bit line voltage generator. The output end of each voltage line forms a connection or disconnection with the connection line through switches B1, B2, and B3. In the same period, only one is closed (connected) each time. There is a connection line for one of the source line voltages of the MRAM source line voltage generator. A plurality of voltage circuits are provided inside the source line voltage generator. Each voltage circuit forms a connection or disconnection with the connection line through switches S1, S2, and S3. In the same period, only one is closed (connected) each time. These switches are respectively controlled by the bit line voltage generator and the source line voltage generator. The bit line voltage generator and the source line voltage generator switch the switches according to the pulse timing of the timing signal CLK.

[0046] Optionally, the potential of the line voltage provided by the line voltage generator in the previous pulse is lower than the potential of the line voltage provided in the subsequent pulse, such as VWBl1 < VWBL2 < VWBL3 and VWSl1 < VWSL2 < VWSL3 as described above.

[0047] In the previous pulse, the write detection circuit obtains the detection data. In the subsequent pulse, the detection data is compared with the data to be written. When there is more than one matching data between the detection data and the data to be written, the selected unit corresponding to the matching data will have its line write driver directly or indirectly controlled by the detection circuit to be turned off; for the selected unit corresponding to the non-matching data, its line write driver performs the operation; when the detection data and the data to be written are judged to be the same, data writing is not performed and the write operation ends. That is to say, the write detection circuit detects the change of the bit line set voltage IO_BL or the source line set voltage IO_SL in real time during the MRAM write operation, and generates the detection data of the MRAM unit. Compare the detection data with the data to be written. If they are the same, it means that the data of the MRAM unit and the data to be written are the same, and the corresponding bit line driver and source line driver of the selected unit are turned off.

[0048] Please continue to refer to Figure 7The MRAM accelerated write circuit includes a bit line write driver, a source line write driver, a bit line voltage generator, a source line voltage generator, a timing controller, a write detection circuit and a data buffer.

[0049] In some embodiments, the row address decoder and the column address decoder generate row address signals and column address signals, respectively. The bit line driver generates a bit line set voltage IO BL, and the source line driver generates a source line set voltage IO SL. The bit line set voltage IO BL and the source line set voltage IO SL are sent to the bit line BL and the source line SL of the MRAM cell through the column address decoder (column selection MUX) controlled by the column address signals, in combination with the row address signals (word line WL) to implement the read and write of the MRAM cell.

[0050] In some embodiments, the timing controller generates the MRAM row address decoder and column address decoder signals and timing signals CLK, and controls the bit line voltage generator and the source line voltage generator according to the timing signals CLK to indirectly control the bit line voltage and the source line voltage.

[0051] In some embodiments, the write detection circuit detects the change of the bit line set voltage IO BL or the source line set voltage IO SL in real time during the MRAM write operation, and generates detection data of the MRAM cell. The detection data and the to-be-written data are compared, and if they are the same, it indicates that the data of the MRAM cell and the to-be-written data are the same, and the bit line driver and the source line driver of the corresponding selected cell are turned off. The bit line / source line voltage generator, the write detection circuit, the row / column address decoding circuit are all synchronously controlled through the timing signal CLK, and the write detection signal is switched through the pulse timing of the timing signal CLK to sequentially switch the switches B1, B2, B3 and the switches S1, S2, S3 to form the bit line voltage and the source line voltage sequentially rising.

[0052] In some embodiments, the write detection circuit obtains the to-be-written data DATA, and detects whether the detection data is consistent with the to-be-written data DATA. If they are consistent, the data of the selected cell does not perform the write operation, and the corresponding bit line driver and source line driver are turned off, thereby reducing the write power consumption; if they are not consistent, the to-be-written data is written into the selected cell.

[0053] Figure 8 The timing diagram of the magnetic random access memory architecture of the embodiments of the present application. Wherein WE is the write enable signal of the memory, and WL is the word line control signal of the MRAM array.

[0054] WE controls memory write operations; a high WE signal indicates a write operation. The timing signal CLK, generated by the timing controller, is a series of short, continuous high-level pulses. The number of pulses can be multiple; three are shown in this example, but this is not a limitation. TR represents the pulse trigger period, and TW represents the pulse interval period, with TW being significantly longer than TR.

[0055] In some embodiments, when the write enable signal WE is initially high, the word line signal WL is high, and a certain current flows through the corresponding magnetic tunnel junction MTJ. The write detection circuit determines whether the magnetic tunnel junction MTJ is in a high-resistance state or a low-resistance state based on the bit line setting voltage IO_BL or the source line setting voltage IO_SL, obtaining detection data. This data is compared with the data to be written. If the detection data matches the data to be written, the bit line / source line write driver corresponding to the data bit is turned off; otherwise, the bit line / source line write driver corresponding to the inconsistent data bit performs a write operation. If all compared data matches, no write operation is performed, and the MRAM completes this write operation.

[0056] In some embodiments, during the first timing signal CLK pulse, the bit line setting voltage IO_BL write voltage is switched to the bit line voltage VWBL1, and the source line setting voltage IO_SL write voltage is switched to the source line voltage VWSL1. The write detection circuit detects the voltage changes of the bit line voltage VWBL1 and the source line voltage VWSL1, forming detection data. After a time interval TR1+TW1, during the second timing signal CLK pulse, the bit line setting voltage IO_BL write voltage is switched to the bit line voltage VWBL2, and the source line setting voltage IO_SL write voltage is switched to the source line voltage VWSL2. At this time, the write detection circuit compares the detection data with the data to be written. If the read data matches the data to be written, the write driver corresponding to the data bit is turned off; if they do not match, the write driver corresponding to the data bit performs a write operation. If all compared data match, no write operation is performed, and the MRAM completes this write operation. During the third timing signal CLK pulse, the detection, comparison, and line control methods of the write detection circuit are similar to those during the second timing signal CLK pulse. The diagram only shows up to the third pulse; in practice, there should be no limit to the number of pulses. If there are multiple pulses, the operation process will follow the same logic.

[0057] The application reduces unnecessary write operations through the detection mechanism of the write circuit, which can not only reduce write power consumption, but also improve the reliability of the MRAM cell. Second, compared with the existing write detection circuit method, the application uses a multi-stage write circuit design to gradually increase the write voltage to implement MRAM write operation, which can improve the write speed of MRAM. Third, due to the characteristics of the write operation of the MRAM cell, most cells can be completed quickly, and only a small part of the write time is relatively long; too high write voltage will affect the service life of the MRAM cell. Fourth, the method of the application can complete the write operation of most cells at a lower voltage, which improves the overall service life of the MRAM; a small part of the cells complete the write operation at a higher voltage, which has little effect on the overall service life of the MRAM. In summary, the application can effectively improve the overall write speed of the MRAM, shorten the write time, and reduce the write power consumption of the MRAM.

[0058] The phrases "in one embodiment of the application" and "in various embodiments" are repeated. This phrase is not intended to necessarily refer to the same embodiment; however, it can also refer to the same embodiment. The words "comprise", "have", and "include" and the like are synonymous, unless the context clearly indicates otherwise.

[0059] The above is only a specific embodiment of the application, and does not limit the application in any form. Although the application has been disclosed as above, it is not intended to limit the application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the technical solution of the application, and any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the application are still within the scope of the technical solution of the application.

Claims

1. A magnetic random access memory comprising a write circuit, a memory array, a row address decoder and a column address decoder, said row address decoder and said column address decoder generating row address information and column address information, respectively, to the memory array to select one or more selected cells to which write data supplied from the write circuit is written, characterized by, The write circuit comprises: ​ a line voltage generator generating a plurality of line voltages in ascending order; a line write driver generating a line setting voltage corresponding to the selected cell according to the data to be written, the line setting voltage being raised in potential according to the plurality of line voltages in ascending order; a write detection circuit detecting the line setting voltage to obtain detection data during execution of the write operation, and comparing the detection data with the data to be written to determine whether to turn off the line write driver corresponding to the selected cell; and a timing controller generating timing signals, the line voltage generator providing line voltages of different potentials in cooperation with the timing signals.

2. The magnetic random access memory of claim 1, wherein, The line voltage generator and the line write driver are provided with a plurality of connection lines, a bit line voltage generator is connected to the timing controller to obtain the timing signals, and the line voltage generator selects a corresponding connection line to output a line voltage according to a pulse of the timing signals.

3. The magnetic random access memory as described in claim 1, characterized in that, The line voltage generator and the line write driver are provided with a plurality of connection lines, each connection line being provided with a corresponding switch, the write detector controls the on and off of each connection line according to a pulse timing of the timing signals, so that the line voltage generator provides line voltages of different potentials in cooperation with the pulse timing of the timing signals.

4. The magnetic random access memory as described in claim 1, characterized in that, The line voltage generator and the line write driver are provided with one connection line, a bit line voltage generator is connected to the timing controller to obtain the timing signals, and the line voltage generator switches the output line voltage according to a pulse of the timing signals.

5. The magnetic random access memory of claim 4, wherein the magnetic tunnel junction is formed on the substrate and the magnetic tunnel junction is formed on the magnetic free layer. The line voltage generator is provided with a plurality of voltage lines, and each voltage line is provided with a switch at an output end, the bit line voltage generator controls the on and off of each voltage line and the connection line according to a pulse of the timing signals to switch the output line voltage.

6. The MRAM of claim 1, wherein, The line voltage generator provides a line voltage at a potential lower than that of a line voltage provided at a next pulse; The write detection circuit obtains the detection data at a previous pulse and compares the detection data with the data to be written at a next pulse.

7. The magnetic random access memory as described in claim 6, characterized in that, When there is more than one consistent data between the detection data and the data to be written, the line write driver of the selected cell matched with the consistent data is directly or indirectly controlled to be turned off by the detection circuit; The line write driver of the selected cell matched with the inconsistent data is executed as an operation; When the detection data and the data to be written are determined to be consistent, no data is written and the write operation is ended.

8. The MRAM of claim 1, wherein, The write operation is a write 1 state, the line voltage generator is a bit line voltage generator, the line write driver is a bit line write driver, the line voltage is a bit line voltage, and the line setting voltage is a bit line setting voltage.

9. The MRAM of claim 1, wherein, The write operation is a write 0 state, the line voltage generator is a source line voltage generator, the line write driver is a source line write driver, the line voltage is a source line voltage, and the line setting voltage is a source line setting voltage.

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