Dry engraving method for through holes

Abstract

The application relates to a via dry etching method, which comprises etching a first interlayer insulating layer and a gate insulating layer by using a second etching gas, the second etching gas comprises Ar, H2 and C2HF5, C2HF5 reacts to generate CF x during the etching process of the first interlayer insulating layer and the gate insulating layer, CF x deposited on the gate insulating layer in the hole causes etching interruption, and the method further comprises removing CF x by using a low-temperature oxygen plasma. The method provided by the application can avoid the etching interruption caused by the deposit in the via dry etching process, reduce the PSI over-etching degree in the via dry etching process, avoid the serious over-etching, ensure the film thickness uniformity of the PSI at the via, eliminate MURA, and improve the product yield.

Description

Technical Field

[0001] This invention relates to the field of display screen technology, and in particular to a method for dry etching vias. Background Technology

[0002] MURA refers to the perceived color difference under the same light source and background color on a display screen.

[0003] Active matrix organic light-emitting diode (AMOLED) displays are widely used due to their advantages such as long lifespan, high brightness, high contrast, and wide color gamut. Thin film transistors (TFTs) are the core components of these displays. In AMOLED displays, each pixel relies on a TFT for switching and driving. Low-temperature polysilicon (LTPS) is an important semiconductor material for the active layer of TFTs. Using LTPS technology enables AMOLED displays to have higher resolution and faster response time, providing a higher quality display.

[0004] In AMOLED production, large-panel displays exhibit MURA (Mullage-Range Radiance) when lit up, resulting in product yield loss. Through analysis and investigation, the inventors discovered that the uneven film thickness of the low-temperature polycrystalline silicon (PSI) at the vias, and the severe local over-etching of the PSI layer, affects the characteristics of the TFTs. If the characteristics of each TFT are affected, it further affects the light emission and display brightness of each sub-pixel, thus causing uneven display brightness, which leads to MURA.

[0005] Vias are formed by dry etching or wet etching. Currently, dry etching is widely used in the industry. Dry etching refers to the etching of the film layer by ionizing organic etching gas and physically bombarding and chemically reacting with it. The etched film layers are the gate insulating layer (GI) and the interlayer insulating layer (ILD). The interlayer insulating layer is further divided into the first interlayer insulating layer (ILD1) and the second interlayer insulating layer (ILD2). There are three etching processes:

[0006] 1. O2+CF4: This process has a fast etching rate and the product is easy to volatilize, but it has poor PSI selectivity. Using only the main etching process will cause severe local PSI over-etching.

[0007] 2.A r +H2+C2HF5: This process has a high selectivity for polysilicon, but the etching process produces CF... X It is easy for deposits to accumulate at the bottom of the hole, which can cause the etching process to be interrupted, resulting in a smaller etching amount.

[0008] 3. The combination of main etching (O2+CF4) and one-step etching (Ar+H2+C2HF5) can achieve good etching speed and selectivity. O2+CF4 is selected to etch the ILD on the upper layer of the via, and then Ar+H2+C2HF5 is selected to etch the GI of the lower layer in one step.

[0009] However, in actual production, it was found that: 1. During the over-etching process, deposits still accumulate at the bottom of the vias, interrupting the etching process and resulting in a smaller etching volume; 2. As production increases, equipment ages, leading to poor PSI uniformity during film formation and dry etching. This manifests as severe PSI over-etching in localized areas of the backplane during main etching, resulting in a decreased PSI selectivity in these areas. Severe localized PSI over-etching causes poor film thickness uniformity, leading to TFT characteristic shifts, uneven display brightness, and MURA (Mullage Raising Aspect Ratio). Summary of the Invention

[0010] To address the technical problems existing in the prior art, the present invention provides a via dry etching method. This method can avoid etching interruption caused by deposits during the via dry etching process. At the same time, it can also improve the situation where the uniformity of via dry etching deteriorates due to equipment aging, resulting in severe PSI over-etching, and improve the situation where the film thickness uniformity of PSI at the via is damaged, thereby eliminating MURA and improving product yield.

[0011] A method for dry etching vias, the method comprising etching a first interlayer insulating layer and a gate insulating layer with a second etching gas, the second etching gas comprising Ar, H2, and C2HF5, wherein the C2HF5 reacts during the etching of the first interlayer insulating layer and the gate insulating layer to generate CF. x The CF x The deposition on the gate insulating layer within the via causes etching interruption, characterized in that the method further includes removing the CF using a low-temperature oxygen plasma. x .

[0012] Furthermore, the method also includes using emission spectroscopy to remove the CF from the low-temperature oxygen plasma. x The process is monitored.

[0013] Furthermore, the method includes the following steps:

[0014] S1: The second etching gas performs a first-step over-etching on the first interlayer insulating layer and the gate insulating layer;

[0015] S2: The low-temperature oxygen plasma removes the CF x ;

[0016] S3: The second etching gas performs a second-step over-etching on the gate insulating layer to form the via.

[0017] Further, the CF is removed by the low-temperature oxygen plasma. x During the process, the O2 flow rate is 700-1000 sccm, the chamber pressure is 3-5 Pa, and the source RF power is 700-1500 W.

[0018] Furthermore, the second etching gas satisfies the following conditions: the C2HF5 flow rate is 30-100 sccm, the H2 flow rate is 30-100 sccm, the Ar flow rate is 200-500 sccm, the chamber pressure is 1-3 Pa, the source RF power is 3000-6000 W, and the bias RF power is 3000-6000 W.

[0019] Furthermore, the etching time of the first step of etching is 30-50s and the etching depth is 30-150nm. After the first step of etching is completed, the remaining etching depth is 10-100nm. The etching time of the second step of etching is 30-50s and the etching depth is 30-150nm. After the second step of etching is completed, the etching depth of the low-temperature polycrystalline silicon layer is 0-20nm.

[0020] Furthermore, the method further includes step S0, wherein step S0 is to perform main etching on the gate insulating layer and the first interlayer insulating layer and the second interlayer insulating layer above the gate insulating layer by a first etching gas, wherein the first etching gas includes O2 and CF4, and step S0 is performed before step S1.

[0021] Furthermore, the etching depth of the main etching is 400-900nm, and the remaining etching depth after the main etching is 50-250nm. The first etching gas satisfies the following conditions: the CF4 flow rate is 300-600sccm, the O2 flow rate is 30-100sccm, the chamber pressure is 1-3Pa, the source RF power is 7000-9500W, and the bias RF power is 2000-4000W.

[0022] Furthermore, emission spectroscopy was used to monitor the main markings on SiN. x The product CN produced by the reaction with CF4 x Monitoring was conducted on the CN emission spectrum. x The starting point of the first interlayer insulating layer etching is the x-coordinate value of the lowest luminous intensity point plus 2-3. The ending point of the main etching is the x-coordinate value of the lowest point plus 32-63. The x-coordinate of the ending point is the main etching time.

[0023] Furthermore, the through-hole dry etching process is carried out in the process chamber, where the upper part of the process chamber is 80°C, the side wall temperature is 80°C, and the temperature of the stage holding the glass substrate is 0°C.

[0024] Compared with existing technologies, the technical solution of this invention has at least the following beneficial effects: This invention improves and optimizes the existing via dry etching method by adding low-temperature oxygen plasma ashing and a second over-etching step. Low-temperature oxygen plasma ashing can remove deposits generated during the etching process, avoid etching interruption, and ensure the etching amount of the over-etching step; the second over-etching step etches GI, reducing the degree of PSI over-etching during via dry etching, improving the situation where the uniformity of PSI film thickness at the via is damaged, eliminating MURA, and improving product yield; at the same time, all steps of this method are carried out on existing process equipment and are also applicable to aging equipment, extending the service life of the equipment and reducing the production cost of enterprises. Attached Figure Description

[0025] The accompanying drawings further illustrate the invention, but the embodiments in the drawings do not constitute any limitation on the invention.

[0026] Figure 1 A flowchart of the through-hole dry etching method provided by the present invention;

[0027] Figure 2 A diagram of a via insulating layer structure provided in one embodiment;

[0028] Figure 3 CN provided for one embodiment x Emission spectrum;

[0029] Figure 4 CF provided for one embodiment x Emission spectrum.

[0030] The reference numerals in the attached figures are: 1-glass substrate, 2-PSI, 3-gate insulating layer, 31-SiO x Gate insulating layer, 32-SiN x Gate insulating layer, 4-interlayer insulating layer, 41-first interlayer insulating layer, 42-second interlayer insulating layer. Detailed Implementation

[0031] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0032] like Figure 1 As shown, a method for dry etching vias includes etching a first interlayer insulating layer and a gate insulating layer using a second etching gas. The second etching gas includes Ar, H2, and C2HF5. During the etching process of the first interlayer insulating layer and the gate insulating layer, C2HF5 reacts to generate CF. x CF x The method also includes using low-temperature oxygen plasma to remove CF deposits on the gate insulating layer within the via, which cause etching interruptions. x.

[0033] S101 First etching gas performs main etching on the gate insulating layer and the first interlayer insulating layer and the second interlayer insulating layer above the gate insulating layer;

[0034] like Figure 2 As shown, the film layers forming the vias and their etching sequence from top to bottom are: second interlayer insulating layer 42, first interlayer insulating layer 41, and SiN. x Gate insulating layer 32, SiO x Gate insulating layer 31. The second interlayer insulating layer is composed of SiO2. x The first interlayer insulating layer is composed of SiN x .

[0035] In the main etching process, O2 and CF4 are the first etching gases. The flow rate of CF4 is 300-600 sccm, the flow rate of O2 is 30-100 sccm, the chamber pressure is 1-3 Pa, the source RF power is 7000-9500 W, and the bias RF power is 2000-4000 W.

[0036] CF4 provides the etching ion source. The CF4 flow rate is in the range of 300-600 sccm. The CF4 flow rate is positively correlated with the etching rate, that is, the higher the CF4 flow rate, the faster the etching rate. When the CF4 flow rate is greater than 600 sccm, the effect of increasing the CF4 flow rate on promoting the etching rate is no longer significant. That is, the CF4 flow rate has reached the threshold at 600 sccm. Continuing to increase the CF4 flow rate will result in waste and increase costs. When the CF4 flow rate is less than 300 sccm, the etching speed is slow, which increases the time cost of the main etching process.

[0037] The O2 flow rate in the first etching gas affects the uniformity of the via etching profile tilt. When the O2 flow rate exceeds 100 sccm, the etching profile becomes rough, and delamination occurs in the via etching profile tilt, affecting the accuracy of the etching depth in subsequent etching processes and disrupting the uniformity between the via wall layers. Simultaneously, oxygen increases the etching rate. To prevent excessively rapid etching that could lead to uncontrolled etching and consequently, defective vias and device scrap, oxygen is used. With a CF4 flow rate of 300-600 sccm, the oxygen flow rate is controlled between 30-100 sccm. Within this range, oxygen both accelerates the etching rate and ensures the uniformity between the via wall layers, preventing delamination.

[0038] Pressure affects the concentration of CF4 and O2, which in turn affects the etching rate and etching uniformity. The chamber pressure is 1-3 Pa. Within this range, the etching rate and depth of the second interlayer insulating layer 42, the first interlayer insulating layer 41, and the gate insulating layer 3 during the main etching process can be effectively controlled, ensuring the etching effect of the main etching.

[0039] Power is a factor affecting the etching rate selectivity. The source RF power is 7000-9500W, and the bias RF power is 2000-4000W. When the source RF power and bias RF power are within the above range, the etching rate selectivity is high, that is, the vertical etching speed is greater than the horizontal etching speed. This is beneficial for the etching of the second interlayer insulating layer 42, the first interlayer insulating layer 41, and the gate insulating layer 3. At the same time, the above power settings will not exceed the bearing capacity of the instrument and equipment, and the main etching can be performed on the aging equipment.

[0040] In the main etching process, by controlling the gas flow rate, pressure, power and time, the accuracy of the etching position and depth of the film layer can be improved, which makes it easier to control the etching process and avoid over-etching, which could lead to severe over-etching of the PSI or even etching through the PSI.

[0041] EPD (Endpoint Detector) employs emission spectroscopy. Excited atoms or molecular groups in the plasma emit light of specific wavelengths, and the intensity of this light is related to the concentration of excited atoms and groups. By detecting the intensity of this specific wavelength of light emitted by reactants or products, EPD can obtain real-time information about the plasma etching process. This invention uses emission spectroscopy to monitor the main etching process, specifically for SiN... x The product CN produced by the reaction with CF4 x Monitoring was conducted, and CN was observed in the emission spectrum. x The x-coordinate of the lowest luminous intensity point plus 2-3 marks the etching start point of the first interlayer insulating layer 41. The x-coordinate of the lowest point plus 32-63 marks the main etching end point, and the x-coordinate of the end point is the main etching time. In actual operation, to facilitate data acquisition and ensure that the error is within a reasonable and controllable range, such as... Figure 3 As shown, in the emission spectrum, the intersection point A of the vertical line and the curve is selected as the etching start point of the first interlayer insulating layer 41. The abscissa value at point A differs from the lowest point of the curve by 2-3, and the slope at point A is 0.05, at which point the curve begins to rise. Choosing point A as the etching start point of the first interlayer insulating layer 41 allows for rapid judgment of the etching process within a reasonable error range through the slope, thereby enabling control of the etching process.

[0042] The etching depth of the main etching is 400-900nm. After the main etching is completed, the remaining etching depth for forming vias is 50-250nm. Due to the difference in etching uniformity in different regions of the film, that is, there are local areas with large etching amount and depth, and local areas with small etching amount and etching residue, when the main etching is finished, the second interlayer insulating layer 42 forming vias is basically etched, while only local areas are etched to the first interlayer insulating layer 41, and there are also local areas where etching reaches the gate insulating layer 3. That is, the main etching completes the etching of the second interlayer insulating layer 42 and the partial etching of the first interlayer insulating layer 41 and the gate insulating layer 3.

[0043] S102 second etching gas performs the first step of over-etching on the first interlayer insulating layer and the gate insulating layer;

[0044] Because the thickness of the remaining insulating layer in the hole varies greatly after the main etching is completed, the etching process is switched to over-etching before the main etching reaches the PSI.

[0045] In the first etching step, Ar, H2, and C2HF5 are used as the second etching gases. The flow rate of C2HF5 is 30-100 sccm, the flow rate of H2 is 30-100 sccm, the flow rate of Ar is 200-500 sccm, the chamber pressure is 1-3 Pa, the source RF power is 3000-6000 W, and the bias RF power is 3000-6000 W.

[0046] C2HF5 provides the etching ion source. The C2HF5 flow rate is in the range of 30-100 sccm. The C2HF5 flow rate is positively correlated with the etching rate, that is, the higher the C2HF5 flow rate, the faster the etching rate. When the C2HF5 flow rate is greater than 100 sccm, the effect of increasing the C2HF5 flow rate on promoting the etching rate is no longer significant. That is, the C2HF5 flow rate has reached the threshold at 100 sccm. Continuing to increase the C2HF5 flow rate will result in waste and increase costs. When the C2HF5 flow rate is less than 30 sccm, the etching speed is slow, which increases the time cost of the first step of etching.

[0047] Hydrogen gas can improve the oxide / silicon etching selectivity during the etching process, preventing severe over-etching or etch-through of the PSI. The H2 flow rate is 30-100 sccm; when the H2 flow rate exceeds 100 sccm, it will accelerate the etching process. CF x The deposition of H2 accelerates the occurrence of etching interruptions; that is, an H2 flow rate greater than 100 sccm will reduce the etching rate. When the H2 flow rate is less than 30 sccm, the improvement effect on the oxide / silicon etching selectivity is not significant. SiN in gate insulating layer 3 x Gate insulating layer 32 is the upper layer and SiO x Gate insulating layer 31 is the lower layer, SiO xThe gate insulating layer 31 is in contact with the PSI. The H2 flow rate is within 30-100 sccm, which can ensure the etching amount of the gate insulating layer 3 during the over-etching process, and reduce the etching rate of the second etching gas on the PSI during the over-etching process. That is, it effectively improves the oxide / silicon etching selectivity and avoids severe over-etching or etch-through of the PSI.

[0048] Argon is added to ensure a more uniform mixing of the etching components and to act as a buffer to prevent excessively rapid local etching rates. The Ar flow rate is 200-500 sccm; within this range, argon can effectively adjust the etching rate, which is beneficial for achieving the desired etching effect.

[0049] Pressure affects the concentrations of Ar, H2, and C2HF5, which in turn affects the etching rate and etching uniformity. The chamber pressure is 1-3 Pa. Within this range, the etching rate, depth, and uniformity of the first over-etching process on the first interlayer insulating layer 41 and the gate insulating layer 3 can be effectively controlled, ensuring the etching effect of the first over-etching.

[0050] Power is a factor affecting the etching rate selectivity. The source RF power is 3000-6000W, and the bias RF power is 3000-6000W. When the source RF power and bias RF power are within the above range, the etching rate selectivity is high, that is, the longitudinal etching rate is greater than the transverse etching rate. This is beneficial for controlling the aperture and the slope of the borehole. At the same time, the above power settings will not exceed the bearing capacity of the instrument and equipment, and etching can be performed on aging equipment.

[0051] The inventors discovered that the etching time for the first step of over-etching is 30-50 seconds. When the over-etching time is greater than 50 seconds, the fluorocarbon polymer is deposited on the gate insulating layer 3 inside the hole, and the deposit will cause the etching to be interrupted. Increasing the etching time will not have an etching effect on the bottom of the hole.

[0052] The etching depth of the first step is 30-150nm. In the first step, by controlling the gas flow rate, pressure and power, the first step etching process can accurately etch the first interlayer insulating layer 41 and the gate insulating layer 3, improve the accuracy of the etching position and depth, facilitate the control of the etching process, and avoid over-etching, which may cause severe over-etching of the PSI or etch through the PSI. After the first step etching is completed, the remaining etching depth is 10-100nm. At this time, the first interlayer insulating layer 41 is etched and the gate insulating layer 3 is partially etched.

[0053] S103 Low-Temperature Oxygen Plasma Removal of Deposits CF x ;

[0054] Low-temperature oxygen plasma ashing to remove CF deposits xDuring the low-temperature oxygen plasma ashing process, the O2 flow rate is 700-1000 sccm, the chamber pressure is 3-5 Pa, and the source RF power is 700-1500 W.

[0055] An O2 flow rate of 700-1000 sccm ensures sufficient oxygen ions to react with the deposits and completely remove them. When the O2 flow rate is less than 700 sccm, the deposit removal time is longer; when the O2 flow rate equals 1000 sccm, the maximum threshold for complete deposit removal has been reached. A pressure range of 3-5 Pa and a source RF power range of 700-1500 W ensure low-temperature oxygen plasma ashing for the removal of deposits (CF). x The effect.

[0056] The principle of low-temperature oxygen plasma ashing is that under the action of a high-frequency electric field, oxygen at low pressure generates oxygen plasma with strong oxidizing ability through gas discharge. This plasma can oxidize and decompose organic matter at relatively low temperatures. In the first etching step, for example, the reaction C2HF5→CF... x + As shown in +HF, C2HF5 readily decomposes to form sedimentary CF. x The deposit will be deposited and cover the gate insulating layer 3, preventing the first step of over-etching from proceeding. The deposit is removed by low-temperature oxygen plasma ashing. After low-temperature oxygen plasma ashing, oxygen ions react completely with the deposit, ensuring that the next etching reaction can continue and increasing the etching depth. In addition, this step is performed in the existing equipment without the need for additional reaction equipment, making the operation simple and the process simplified, thus avoiding increased production costs.

[0057] The ashing of low-temperature oxygen plasma was monitored using emission spectroscopy. The endpoint of the ashing process was defined as the point at which the luminescence intensity of fluorine no longer changed. Figure 4 As shown, in the emission spectrum, the intersection point B of the vertical line and the curve is the endpoint of the low-temperature oxygen plasma ashing step. The low-temperature oxygen plasma ashing process mainly monitors the fluorine element. The low-temperature oxygen plasma ashing time is based on the complete reaction of the fluorocarbon polymer. After the fluorocarbon polymer has completely reacted, the luminescence intensity of the fluorine element remains basically unchanged.

[0058] The second etching gas S104 performs a second-step over-etching of the gate insulating layer to form vias.

[0059] In the second etching step, Ar, H2, and C2HF5 are used as the second etching gases. The flow rate of C2HF5 is 30-100 sccm, the flow rate of H2 is 30-100 sccm, and the flow rate of Ar is 200-500 sccm. The chamber pressure is 1-3 Pa, the source RF power is 3000-6000 W, and the bias RF power is 3000-6000 W. After removing the deposits by low-temperature oxygen plasma ashing, the gate insulating layer 3 continues to be etched. This ensures the etching effect while avoiding severe PSI over-etching. The etching time for the second etching step is 30-50 s. Within this time, the etching depth of the second etching step is 30-150 nm. After the second etching step completes the etching of the remaining gate insulating layer 3, the PSI over-etching depth is 0-20 nm. Although the PSI is etched, the etching amount is small, and the second etching step has little impact on the uniformity of the PSI film thickness, thus avoiding MURA (mullage irradiation).

[0060] The dry etching process for vias is carried out in a process chamber. The temperature of the upper part of the process chamber is 80°C, the sidewalls are 80°C, and the stage holding the glass substrate is 0°C. The formation of film thickness uniformity is controlled by the film deposition process, and the dry etching process will disrupt the film thickness uniformity. When the stage temperature is 0°C, the low temperature is beneficial for controlling the etching rate, making it easier to control the etching process and reducing the degree of damage to film thickness uniformity caused by the dry etching process. Byproducts are generated during the etching process. Setting the temperature of the upper part and sidewalls of the chamber to 80°C helps to reduce the deposition of byproducts, thereby achieving the purpose of cleaning the chamber environment.

[0061] This invention, based on the main etching and first-step over-etching, adds low-temperature oxygen plasma ashing and a second-step over-etching. Its advantages are: 1. By controlling the gas flow rate, pressure, and power in the main etching and first-step over-etching processes, the etching process is effectively controlled, allowing the main etching process to etch ILD2, ILD1, and GI, while the first-step over-etching process precisely etches the remaining ILD1 and GI, improving the accuracy of the etching position and depth; 2. Low-temperature oxygen plasma ashing is used in existing equipment to remove deposited CF. x This promotes the continuous etching reaction, increases the etching rate, and ensures the etching effect; 3. The setting of process parameters in the over-etching process effectively improves the oxide / silicon etching selectivity ratio in GI, controls the etching accuracy, avoids severe PSI over-etching or etching through, ensures the uniformity of PSI film thickness at the via, eliminates MURA, and improves product yield.

[0062] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for via dry etching, characterized in that, The film layer and etching sequence of forming via hole are second interlayer insulating layer, first interlayer insulating layer and gate insulating layer from top to bottom, the second interlayer insulating layer is composed of SiO x , the first interlayer insulating layer is composed of SiN x , the gate insulating layer includes SiN x gate insulating layer and SiO x gate insulating layer, the SiN x gate insulating layer in the gate insulating layer is the upper layer and the SiO x gate insulating layer is the lower layer, the SiO x gate insulating layer is in contact with the low temperature polysilicon layer; the method comprises the following steps: S101, the first etching gas is used to etch the gate insulating layer and the first interlayer insulating layer and the second interlayer insulating layer above the gate insulating layer, the first etching gas includes O2 and CF4, the main etching is monitored by using emission spectroscopy, and the SiN x product CN generated by the reaction of O2 and CF4 x is monitored, and the minimum point of the luminescence intensity of the CN x on the emission spectrum is added by 2-3 to obtain the etching starting point of the first interlayer insulating layer, and the minimum point is added by 32-63 to obtain the ending point of the main etching, and the horizontal coordinate of the ending point is the main etching time. S102, the second etching gas performs the first step of over-etching on the first interlayer insulating layer and the gate insulating layer. The second etching gas includes Ar, H2, and C2HF5. During the etching process of the first interlayer insulating layer and the gate insulating layer, C2HF5 reacts to generate CF. x The CF x Deposition on the gate insulating layer within the hole causes etching interruption; S103, low temperature oxygen plasma removes deposits CF x The process of removing the CFx by low temperature oxygen plasma is monitored by emission spectroscopy. S104, a second etching gas is used to perform a second step over-etching on the gate insulating layer to form a via to expose the low-temperature polysilicon layer; the etching depth of the main etching is 400-900nm, and the remaining etching depth after the main etching is completed is in the range of 50-250nm, the first etching gas satisfies: the CF4 flow rate is 300-600sccm, the O2 flow rate is 30-100sccm, the chamber pressure is 1-3Pa, the source RF power is 7000-9500W, and the bias RF power is 2000-4000W; the etching time of the first step over-etching is 30-50s, and the etching depth is 30-150nm, and the remaining etching depth after the first step over-etching is completed is in the range of 10-100nm, the second etching gas satisfies: the C2HF5 flow rate is 30-100sccm, the H2 flow rate is 30-100sccm, the Ar flow rate is 200-500sccm, the chamber pressure is 1-3Pa, the source RF power is 3000-6000W, and the bias RF power is 3000-6000W; removing the CF x During the process, the O2 flow rate is 700-1000 sccm, the chamber pressure is 3-5 Pa, and the source RF power is 700-1500 W. the etching time of the second step over-etching is 30-50s, and the etching depth is 30-150nm, and the low-temperature polysilicon layer over-etching depth after the second step over-etching is completed is 0-20nm.

2. The method of via dry etching according to claim 1, wherein, The via dry etching process is performed in a process chamber, the upper temperature of the process chamber is 80℃, the sidewall temperature is 80℃, and the temperature of the platen for holding the glass substrate is 0℃.

Images