Method for manufacturing wafer-level chip scale package (WLCSP)

Abstract

The present disclosure relates to a method for manufacturing a wafer-level chip scale package (WLCSP). Open trenches are formed that extend downward from the top surface of a production wafer through a scribe region to a depth that only partially penetrates a semiconductor substrate. Before performing a bumping process, a first handle is attached to the top surface of the production wafer. Then, the back surface of the semiconductor substrate is thinned to reach the trenches and form a wafer-level chip scale package at each integrated circuit location defined by the trenches. Then, a second handle is attached to the bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose under-bump metallization pads at the top surface. Then, a bumping process is performed to form solder balls at each exposed under-bump metallization pad.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 094,424, filed on October 21, 2020, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention generally relates to a method for manufacturing an integrated circuit package, and more particularly, to a method for manufacturing a wafer-level chip-scale package (WLCSP). BACKGROUND OF THE INVENTION

[0004] REFERENCE Figure 1 , Figure 1 FIG. 1 schematically shows (not necessarily to scale) a cross-section of a wafer-level chip-scale package (WLCSP) 10, which includes a semiconductor substrate 12 having a top surface 14, a bottom surface 16, and a thickness 18. For example, the semiconductor substrate 12 may include a bulk substrate or a semiconductor-on-insulator (SOI) substrate. An integrated circuit device 20 is disposed on the top surface 14 of the semiconductor substrate 12 and below the top surface (e.g., the integrated circuit device includes doped regions within the substrate, transistor gate structures, and metal contacts above the substrate). At the top surface 14 of the semiconductor substrate 12, a pre-metalization dielectric (PMD) layer covers the integrated circuit device 20. An interconnect structure 22 formed of multiple metallization layers (as known in the art, including wires, vias, and bond pads 26 located within an insulating material) is disposed on top of the PMD layer and is configured to electrically interconnect the integrated circuit device 20. A passivation layer 24 having an opening exposing the bond pads 26 is disposed on top of the topmost layer of the interconnect structure 22. The overall structure from the bottom surface 16 of the substrate 12 to the passivation layer having the exposed bond pads 26 is known in the art as a semiconductor die 28. The package 10 further includes a redistribution layer (RDL), which is also known in the art as an interposer, to provide electrical connection lines between the bond pads 26 of the die 28 and the under-bump metallization (UBM) pads 30 for the package. A passivation layer 32 above the redistribution layer RDL includes an opening exposing the UBM pads 30. Solder balls 34 are mounted to each UBM pad 30. Generally, in a common implementation, the thickness of the balls 34 is less than the thickness 18 of the substrate 12 (and more specifically, the thickness of the substrate 12 is approximately twice the thickness of the balls 34).

[0005] In many space-sensitive applications, it is crucial that the total thickness of the packaged integrated circuit be as thin as possible. Therefore, the industry is making efforts to reduce the total thickness of the wafer-level chip-scale package 10 by reducing the thickness 18 of the semiconductor substrate 12. This is as Figure 2As shown. For example, in a common embodiment, the thickness of the ball 34 is greater than the thickness 18. However, one problem with reducing the thickness of the substrate 12 is that cracks 40 will form in the die 28 at the location where the solder balls are attached.

[0006] There is a need in the art for a process or method for manufacturing wafer-level chip scale packages (WLCSPs) that support the use of thinned semiconductor substrates 12. SUMMARY OF THE INVENTION

[0007] In one embodiment, a process includes: producing a front-end-of-line (FEOL) substrate wafer that includes a semiconductor substrate wafer having a first thickness and a back surface and a pre-metalization dielectric layer; producing a back-end-of-line (BEOL) structure over the pre-metalization dielectric layer, the BEOL structure including a first passivation layer that includes openings for bond pads; forming a redistribution layer over the first passivation layer, wherein the redistribution layer electrically connects the bond pads to under-bump metallization pads; forming a second passivation layer that includes openings for the under-bump metallization pads and thereby manufacturing a production wafer; opening trenches that extend from the top surface of the production wafer downward to a depth that only partially penetrates the semiconductor substrate wafer; attaching a first handle to the top surface of the production wafer prior to performing a bumping process at the under-bump metallization pads; thinning from the first thickness to a second thickness at the back surface of the semiconductor substrate wafer to reach the trenches and form a plurality of wafer-level chip scale packages; attaching a second handle to the bottom surface of the plurality of wafer-level chip scale packages; removing the first handle to expose the under-bump metallization pads; and performing the bumping process to form solder balls at each exposed under-bump metallization pad.

[0008] In one embodiment, a process includes: opening trenches that extend from the top surface of a production wafer downward through a scribe region to a depth that only partially penetrates the semiconductor substrate, the trenches defining integrated circuit locations; attaching a first handle to the top surface of the production wafer prior to performing a bumping process; thinning at the back surface of the semiconductor substrate to reach the trenches and form a wafer-level chip scale package at each integrated circuit location; attaching a second handle to the bottom surface of the thinned semiconductor substrate for the wafer-level chip scale package; removing the first handle to expose the under-bump metallization pads at the top surface; and performing the bumping process to form solder balls at each exposed under-bump metallization pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To better understand the embodiments, reference is now made, by way of example only, to the accompanying drawings, in which:

[0010] Figure 1 and Figure 2shows a schematic cross-section of a wafer-level chip scale package (WLCSP); and

[0011] Figures 3A - 3H shows steps in a method for manufacturing a wafer-level chip scale package (WLCSP). DETAILED DESCRIPTION

[0012] Reference is now made to Figures 3A - 3H , which shows steps in a method for manufacturing a wafer-level chip scale package (WLCSP). These steps are shown using cross-sectional views. It should be noted that although the proportional relationships between specific structures (as described herein) are shown with a certain degree of precision, they need not be drawn to scale. For the preferred embodiment, Figures 3A - 3H the process steps are shown in sequence.

[0013] Figure 3A shows a semiconductor substrate wafer 112 having a top surface 114, a bottom surface 116, and a thickness 118. The semiconductor substrate wafer 112 includes a plurality of integrated circuit locations 120 defined by scribe (or cut) regions 122. For example, the semiconductor substrate wafer 112 may include a bulk substrate wafer or a semiconductor-on-insulator (SOI) substrate wafer. Each integrated circuit location 120 includes integrated circuit devices 124 (e.g., the integrated circuit devices include doped regions within the substrate, transistor gate structures, and metal contacts above the substrate) disposed on and below the top surface 114 of the semiconductor substrate wafer 112. At the top surface 114 of the semiconductor substrate wafer 112, a pre-metal dielectric (PMD) layer covers the integrated circuit devices 124. The process for forming Figure 3A the structure shown is generally referred to in the art as a front-end-of-line (FEOL) process, which produces a corresponding FEOL wafer 130.

[0014] Figure 3B shows the result of further wafer-size processing performed on the FEOL wafer 130, wherein an interconnect structure 132 formed of a plurality of metallization layers (as known in the art, including wires, vias, and bond pads 136 located within insulating materials) is disposed on top of the PMD layer. The wires and vias are configured to electrically interconnect the integrated circuit devices 124. A passivation layer 134 having an opening exposing the bond pads 136 is disposed on top of the topmost layer of the interconnect structure 132. The process for forming Figure 3B the additional structure shown on top of the FEOL wafer 130 is generally referred to in the art as a back-end-of-line (BEOL) process, which produces a corresponding BEOL wafer 140.

[0015] Figure 3CShows the results of further wafer - sizing processing performed on the BEOL wafer 140, where a redistribution layer (RDL) (also known as an interposer in the art) is added using a conventional RDL deposition process to provide electrical connection lines between the bond pads 136 and the under - bump metallization (UBM) pads 144. Then, a passivation layer 146 is deposited over the redistribution layer RDL and is configured to include an opening that exposes the UBM pad 144. A process for forming the Figure 3C additional structures shown fabricates the production wafer 150.

[0016] Then, the following steps are performed on the production wafer 150. Next, starting from the top surface 154 of the production wafer 150, trenches 156 are cut into the production wafer 150 at the location of each scribe (or cut) region 122 to complete a partial cut of the production wafer 150. The result is as Figure 3D shown. A mechanical cutting process can be used to form the trenches 156. In this process step, a mechanical cutting tool with the ability to achieve a precise partial depth through the substrate 12 is used for cutting. Controlling the cutting depth is crucial. The trenches 156 have a depth that starts from the top surface 154 and extends completely through the passivation layer 146, the redistribution layer RDL, the passivation layer 134, the interconnect structure 132, and the pre - metallization dielectric PMD layer. The trenches 156 further extend only partially into the semiconductor substrate wafer 112 to a depth “D” that is at least and more preferably greater than the final desired thickness of the semiconductor substrate for a wafer - level chip - scale package (WLCSP), but not greater than the thickness of the semiconductor substrate wafer 112.

[0017] A glass support wafer 160 (also known as a glass handle) is bonded to the top surface 154 of the production wafer 150. The support wafer 160 with adhesion is bonded to the surface 154 through a lamination process. The result is as Figure 3E shown.

[0018] Then, substrate back - side thinning is performed at the bottom surface 116 of the semiconductor substrate wafer 112 to reduce the thickness 118 to a thinned thickness 118’, substantially completing the cut of the production wafer 150 at the locations defined by the trenches 156 and fabricating wafer - level chip - scale packages 165 at each integrated circuit location 120. In a preferred embodiment, this thinning is performed by mechanical back - side grinding using a grinding wheel. Alternatively, a suitable mechanical / chemical process can be used. The wafer - level chip - scale packages 165 are held in relative positions to each other at the integrated circuit locations 120 through their attachment to the glass support wafer 160 on their positive sides. The result is as Figure 3F shown.

[0019] Then, another support wafer 170 (also referred to as a handle) is bonded to the bottom surface 116’ of the wafer - level chip - scale package 165. The support wafer 170 with adhesion is bonded to the surface 116’ through a lamination process. In one embodiment, the another support wafer can be made of glass. It is crucial that the material of the another support wafer 170 is heat - resistant to at least the temperature (e.g., at least 200 °C) used for solder reflow (explained further below). After bonding the glass support wafer 170 on the back side, a cleaning process for each wafer - level chip - scale package 165 is used to disconnect the glass support wafer 160 on the front side from the top surface 154 of the passivation layer 146. The result is as Figure 3G shown.

[0020] Next, for each wafer - level chip - scale package 165, a bumping process is performed at the top surface 154 (i.e., at the top surface of the passivation layer 146), and solder is dropped on each UBM pad 144. After dropping the solder, a heat treatment is performed at a certain temperature (e.g., approximately 200 °C) to melt and reflow the deposited solder, and then it is cooled to form solder balls 180 at each UBM pad 144. The result is as Figure 3H shown. It should be noted that the thicknesses of the structures 146, RDL, 134, 132, PMD are magnified in size relative to the size of the substrate 112’ and the balls 180. The general size relationship between the substrate 112' and the balls 180 is shown more precisely.

[0021] Then, the wafer - level chip - scale package 165 is removed from the support wafer 170. A non - eject tape - and - reel (TnR) process well - known to those skilled in the art can be used for this removal. This process is a standard WLCSP process for picking up individual die cut from a wafer and placing them into corresponding carrier tape pockets, and then winding the carrier tape onto an industry - standard reel.

[0022] Figures 3A - 3H The process shown has many advantages compared to traditional processes where back - grinding of a semiconductor substrate wafer is performed after the bumping process (e.g., see U.S. Patent No. 9,466,585 to Kamphuis and U.S. Patent Application Publication No. 2019 / 0172814 to Kim). These prior - art processes involve a significant risk of substrate cracking. However, in Figures 3A - 3H the process, the bumping process advantageously occurs after thinning of the semiconductor substrate wafer, thus minimizing (if not eliminating) the risk of cracking. Additionally, Figures 3A - 3H the process performs partial cutting of the semiconductor substrate wafer before performing the back - thinning and front - side bumping operations to allow the use of a support handle directly attached to the front side for back - grinding without intervening solder bumps.

[0023] Although the present invention has been described in detail in the drawings and the foregoing description, such description and illustration are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A method for manufacturing a wafer - level chip - scale package, comprising: producing a front - end - of - line (FEOL) substrate wafer, the FEOL substrate wafer including a semiconductor substrate wafer having a first thickness and a back surface, and a pre - metallization dielectric layer; producing a back - end - of - line (BEOL) structure over the pre - metallization dielectric layer, the BEOL structure including a first passivation layer, the first passivation layer including an opening for a bonding pad; forming a redistribution layer over the first passivation layer, wherein the redistribution layer electrically connects the bonding pad to an under - bump metallization (UBM) pad; forming a second passivation layer, the second passivation layer including an opening for the under - bump metallization pad, and thereby manufacturing a production wafer; opening trenches extending from the top surface of the production wafer downward to a depth that only partially penetrates the semiconductor substrate wafer; attaching a first handle to the top surface of the production wafer before performing a bumping process at the under - bump metallization pads; thinning the semiconductor substrate wafer of the production wafer at the back surface from the first thickness to a second thickness, reaching the trenches and forming a plurality of wafer - level chip - scale packages; attaching a second handle to the bottom surface of the plurality of wafer - level chip - scale packages; removing the first handle to expose the under - bump metallization pads; and performing the bumping process to form solder balls at each exposed under - bump metallization pad, wherein the first handle is a first support wafer, and the second handle is a second support wafer.

2. The method according to claim 1, wherein the second handle is made of a material that is heat - resistant to the temperature of the heat reflow performed during the bumping process.

3. The method according to claim 2, wherein the temperature is at least 200 °C.

4. The method according to claim 1, further comprising: performing a non - eject tape - and - reel process to remove individual wafer - level chip - scale packages from the second handle.

5. The method according to claim 1, wherein the second handle is made of a glass material.

6. The method according to claim 1, wherein the first handle is made of a glass material.

7. The method according to claim 1, wherein attaching the first handle to the top surface of the production wafer comprises: performing lamination.

8. The method according to claim 1, wherein attaching the second handle to the bottom surface of the plurality of wafer - level chip - scale packages comprises: performing lamination.

9. The method according to claim 1, wherein attaching the first handle comprises: directly bonding the first handle to the surface of the second passivation layer.

10. A method for manufacturing a wafer - level chip - scale package, comprising: opening trenches extending from the top surface of a production wafer downward through a scribe region to a depth that only partially penetrates the semiconductor substrate, the trenches defining integrated circuit locations; attaching a first handle to the top surface of the production wafer before performing a bumping process; thinning at the back surface of the semiconductor substrate to reach the trenches and forming a wafer - level chip - scale package at each integrated circuit location; Attach a second handle to the bottom surface of the thinned semiconductor substrate for the wafer - level chip - scale package; Remove the first handle to expose the under - bump metallization pads at the top surface; And Perform the bumping process to form solder balls at each exposed under - bump metallization pad, wherein the first handle is a first support wafer and the second handle is a second support wafer.

11. The method according to claim 10, further comprising: Before the opening step, manufacture the production wafer by the following steps: Perform a front - end - of - line (FEOL) process; Perform a back - end - of - line (BEOL) process; Form a redistribution layer that electrically connects the bonding pads produced in the BEOL process to the under - bump metallization pads; And Form a passivation layer that includes openings for the under - bump metallization pads.

12. The method according to claim 11, wherein the second handle is made of a material that is heat - resistant to the temperature of the heat reflow performed during the bumping process.

13. The method according to claim 12, wherein the temperature is at least 200 °C.

14. The method according to claim 11, wherein attaching the first handle includes directly attaching the first handle to the surface of the passivation layer.

15. The method according to claim 10, further comprising: Perform a non - eject tape - and - reel process to remove individual wafer - level chip - scale packages from the second handle.

16. The method according to claim 10, wherein the second handle is made of a glass material.

17. The method according to claim 10, wherein the first handle is made of a glass material.

18. The method according to claim 10, wherein attaching the first handle to the top surface of the production wafer comprises: Perform lamination.

19. The method according to claim 10, wherein attaching the second handle to the bottom surface of the thinned semiconductor substrate for the wafer - level chip - scale package comprises: Perform lamination.

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