Batch wafer processing method, etching system and storage medium

Abstract

The present application discloses a method for processing batch wafers, an etching system and a storage medium, and belongs to the field of semiconductor processing technology. The method includes: before processing the batch wafers, using a waferless cleaning baseline to perform waferless cleaning on the chamber of the reaction chamber, etching the first product wafer in the batch wafers after cleaning and detecting whether the process performance meets the process specifications; if not, adjusting the cleaning intensity of the waferless cleaning baseline, using the adjusted waferless cleaning baseline to perform waferless cleaning on the chamber, etching the second product wafer and detecting whether the process performance meets the process specifications; if it meets, etching the batch wafers in sequence according to the adjusted waferless cleaning baseline. In this way, the waferless cleaning intensity can be optimized in advance, so that the optimized waferless cleaning can balance the polymer deposition in the chamber, and the polymer state remains stable during the batch wafer processing, reducing the impact on the etching rate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular to a batch wafer processing method, an etching system, and a storage medium. Background Art

[0002] In the field of semiconductor processing technology, to improve processing efficiency, the same etching process is often used to continuously process batches of wafers. The etching process can be a light polymerization etching process or a heavy polymerization etching process. A light polymerization etching process is one that does not produce polymer deposition during the processing, or produces less polymer deposition and has no impact on process performance. A heavy polymerization etching process is one that produces more polymer deposition during the processing, which can affect process performance. A typical heavy polymerization etching process is the Bosch process.

[0003] Since polymer deposition will occur on the walls of the reaction chamber during the process of processing wafers using the heavy polymerization etching process, if too much polymer is deposited, it will seriously affect the process performance of subsequent wafers. Therefore, in the continuous processing of various batches of wafers, before etching the wafers in the batch, a unified waferless cleaning baseline process is used to clean the chamber of the reaction chamber without wafers. After the waferless cleaning, the wafers are placed in the reaction chamber for processing.

[0004] However, during the continuous processing of batch wafers, the polymer deposition state may change according to the changes in the etching process, process time or chamber conditions. Therefore, if a unified waferless cleaning baseline is used for waferless cleaning, the state of the polymer deposited in the chamber after cleaning may be inconsistent, resulting in a drift in the etching rate of the continuously processed batch wafers, and further resulting in substandard products in the reaction chamber. Summary of the Invention

[0005] This application provides a batch wafer processing method, etching system, and storage medium that can solve the problem in related technologies where the inconsistent state of polymer deposited in the chamber causes the etching rate of continuously processed batch wafers to drift, thereby resulting in substandard products in the reaction chamber. The technical solution is as follows:

[0006] In a first aspect, a method for processing batch wafers is provided, the method comprising:

[0007] Perform chamber adjustment on the reaction chamber and calibrate the process parameters of the etching process;

[0008] performing waferless cleaning on a chamber of the reaction chamber using a waferless cleaning baseline, etching a first product wafer in the batch of wafers after the waferless cleaning, and detecting whether process performance of etching the first product wafer meets process specifications;

[0009] If the process performance of etching the first product wafer does not meet the process specification, adjusting the cleaning intensity of the waferless cleaning baseline;

[0010] performing waferless cleaning on a chamber of the reaction chamber using the adjusted waferless cleaning baseline, etching a second product wafer of the batch of wafers after the waferless cleaning, and detecting whether process performance of etching the second product wafer meets process specifications;

[0011] If the process performance of etching the second product wafer meets the process specification, the unprocessed product wafers in the batch of wafers are sequentially etched according to the adjusted waferless cleaning baseline.

[0012] Optionally, if the process performance of etching the second product wafer meets the process specification, etching unprocessed product wafers in the batch of wafers sequentially according to the adjusted wafer-free cleaning baseline includes:

[0013] If the process performance of etching the second product wafer meets the process specification, performing waferless cleaning on the chamber of the reaction chamber using the adjusted waferless cleaning baseline, timing the third product wafer in the batch of wafers after the waferless cleaning, and detecting whether the process performance of etching the third product wafer meets the process specification;

[0014] If the process performance of etching the third product wafer meets the process specification, the unprocessed product wafers in the batch of wafers are sequentially etched according to the adjusted wafer-free cleaning baseline.

[0015] Optionally, after detecting whether the process performance of etching the second product wafer meets the process specification, the method further includes:

[0016] If the process performance of etching the second product wafer does not meet the process specification, the second product wafer is used as the target product wafer, the adjusted waferless cleaning baseline is used as the target waferless cleaning baseline, and the cleaning intensity of the target waferless cleaning baseline is adjusted;

[0017] performing waferless cleaning on a chamber of the reaction chamber using the adjusted target waferless cleaning baseline, etching a product wafer subsequent to the target product wafer as the target product wafer after the waferless cleaning, and detecting whether process performance of etching the target process wafer meets process specifications;

[0018] If the process performance of etching the target processed wafer meets the process specification, etching the unprocessed product wafers in the batch of wafers sequentially according to the adjusted target wafer-free cleaning baseline;

[0019] If the process performance of etching the target processed wafer does not meet the process specifications, the adjusted target waferless cleaning baseline will be used as the target waferless cleaning baseline, and the process will return to the step of adjusting the cleaning intensity of the target waferless cleaning baseline until the chamber of the reaction chamber is waferless cleaned according to the adjusted target waferless cleaning baseline, and after the process performance of etching the next product wafer of the target product wafer meets the process specifications, the unprocessed product wafers in the batch of wafers will be etched in sequence according to the adjusted waferless cleaning baseline.

[0020] Optionally, the adjusting the cleaning intensity of the waferless cleaning baseline includes one or more of the following methods:

[0021] adjusting a cleaning recipe of the waferless cleaning baseline;

[0022] Adjusting the cleaning time of the waferless cleaning baseline;

[0023] Adjusting the radio frequency performance or microwave performance of the waferless cleaning baseline;

[0024] adjusting the gas pressure of the waferless cleaning baseline;

[0025] The gas flow rate of the waferless cleaning baseline is adjusted.

[0026] Optionally, adjusting the cleaning recipe of the waferless cleaning baseline includes:

[0027] If the etching depth of the first product wafer is greater than the etching depth specification, adjusting the first cleaning recipe of the waferless cleaning baseline to a second cleaning recipe, wherein the cleaning intensity of the second cleaning recipe is less than the cleaning intensity of the first cleaning recipe;

[0028] If the etching depth of the first product wafer is less than the etching depth specification, the first cleaning recipe of the waferless cleaning baseline is adjusted to a third cleaning recipe, and the cleaning intensity of the third cleaning recipe is greater than the cleaning intensity of the first cleaning recipe.

[0029] Optionally, adjusting the cleaning time of the waferless cleaning baseline includes:

[0030] According to the correspondence between the process duration of wafer processing and the waferless cleaning time, the cleaning time of the waferless cleaning baseline is adjusted to the waferless cleaning time corresponding to the process duration of the continuous processing of the batch wafers.

[0031] Optionally, the correspondence between the process time of the wafer processing and the waferless cleaning time is obtained in advance based on statistics of different process times of sample product wafer processing and corresponding saturated cleaning times. The saturated cleaning time refers to the cleaning time when waferless cleaning is performed according to the same waferless cleaning formula so that the polymer state deposited on the sample product wafer under the corresponding process time is in a saturated state.

[0032] Optionally, etching unprocessed product wafers in the batch of wafers in sequence according to the adjusted wafer-free cleaning baseline includes:

[0033] For the first product wafer among the unprocessed product wafers in the batch of wafers, after processing of the previous product wafer of the first product wafer is completed, the chamber of the reaction chamber is waferless cleaned using the adjusted waferless cleaning baseline, and the first product wafer is etched after the waferless cleaning, and the first product wafer is any one of the unprocessed product wafers.

[0034] Optionally, the performing chamber adjustment on the reaction chamber and verifying process parameters of the etching process include:

[0035] When a first silicon wafer is placed in the chamber of the reaction chamber, cleaning the chamber of the reaction chamber using a chamber cleaning baseline;

[0036] processing at least one first conditioning wafer to perform chamber conditioning on the reaction chamber;

[0037] Performing each process step of the repolymerization etching process baseline on the second silicon wafer to verify the process parameters of each step in the repolymerization etching process baseline;

[0038] The patterned wafer is etched according to the re-polymerization etch process baseline to verify the process parameters of the re-polymerization etch process baseline.

[0039] Optionally, the repolymerization etching process baseline is a Bosch process baseline, and performing each process step of the repolymerization etching process baseline on the second silicon wafer to verify the process parameters of each step in the repolymerization etching process baseline includes:

[0040] performing polymer deposition on the second silicon wafer to verify the deposition rate and uniformity of the polymer deposition step;

[0041] performing isotropic etching on the second silicon wafer after polymer deposition to verify the etching rate and uniformity of the isotropic etching step;

[0042] The second silicon wafer after polymer deposition was unidirectionally etched to verify the etching rate and uniformity of the unidirectional etching step.

[0043] Optionally, etching the patterned wafer according to the re-polymerization etching process baseline to verify process parameters of the re-polymerization etching process baseline includes:

[0044] Etch patterned or structured wafers according to the re-polymerization etch process baseline to verify the etch depth, size, profile, striations, surface roughness, and residue of the re-polymerization etch process.

[0045] Optionally, the etching process for the batch wafers adopts a heavy polymerization etching process.

[0046] Optionally, the repolymerization etching process is a Bosch process.

[0047] Optionally, the method further includes:

[0048] If the etching process for the batch wafers adopts a light polymer etching process, the chamber of the reaction chamber is cleaned using a chamber cleaning baseline when a third silicon wafer is placed in the chamber of the reaction chamber;

[0049] processing at least one second conditioning wafer to perform chamber conditioning on the reaction chamber;

[0050] Etching the oxide-covered wafer and the patterned wafer according to the light polymer etching process baseline to verify the process parameters of the light polymer etching process baseline;

[0051] The batch of wafers are etched sequentially according to the verified light polymerization etching process baseline.

[0052] Optionally, adjusting the chamber conditions of the reaction chamber includes:

[0053] acquiring an optical emission spectrum from an optical emission spectroscopy system connected to the reaction chamber;

[0054] The chamber conditions of the reaction chamber are adjusted according to the acquired optical emission spectrum.

[0055] Optionally, the continuously etching unprocessed product wafers in the wafer batch according to the adjusted wafer-free cleaning baseline includes:

[0056] acquiring an optical emission spectrum from an optical emission spectroscopy system connected to the reaction chamber;

[0057] The unprocessed product wafers in the batch of wafers are sequentially etched according to the acquired optical emission spectrum and the adjusted wafer-free cleaning baseline.

[0058] In a second aspect, a batch wafer processing apparatus is provided, wherein the batch wafer processing apparatus has the function of implementing the batch wafer processing method described in the first aspect. The batch wafer processing apparatus includes at least one module, wherein the at least one module is configured to implement the batch wafer processing method described in the first aspect.

[0059] In a third aspect, an etching system is provided, comprising a controller, a reaction chamber, a cleaning system, and an etching tool, wherein the controller is connected to the reaction chamber, the cleaning system, and the etching tool, respectively; the cleaning system is used to clean the reaction chamber; the etching tool is used to etch a wafer placed in the reaction chamber; and the controller is used to control the reaction chamber, the cleaning system, and the etching tool, respectively.

[0060] In which, the controller includes a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the computer program is executed by the processor, the etching system implements any one of the batch wafer processing methods described in the first aspect above.

[0061] Optionally, the etching system further comprises an optical emission spectroscopy system, wherein the optical emission spectroscopy system is connected to the controller and the reaction chamber respectively;

[0062] The controller is used to obtain the optical emission spectrum of the reaction chamber from an optical emission spectrum system connected to the reaction chamber, and adjust the chamber conditions of the reaction chamber according to the obtained optical emission spectrum.

[0063] Optionally, the controller is further configured to obtain an optical emission spectrum of the reaction chamber from an optical emission spectroscopy system connected to the reaction chamber, and control the reaction chamber and the etching tool to continuously etch batches of wafers based on the obtained optical emission spectrum.

[0064] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements any one of the batch wafer processing methods described in the first aspect.

[0065] In a fifth aspect, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, any one of the batch wafer processing methods described in the first aspect is implemented.

[0066] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute any one of the batch wafer processing methods described in the first aspect.

[0067] The beneficial effects provided by the embodiments of the present application are:

[0068] In an embodiment of the present application, the chamber of the reaction chamber can be adjusted first, and the process parameters of the etching process can be verified. Then, the chamber of the reaction chamber is cleaned without wafers using the waferless cleaning baseline. After the waferless cleaning, the first product wafer in the batch of wafers is etched, and the process performance of etching the first product wafer is detected to see whether it meets the process specifications. If not, the cleaning intensity of the waferless cleaning baseline is adjusted, and after the chamber of the reaction chamber is cleaned without wafers using the adjusted waferless cleaning baseline, the second product wafer is etched and the etching process performance is detected to see whether it meets the process specifications. If it meets, the unprocessed product wafers in the batch of wafers are etched in sequence according to the adjusted waferless cleaning baseline. In this way, the waferless cleaning intensity can be optimized by pre-etching the product wafers before processing batch wafers, so that the optimized waferless cleaning intensity will not affect the process performance of the product wafers. That is, the optimized waferless cleaning can balance the polymer deposition in the chamber, ensuring that the state of the polymer deposited in the chamber after cleaning remains stable, and will not cause the etching rate of the product wafers to drift, thereby avoiding the production of substandard products. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0070] Figure 1 is a schematic diagram of an etching system provided in an embodiment of the present application;

[0071] Figure 2 is a schematic diagram of another etching system provided in an embodiment of the present application;

[0072] Figure 3This is a flow chart of a batch wafer processing method provided by an embodiment of the present application;

[0073] Figure 4 This is a schematic diagram of the change of the polymer state of a reaction chamber provided in an embodiment of the present application;

[0074] Figure 5 1 is a schematic diagram of the corresponding relationship between the process time of wafer processing and the time without wafer cleaning provided in an embodiment of the present application;

[0075] Figure 6 This is a schematic diagram of a light polymerization process flow and a heavy polymerization etching process flow provided in an embodiment of the present application;

[0076] Figure 7 Schematic diagram of a wafer processing sequence in a light polymerization etching process provided in an embodiment of the present application;

[0077] Figure 8 Schematic diagram of a wafer processing sequence in a repolymerization etching process provided in an embodiment of the present application;

[0078] Figure 9 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0080] It should be understood that the “plurality” mentioned in this application refers to two or more. In the description of this application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of this application, words such as “first” and “second” are used to distinguish between identical or similar items with basically the same functions and effects. Those skilled in the art will understand that words such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not necessarily limit them to be different.

[0081] Before explaining the embodiments of the present application in detail, the application scenarios of the embodiments of the present application are first explained.

[0082] During the continuous processing of batches of wafers, chamber conditions may vary from wafer to wafer. For example, the state of polymer deposited in the chamber may vary from wafer to wafer. This can cause etch rate drift, meaning that the etch rate varies from wafer to wafer, leading to substandard product in the reaction chamber. This phenomenon is common in heavy polymer etch processes, particularly the Bosch process.

[0083] In order to ensure that the chamber conditions remain consistent during the continuous processing of batch wafers, an embodiment of the present application proposes a batch wafer processing method that can optimize the waferless cleaning intensity. By optimizing the waferless cleaning intensity, the two driving forces of polymer generation and removal are balanced to balance the polymer deposition in the etching of product wafers, so that the polymer state in the chamber can be maintained at a stable level during continuous wafer processing, thereby avoiding drift in the etching rate of the product wafers.

[0084] The batch wafer processing method provided in the embodiment of the present application can optimize the wafer-free cleaning intensity and keep the polymer state of the reaction chamber stable with a shorter turnaround time. This method can be logically inserted into various etching process flows. For example, it can be adapted to light polymerization etching processes and heavy polymerization etching processes in semiconductor chip manufacturing. Specifically, it can include: 1. Dielectric etching processes in semiconductor wafer production lines. 2. Silicon etching processes using light polymerization chemistry or heavy polymerization chemistry. 3. Single-step and multi-loop processes (such as Bosch processes). 4. Low aspect ratios of etching depth to line width (such as 2:1) to high aspect ratios (such as 10:1). 5. Through-hole and groove etching patterns. In addition, the technical solutions provided in the embodiment of the present application can be implemented in various semiconductor applications, such as silicon photonics, MEMS (Micro-Electro-Mechanical System), CMOS (Complementary Metal Oxide Semiconductor), and other power device applications such as micro LEDs (Light-Emitting Diodes).

[0085] Next, the implementation environment involved in the embodiments of the present application is introduced.

[0086] Figure 1 FIG. 1 is a schematic diagram of an etching system 100 provided in an embodiment of the present application. The etching system 100 can be used to continuously process batches of wafers. Figure 1 As shown, the etching system 100 includes a controller 10, a reaction chamber 20, a cleaning system 30 and an etching tool 40, and the controller is connected to the reaction chamber 20, the cleaning system 30 and the etching tool 40 respectively.

[0087] The cleaning system 30 is used to clean the reaction chamber 20, for example, to perform wafer-free cleaning on the reaction chamber 20. The etching tool 40 is located in the reaction chamber 20 and is used to etch the wafer placed in the reaction chamber 20. For example, a light polymerization etching process or a heavy polymerization etching process is used to etch the wafer placed in the reaction chamber 20. The controller 10 is used to control the reaction chamber 20, the cleaning system 30, and the etching tool 40 respectively, so as to realize the continuous processing method of batch wafers provided in the embodiment of the present application by controlling the reaction chamber 20, the cleaning system 30, and the etching tool 40.

[0088] In addition, if Figure 1 As shown, the etching system 100 may further include an OES (Optical Emission Spectroscopy) system 50, which is connected to the controller 10 and the reaction chamber 20, respectively. The OES system 50 can assist the etching system 100 in automatically processing batches of wafers continuously, or assist the etching system 100 in automatically adjusting the chamber conditions of the reaction chamber 20.

[0089] For example, the OES system 50 is used to obtain the optical emission spectrum of the reaction chamber 20 and send the obtained optical emission spectrum to the controller 10. The controller 10 adjusts the chamber conditions of the reaction chamber 20 according to the optical emission spectrum sent by the OES system 50, or continuously processes batches of wafers according to the optical emission spectrum sent by the OES system 50.

[0090] As an example, the controller 10 can use an EPD (Endpoint Detection) algorithm to detect the etching process endpoint based on the optical emission spectrum sent by the OES system 50, and control the etching tool 40 to stop the current etching process when the etching endpoint is detected. The EPD algorithm can be a spectral threshold method, an intensity gradient method, or a signal pattern network, etc., which is not limited in the embodiments of the present application. In addition, after the OES system 50 obtains the optical emission spectrum of the reaction chamber 20, the OES system 50 can also use an EPD (Endpoint Detection) algorithm to detect the etching endpoint, and send a control instruction to the controller 10 when the etching endpoint is detected, and the controller 10 controls the etching tool 40 to stop the current etching process according to the control instruction. Alternatively, the OES system 50 can also send a control instruction to the etching tool 40 when the etching endpoint is detected to control the etching tool 40 to stop the current etching process.

[0091] As an example, the controller 10 may automatically process batches of wafers in an automatic mode with the assistance of the etching system 100 , or automatically adjust the chamber conditions of the reaction chamber 20 .

[0092] As an example, see Figure 2 The OES system 50 includes an EPD algorithm program 51, an interface program 52, and an external communication program 53, and the controller 10 includes a control panel 11. To achieve automatic and continuous processing of batches of wafers, the operator can click on the "remote control icon" on the control panel. In response to the click on the "remote control icon" on the control panel, the controller 10 switches the operating mode of the etching system 100 to automatic mode. In automatic mode, the OES system 50 collects the optical emission spectrum of the reaction chamber 20 and generates an OES signal. The OES signal is analyzed by the EPD algorithm program 51, and the analysis results are sent to the etching tool 40 via the interface program 52 and the external communication program 53, so as to control the etching tool 40 to automatically and continuously process batches of wafers.

[0093] Next, the batch wafer processing method provided by the embodiment of the present application is introduced in detail.

[0094] Figure 3 This is a flow chart of a batch wafer processing method provided by an embodiment of the present application, which can be applied to Figure 3 In the etching system 100 shown, Figure 3 As shown, the method may include the following steps:

[0095] Step 301: The etching system performs chamber adjustment on the reaction chamber and verifies the process parameters of the etching process.

[0096] Before the etching process begins, it is necessary to perform chamber adjustment on the reaction chamber and calibrate the process parameters of the etching process in advance to ensure that the chamber conditions and process parameters of the reaction chamber meet the specifications.

[0097] Among them, chamber adjustment may include adjustment of chamber conditions such as gas pipeline leakage rate, LBR (Chamber leak rate, chamber back leakage rate) and MFC (Mass flow controller, mass flow controller) accuracy, and of course may also include adjustment of other chamber conditions, which is not limited in the embodiments of the present application.

[0098] By performing chamber adjustment on the reaction chamber, it is possible to ensure that consistent chamber conditions are maintained between batches of batch wafers, thereby reducing process drift and instability problems between batches of batch wafers.

[0099] As an example, taking the etching process as a heavy-polymer etching process, the implementation process of performing chamber adjustment on the reaction chamber and verifying the process parameters of the etching process may include the following process:

[0100] 1) With a first silicon wafer placed in a chamber of a reaction chamber, the chamber of the reaction chamber is cleaned using a chamber cleaning baseline.

[0101] The first silicon wafer may be a bare silicon wafer. The first silicon wafer may be placed on a wafer block in the reaction chamber, and then the chamber of the reaction chamber may be cleaned using a chamber cleaning baseline. The wafer block is used to place the wafer to be processed.

[0102] The chamber cleaning baseline refers to a pre-set standard cleaning baseline for chamber cleaning. The chamber cleaning baseline uses a standard cleaning recipe and a standard cleaning intensity to clean the reaction chamber. The standard cleaning recipe can be a standard plasma. For example, the chamber cleaning baseline can be a POR (Process of Record) plasma cleaning. The cleaning recipe can be SF6 or O2.

[0103] As an example, when the etching process employs RIE (Reactive Ion Etching), a first silicon wafer may be placed in the chamber of the reaction chamber, and the chamber of the reaction chamber may be cleaned using a chamber cleaning baseline. For example, the chamber of the reaction chamber may be cleaned using a plasma cleaning method known as POR. Furthermore, when the etching process employs DRIE (Deep Reactive Ion Etching), the chamber of the reaction chamber may be cleaned using a waferless cleaning method, such as a POR waferless cleaning method.

[0104] 2) Processing at least one first conditioning wafer to perform chamber conditioning on the reaction chamber.

[0105] The first conditioning wafer is used to condition the reaction chamber, and the first conditioning wafer may be a PR (photoresist) or other similar wafers.

[0106] During the process of processing at least one first adjustment wafer, the chamber wall of the reaction chamber can be pre-coated with polymer, that is, a layer of protective polymer is pre-coated on the chamber wall, and then the at least one first adjustment wafer is processed separately to perform chamber adjustment on the reaction chamber to ensure that the adjusted chamber conditions meet the process requirements.

[0107] Among them, the number and adjustment time of at least one first adjustment wafer depend on the thin film stack, process chemistry and chamber conditions, etc. The embodiment of the present application does not limit the number and adjustment time of at least one first adjustment wafer.

[0108] 3) Performing each process step of the re-polymerization etching process baseline on the second silicon wafer to verify the process parameters of each step in the re-polymerization etching process baseline.

[0109] The second silicon wafer is a bare silicon wafer, and may be the same wafer as the first silicon wafer or a different wafer. The repolymerization etching process baseline is a pre-configured standard repolymerization etching process.

[0110] By verifying the process parameters of each step in the repolymerization etching process baseline, it is possible to detect whether the process parameters of each step in the repolymerization etching process baseline meet the process specifications. If not, it is possible to return to step 1) to optimize the process parameters until the process parameters meet the process specifications.

[0111] Taking the Bosch process as an example, the process parameters for steps D1, E1, and E2 can be verified separately. D1 is the polymer deposition step, E1 is the isotropic etching step, and E2 is the unidirectional etching step. E1 and E2 process the same material: both are the results of D1.

[0112] For example, executing each process step of the Bosch process baseline on the second silicon wafer to verify the process parameters of each step in the Bosch process baseline may include: performing polymer deposition on the second silicon wafer to verify the deposition rate and uniformity of the polymer deposition step; performing isotropic etching on the second silicon wafer after polymer deposition to verify the etching rate and uniformity of the isotropic etching step; and performing unidirectional etching on the second silicon wafer after polymer deposition to verify the etching rate and uniformity of the unidirectional etching step.

[0113] 4) Etching the patterned wafer according to the re-polymerization etching process baseline to verify the process parameters of the re-polymerization etching process baseline.

[0114] For example, a patterned wafer or a structured wafer may be etched according to the repolymerization etching process baseline to verify the process parameters of the repolymerization etching process, such as etching depth, size, profile, stripes, surface roughness, and residue.

[0115] Among them, verifying the process parameters of the heavy polymerization etching process baseline refers to detecting whether the process parameters of the heavy polymerization etching process baseline meet the process specifications. If not, returning to step 1) to optimize the process parameters until the process parameters meet the process specifications.

[0116] Step 302: The etching system performs waferless cleaning on the chamber of the reaction chamber using the waferless cleaning baseline, and etches the first product wafer in the batch of wafers after the waferless cleaning.

[0117] In the embodiments of the present application, the wafers to be processed in a batch of wafers are referred to as product wafers to distinguish them from other wafers. To optimize the waferless cleaning intensity and maintain a stable polymer state in the chamber during continuous wafer processing, the first product wafer in the batch of wafers can be processed according to the waferless cleaning baseline and the post-processing process performance can be tested to see if it meets the process specifications.

[0118] Step 303: The etching system detects whether the process performance of etching the first product wafer meets the process specifications.

[0119] For example, it is possible to detect whether the etch depth of the first product wafer etched meets the etch depth specification.

[0120] Step 304: If the process performance of etching the first product wafer does not meet the process specification, the etching system adjusts the cleaning intensity of the wafer-free cleaning baseline.

[0121] If the process performance of etching the first product wafer does not meet the process specifications, it means that using the waferless cleaning baseline to perform waferless cleaning on the chamber of the reaction chamber cannot guarantee that the polymer state remains stable during the processing of the batch of wafers. In this case, the cleaning intensity of the waferless cleaning baseline can be adjusted so that the cleaning intensity of the adjusted waferless cleaning baseline can meet the process requirements.

[0122] During the continuous processing of batch wafers, polymers are continuously generated and accumulated. Excessive polymer deposition may cause process instability. Cleaning the chamber using a waferless cleaning process before processing the product wafers helps to remove polymers from the chamber to reduce polymer deposition.

[0123] In an embodiment of the present application, the cleaning intensity of the waferless cleaning baseline is adjusted, that is, the waferless cleaning intensity is optimized, in order to balance the two driving forces of polymer generation and removal, so that the cleaning intensity of the adjusted waferless cleaning baseline can balance the polymer deposition in the etching of the product wafers, that is, the polymer state in the etching of the product wafers is in a saturated state, and the polymer state can be maintained at the same level during the processing of each product wafer in the subsequent batch of wafers. The chamber conditions become stable and there is less interference from the process environment, thereby minimizing the impact on the etching rate of the product wafers. In this case, the process performance of the product wafer etching can meet the process specifications.

[0124] Please refer to Figure 4 , Figure 4 Schematic diagram of the change of the polymer state of a reaction chamber provided in an embodiment of the present application. Figure 4Figure (a) is a schematic diagram of a chamber without polymer deposition. Figure 4 Figure (b) is a schematic diagram of polymer pre-coating on the cavity wall of the chamber. Figure 4 Figure (c) is a schematic diagram showing that the polymer deposited on the cavity wall of the chamber is in an unsaturated state. Figure 4 Figure (d) is a schematic diagram showing that the polymer deposited on the cavity wall of the chamber is in a saturated state. Figure 4 As shown, during the batch wafer processing, when the polymer deposited on the chamber wall is always in the state of Figure 4 When the saturation state is shown in Figure (d), the impact on the etching rate of the product wafer can be minimized.

[0125] As an example, the cleaning intensity of the waferless cleaning baseline can be adjusted by adjusting one or more of the following parameters of the waferless cleaning baseline: cleaning recipe, cleaning duration, RF performance or microwave performance, gas pressure, and gas flow rate. RF performance can include one or more of RF power, RF pulse frequency, and RF pulse duty cycle. Microwave performance can include one or more of microwave power, microwave pulse frequency, and microwave pulse duty cycle.

[0126] As an embodiment of the present application, the cleaning recipe of the waferless cleaning baseline may be adjusted to adjust the cleaning intensity of the waferless cleaning baseline.

[0127] For example, if the etching depth of the first product wafer is greater than the etching depth specification, the first cleaning recipe of the wafer-free cleaning baseline is adjusted to a second cleaning recipe, and the cleaning intensity of the second cleaning recipe is less than the cleaning intensity of the first cleaning recipe.

[0128] If the etch depth of the first product wafer is greater than the etch depth specification, it means that excessive polymer deposition will lead to an excessively high etch rate. In this case, the cleaning intensity of the waferless cleaning baseline can be reduced by adjusting the first cleaning recipe of the waferless cleaning baseline to the second cleaning recipe.

[0129] For example, the second cleaning recipe may be a more aggressive waferless cleaning process recipe such as strong O2, SF6 or O2.

[0130] For another example, if the etching depth of the first product wafer is less than the etching depth specification, the first cleaning recipe of the wafer-free cleaning baseline is adjusted to a third cleaning recipe, and the cleaning intensity of the third cleaning recipe is greater than the cleaning intensity of the first cleaning recipe.

[0131] If the etching depth of the first product wafer is less than the etching depth specification, it means that too little polymer deposition will lead to a too low etching rate. In this case, the cleaning intensity of the waferless cleaning baseline can be improved by adjusting the first cleaning recipe of the waferless cleaning baseline to the third cleaning recipe.

[0132] As another embodiment of the present application, the cleaning duration of the waferless cleaning baseline can be adjusted to adjust the cleaning intensity of the waferless cleaning baseline. The longer the cleaning duration of the waferless cleaning baseline, the greater the cleaning intensity of the waferless cleaning baseline.

[0133] For example, based on the correspondence between the process time of wafer processing and the waferless cleaning time, the cleaning time of the waferless cleaning baseline can be adjusted to the waferless cleaning time corresponding to the process time of continuous processing of batch wafers.

[0134] Among them, the waferless cleaning time corresponding to the process time of wafer processing is the cleaning time in which waferless cleaning according to the corresponding waferless cleaning time can make the polymer deposited on the product wafer under the corresponding process time in a saturated state.

[0135] Among them, the correspondence between the process time of wafer processing and the waferless cleaning time can be obtained in advance based on the different process times of sample product wafer processing and the corresponding saturated cleaning time. The saturated cleaning time refers to the cleaning time when waferless cleaning is performed according to the same waferless cleaning formula so that the polymer deposited on the sample product wafer under the corresponding process time is in a saturated state.

[0136] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the corresponding relationship between the process time of wafer processing and the time without wafer cleaning provided in an embodiment of the present application. Figure 5 As shown, the longer the process time of wafer handling, the longer the waferless cleaning time required to clean the polymer.

[0137] Step 305: The etching system performs waferless cleaning on the chamber of the reaction chamber using the adjusted waferless cleaning baseline, and etches the second product wafer of the batch of wafers after the waferless cleaning.

[0138] Step 306: The etching system detects whether the process performance of etching the second product wafer meets the process specifications.

[0139] Step 307: If the process performance of etching the second product wafer meets the process specification, the etching system sequentially etches the unprocessed product wafers in the batch of wafers according to the adjusted wafer-free cleaning baseline.

[0140] If the process performance of etching the second product wafer after waferless cleaning the reactor chamber using the adjusted waferless cleaning baseline meets the process specifications, then waferless cleaning the reactor chamber using the adjusted waferless cleaning baseline can ensure stable polymer conditions throughout the wafer batch. In this case, no secondary adjustment is required, and the unprocessed product wafers in the batch can be continuously etched directly using the adjusted waferless cleaning baseline.

[0141] In addition, to further verify that the adjusted waferless cleaning baseline meets the process requirements, after detecting that the process performance of etching the second product wafer meets the process specifications, the adjusted waferless cleaning baseline can also be used to perform waferless cleaning on the chamber of the reaction chamber. After the waferless cleaning, the third product wafer in the batch of wafers is timed to detect whether the process performance of etching the third product wafer meets the process specifications. If the process performance of etching the third product wafer meets the process specifications, it means that the adjusted waferless cleaning baseline has passed the verification of the third product wafer, and the unprocessed product wafers in the batch of wafers can be continuously etched based on the adjusted waferless cleaning baseline.

[0142] In the heavy polymer etch process, to reduce polymer deposition, the processing flow of each product wafer in a batch of wafers includes two processes: waferless cleaning and etching. In other words, the processing of batch wafers is a continuous cycle of these two processes.

[0143] Accordingly, continuously etching unprocessed product wafers in a batch of wafers according to the adjusted waferless cleaning baseline includes: for the first product wafer in the unprocessed product wafers in the batch of wafers, after processing of the previous product wafer of the first product wafer is completed, performing waferless cleaning on the chamber of the reaction chamber using the adjusted waferless cleaning baseline, and etching the first product wafer after the waferless cleaning.

[0144] The first product wafer is any one of the unprocessed product wafers, that is, any one of the unprocessed product wafers is processed in sequence according to the above process.

[0145] Generally speaking, a single adjustment to the waferless cleaning baseline's cleaning intensity is sufficient to bring it within process requirements. In this case, using just two to three production wafers is sufficient, resulting in a relatively short adjustment cycle. In exceptional cases, two adjustments may be necessary.

[0146] Step 308: If the process performance of etching the second product wafer does not meet the process specification, the etching system uses the second product wafer as the target product wafer and uses the adjusted waferless cleaning baseline as the target waferless cleaning baseline.

[0147] Step 309: The etching system adjusts the cleaning intensity of the target wafer-free cleaning baseline.

[0148] For example, if after performing waferless cleaning on a chamber of a reaction chamber using the adjusted waferless cleaning baseline, process performance of etching a second product wafer does not meet process specifications, the adjusted waferless cleaning baseline may be further adjusted a second time.

[0149] Step 310: The etching system performs waferless cleaning on the chamber of the reaction chamber using the adjusted target waferless cleaning baseline, and etches the next product wafer of the target product wafer as the target product wafer after the waferless cleaning.

[0150] For example, the etching system performs waferless cleaning on the chamber of the reaction chamber using the secondary adjusted waferless cleaning baseline, and etches the next product wafer after the waferless cleaning.

[0151] Step 311: The etching system detects whether the process performance of etching the target processing wafer meets the process specification.

[0152] For example, the etching system can detect whether the process performance of etching the next product wafer meets the process specifications.

[0153] Step 312: If the process performance of etching the target processed wafer meets the process specification, the etching system sequentially etches the unprocessed product wafers in the batch of wafers according to the adjusted target wafer-free cleaning baseline.

[0154] For example, if the process performance for etching the next product wafer meets the process specifications, then using the second-adjusted waferless cleaning baseline to clean the reactor chamber without a wafer will ensure stable polymer conditions throughout the batch. In this case, a third adjustment is not required; the unprocessed product wafers in the batch can be continuously etched directly using the second-adjusted waferless cleaning baseline.

[0155] In addition, if the process performance of etching the target processed wafer does not meet the process specifications, the etching system will use the adjusted target waferless cleaning baseline as the target waferless cleaning baseline, and return to step 307 to continue adjusting the cleaning intensity of the target waferless cleaning baseline until the chamber of the reaction chamber is waferless cleaned according to the adjusted target waferless cleaning baseline, and the process performance of processing the next product wafer of the target product wafer meets the process specifications.

[0156] For example, if the etching process performance of the next product wafer meets the process specifications, then using the twice-adjusted waferless cleaning baseline to clean the reactor chamber without wafers cannot guarantee stable polymer conditions during the processing of the batch of wafers. In this case, three more adjustments are required. Then, the reactor chamber is cleaned without wafers using the three-adjusted waferless cleaning baseline. After the waferless cleaning, the next product wafer is etched and the etching process performance is tested to see if it meets the process specifications. If not, the adjustment is stopped and the unprocessed product wafers in the batch are etched sequentially using the adjusted waferless cleaning baseline. If not, the adjustment is repeated four times, and the cycle repeats until the process performance of the next product wafer meets the process specifications after the reactor chamber is cleaned without wafers using the adjusted waferless cleaning baseline. At this point, the adjustment is stopped and the unprocessed product wafers in the batch are etched sequentially using the adjusted waferless cleaning baseline.

[0157] In addition, if the etching process of the matching wafer adopts a light polymerization etching process, the light polymerization etching process may include the following steps:

[0158] 1) With a third silicon wafer placed in the chamber of the reaction chamber, the chamber of the reaction chamber is cleaned using the chamber cleaning baseline.

[0159] The third silicon wafer may be a bare silicon wafer, and may be the same as or different from the first and second silicon wafers, which is not limited in this embodiment of the present application.

[0160] Among them, when the third silicon wafer is placed in the chamber of the reaction chamber, the process of using the chamber cleaning baseline to clean the chamber of the reaction chamber is the same as the process of using the chamber cleaning baseline to clean the chamber of the reaction chamber when the first silicon wafer is placed in the chamber of the reaction chamber. The specific process can be found in the relevant description of the above step 301, and the embodiment of the present application will not be repeated here.

[0161] 2) Processing at least one second conditioning wafer to perform chamber conditioning on the reaction chamber.

[0162] The second adjustment wafer may be a PR wafer or other similar wafers.

[0163] Among them, the process of processing at least one second adjustment wafer to perform chamber adjustment on the reaction chamber is the same as the process of processing at least one first adjustment wafer to perform chamber adjustment on the reaction chamber. The specific process can be found in the relevant description of the above step 301, and the embodiment of this application will not be repeated here.

[0164] 3) Etching the oxide-covered wafer and the patterned wafer respectively according to the light polymerization etching process baseline to verify the process parameters of the light polymerization etching process baseline.

[0165] Among them, verifying the process parameters of the light polymerization etching process baseline refers to detecting whether the process parameters of the light polymerization etching process baseline meet the process specifications. If not, return to step 1) to optimize the process parameters until the process parameters meet the process specifications.

[0166] For example, an oxide-covered wafer can be etched using a light polymer etch baseline to verify the etch rate and uniformity of the light polymer etch baseline. A patterned wafer can then be etched using the light polymer etch baseline to verify the etch depth, size, profile, striations, surface roughness, residue, and other process parameters of the light polymer etch baseline.

[0167] 4) Etch the batches of wafers in sequence according to the verified light polymerization etching process baseline.

[0168] As an example, for each product wafer in a batch of wafers, the product wafer may be etched according to the calibrated light polymer etching process baseline.

[0169] As another example, for each product wafer in a batch of wafers, the chamber of the reaction chamber can be cleaned using a wafer-free cleaning baseline, and then the product wafer can be etched according to the calibrated light polymer etch process baseline.

[0170] Since the light polymer etching process does not produce polymer deposition, or produces less polymer deposition and does not affect the process performance, the chamber of the reaction chamber does not need to be cleaned without wafers before etching each product wafer, or the chamber of the reaction chamber can be cleaned directly using a waferless cleaning baseline.

[0171] In an embodiment of the present application, the chamber of the reaction chamber can be adjusted first, and the process parameters of the etching process can be verified. Then, the chamber of the reaction chamber is cleaned without wafers using the waferless cleaning baseline. After the waferless cleaning, the first product wafer in the batch of wafers is etched, and the process performance of etching the first product wafer is detected to see whether it meets the process specifications. If not, the cleaning intensity of the waferless cleaning baseline is adjusted, and after the chamber of the reaction chamber is cleaned without wafers using the adjusted waferless cleaning baseline, the second product wafer is etched and the etching process performance is detected to see whether it meets the process specifications. If it meets, the unprocessed product wafers in the batch of wafers are etched in sequence according to the adjusted waferless cleaning baseline. In this way, the waferless cleaning intensity can be optimized by pre-etching the product wafers before processing batch wafers, so that the optimized waferless cleaning intensity will not affect the process performance of the product wafers. That is, the optimized waferless cleaning can balance the polymer deposition in the chamber, ensuring that the state of the polymer deposited in the chamber after cleaning remains stable, and will not cause the etching rate of the product wafers to drift, thereby avoiding the production of substandard products.

[0172] For ease of understanding, the light polymerization etching process flow and the heavy polymerization etching process flow using the above-mentioned batch wafer processing method will be described below with reference to the accompanying drawings.

[0173] Please refer to Figure 6 , Figure 6 Schematic diagram of a light polymerization process flow and a heavy polymerization etching process flow provided by an embodiment of the present application, wherein: Figure 6 The left process is the light polymerization process. Figure 6 The right process in the figure is the re-polymerization etching process.

[0174] like Figure 6 As shown on the left side of the figure, the light polymer etching process includes the following steps:

[0175] 1) When a bare silicon wafer is placed in a chamber of a reaction chamber, the chamber of the reaction chamber is cleaned using a chamber cleaning baseline.

[0176] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a wafer processing sequence in a light polymerization etching process provided in an embodiment of the present application. Figure 7 For example, an etching system can process 25 wafers in one batch, and these 25 wafers are numbered from #1 to #25.

[0177] For example, #1 (the first wafer) is a bare silicon wafer. For #1, the chamber of the reaction chamber can be cleaned using the chamber cleaning baseline while #1 is placed in the chamber of the reaction chamber.

[0178] 2) Process at least one PR wafer or similar wafer to perform chamber conditioning on the reaction chamber.

[0179] For example, wafers #2 (the second wafer) through #N-1 (the N-1th wafer) are PR wafers or similar wafers. These wafers can be processed sequentially to adjust the chamber conditions. Where N is greater than or equal to 3, meaning that the number of at least one PR wafer is greater than or equal to 1.

[0180] 3) Etching the oxide-covered wafer according to the light polymer etching process baseline to verify whether the etching rate and uniformity of the light polymer etching process baseline meet the process specifications.

[0181] If it meets the requirements, jump to step 4); if it does not meet the requirements, jump to step 1) and continue chamber cleaning, chamber adjustment and process verification.

[0182] For example, #N (the Nth wafer) is an oxide covered wafer, and #N can be etched according to the light polymer etching process baseline to verify the etching rate and uniformity of the light polymer etching process baseline.

[0183] 4) Etching the patterned wafer according to the light polymer etching process baseline to verify whether the process parameters of the light polymer etching process baseline, such as etching depth, size, profile, stripes, surface roughness, residue, etc., meet the process specifications.

[0184] If it meets the requirements, jump to step 5); if it does not meet the requirements, jump to step 1) and continue chamber cleaning, chamber adjustment and process verification.

[0185] For example, #N+1 (N+1th wafer) is a patterned wafer, and #N+1 can be etched according to the light polymer etching process baseline to verify the process parameters of the light polymer etching process baseline, such as etching depth, size, profile, stripes, surface roughness, residue, etc.

[0186] 5) Etch the batches of wafers sequentially.

[0187] For example, #N+2 (wafer N+2) to #25 (wafer 25) are all product wafers. #N+2 is the first product wafer, and #N+3 is the second product wafer.

[0188] 6) Batch wafer processing is completed.

[0189] In addition, if Figure 6As shown in the right process of Figure 1, the repolymerization etching process includes the following steps:

[0190] 1) When a bare silicon wafer is placed in a chamber of a reaction chamber, the chamber of the reaction chamber is cleaned using a chamber cleaning baseline.

[0191] Please refer to Figure 8 , Figure 8 This is a schematic diagram of a wafer processing sequence in a re-polymerization etching process provided in an embodiment of the present application. Figure 8 For example, an etching system can process 25 wafers in one batch, and these 25 wafers are numbered from #1 to #25.

[0192] For example, #1 is a bare silicon wafer. For #1, #1 can be placed in the chamber of the reaction chamber and the chamber cleaning baseline can be used to clean the chamber of the reaction chamber.

[0193] 2) Process at least one PR wafer or similar wafer to perform chamber conditioning on the reaction chamber.

[0194] For example, wafers #2 to #N-1 are PR wafers or similar wafers, and wafers #2 to #N-1 can be processed sequentially to adjust the chamber. Where N is greater than or equal to 3, that is, the number of at least one PR wafer is greater than or equal to 1.

[0195] 3) Performing steps D1, E1, and E2 of the repolymerization etching process baseline on the bare silicon wafer respectively to verify whether the etching rates and uniformity of steps D1, E1, and E2 in the repolymerization etching process baseline meet the process specifications.

[0196] If it meets the requirements, jump to step 4); if it does not meet the requirements, jump to step 1) and continue chamber cleaning, chamber adjustment and process verification.

[0197] For example, if #N is a bare silicon wafer, D1 (polymer deposition) is first performed on #N to verify the polymer deposition rate and uniformity. Both #N+1 and #N+2 are bare silicon wafers processed after D1. Next, E1 (isotropic etching) is performed on #N+1 to verify the isotropic etching rate and uniformity. E2 (isotropic etching) is performed on #N+2 to verify the isotropic etching rate and uniformity.

[0198] 4) Etching the patterned wafer according to the re-polymerization etching process baseline to verify whether the process parameters such as etching depth, size, profile, stripes, surface roughness, residue, etc. of the re-polymerization etching process baseline meet the process specifications.

[0199] If it meets the requirements, jump to step 5); if it does not meet the requirements, jump to step 1) and continue chamber cleaning, chamber adjustment and process verification.

[0200] For example, #N+3 is a patterned wafer, and #N+3 can be etched according to the re-polymerization etching process baseline to verify the process parameters of the re-polymerization etching process baseline, such as etching depth, size, profile, stripes, surface roughness, and residue.

[0201] 5) Etch the first product wafer in the batch of wafers to test whether the etching process performance meets the process specifications.

[0202] If it meets the requirements, jump to step 6). If it does not meet the requirements, optimize the cleaning intensity of the wafer and etch the next product wafer to detect whether the etching process performance meets the process specifications.

[0203] Wafers #N+4 to #25 are all product wafers. For example, wafer #N+4 is the first product wafer and can be etched to test whether the etching process performance meets the process specifications.

[0204] 6) Etch the next product wafer to check whether the etching process performance meets the process specifications.

[0205] If it meets the requirements, jump to step 7). If it does not meet the requirements, optimize the cleaning intensity of the wafer and etch the next product wafer to detect whether the etching process performance meets the process specifications.

[0206] For example, #N+5 is the second product wafer, and #N+5 can be etched to detect whether the etching process performance meets the process specifications, and then to detect whether the optimized wafer-free cleaning strength meets the process requirements.

[0207] 7) Etch the next product wafer to check whether the etching process performance meets the process specifications.

[0208] If it meets the requirements, jump to step 8). If it does not meet the requirements, optimize the cleaning intensity of the wafer and etch the next product wafer to detect whether the etching process performance meets the process specifications.

[0209] For example, #N+6 is the third product wafer, and #N+6 can be etched to detect whether the etching process performance meets the process specifications, and then verify whether the optimized waferless cleaning strength meets the process requirements.

[0210] 8) Etch the batches of wafers sequentially.

[0211] For example, according to the optimized wafer-free cleaning intensity, #N+7 to #25 are etched in sequence.

[0212] Please refer to Figure 8 , Figure 8 This is a schematic diagram of a wafer processing sequence in a re-polymerization etching process provided in an embodiment of the present application.

[0213] Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. The computer device can be Figure 1 The controller 10 shown. Figure 9 As shown, the computer device includes: a processor 90, a memory 91, and a computer program 92 stored in the memory 91 and executable on the processor 90. When the processor 90 executes the computer program 92, the steps in the batch wafer processing method in the above embodiment are implemented.

[0214] The computer device may be a general-purpose computer device or a dedicated computer device. In a specific implementation, the computer device may be a desktop computer, a portable computer, a network server, a PDA, a mobile phone, a tablet computer, a wireless terminal device, a communication device or an embedded device. The embodiment of the present application does not limit the type of computer device. Those skilled in the art will understand that Figure 9 This is merely an example of a computer device and does not constitute a limitation on the computer device. The computer device may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0215] The processor 90 may be a central processing unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor may be a microprocessor or any conventional processor.

[0216] In some embodiments, the memory 91 may be an internal storage unit of a computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory 91 may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on the computer device. Furthermore, the memory 91 may include both an internal storage unit of the computer device and an external storage device. The memory 91 is used to store an operating system, application programs, a boot loader, data, and other programs. The memory 91 may also be used to temporarily store data that has been output or is about to be output.

[0217] An embodiment of the present application also provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps of any of the above-mentioned method embodiments when executing the computer program.

[0218] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0219] An embodiment of the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the steps in the above-mentioned various method embodiments.

[0220] If the integrated unit is implemented as a software functional unit and sold or used as a standalone product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application can implement all or part of the processes in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a camera / terminal device, a recording medium, computer memory, ROM (Read-Only Memory), RAM (Random Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk, and optical data storage device. The computer-readable storage medium mentioned in the present application can be a non-volatile storage medium, in other words, a non-transitory storage medium.

[0221] It should be understood that all or part of the steps for implementing the above embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the steps may be implemented in the form of a computer program product. The computer program product may include one or more computer instructions. The computer instructions may be stored in the computer-readable storage medium described above.

[0222] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0223] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0224] In the embodiments provided in this application, it should be understood that the disclosed apparatus / computer equipment and methods can be implemented in other ways. For example, the apparatus / computer equipment embodiments described above are merely schematic. For example, the division of modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of the apparatus or unit, which can be electrical, mechanical or other forms.

[0225] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0226] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for processing batch wafers, characterized in that: The method comprises: Perform chamber adjustment on the reaction chamber and verify the process parameters of the etching process; performing waferless cleaning on a chamber of the reaction chamber using a waferless cleaning process, etching a first product wafer in the batch of wafers after the waferless cleaning, and detecting whether the process performance of etching the first product wafer meets process specifications; If the process performance of etching the first product wafer does not meet the process specification, adjusting the cleaning intensity of the waferless cleaning process; performing waferless cleaning on a chamber of the reaction chamber using the adjusted waferless cleaning process, etching a second product wafer of the batch of wafers after the waferless cleaning, and detecting whether the process performance of etching the second product wafer meets the process specification; If the process performance of etching the second product wafer meets the process specification, etching the unprocessed product wafers in the batch of wafers in sequence according to the adjusted waferless cleaning process; The step of adjusting the cleaning intensity of the wafer-free cleaning process includes: According to the correspondence between the process time of wafer processing and the waferless cleaning time, the cleaning time of the waferless cleaning process is adjusted to the waferless cleaning time corresponding to the process time of the continuous processing of the batch wafers; the correspondence between the process time of wafer processing and the waferless cleaning time is obtained in advance based on the different process times of sample product wafer processing and the corresponding saturation cleaning time. The saturated cleaning time refers to the cleaning time when waferless cleaning is performed according to the same waferless cleaning formula so that the polymer state deposited on the sample product wafer under the corresponding process time is in a saturated state.

2. The method according to claim 1, wherein If the process performance of etching the second product wafer meets the process specification, etching the unprocessed product wafers in the batch of wafers in sequence according to the adjusted waferless cleaning process, including: If the process performance of etching the second product wafer meets the process specification, performing waferless cleaning on the chamber of the reaction chamber using the adjusted waferless cleaning process, etching the third product wafer in the batch of wafers after the waferless cleaning, and testing whether the process performance of etching the third product wafer meets the process specification; If the process performance of etching the third product wafer meets the process specification, the unprocessed product wafers in the batch of wafers are etched sequentially according to the adjusted waferless cleaning process.

3. The method according to claim 1, wherein After detecting whether the process performance of etching the second product wafer meets the process specification, the method further includes: If the process performance of etching the second product wafer does not meet the process specification, the second product wafer is used as the target product wafer, the adjusted waferless cleaning process is used as the target waferless cleaning process, and the cleaning intensity of the target waferless cleaning process is adjusted; performing waferless cleaning on a chamber of the reaction chamber using the adjusted target waferless cleaning process, etching a product wafer subsequent to the target product wafer as the target product wafer after the waferless cleaning, and detecting whether the process performance of etching the target process wafer meets the process specification; If the process performance of etching the target processed wafer meets the process specification, etching the unprocessed product wafers in the batch of wafers in sequence according to the adjusted target waferless cleaning process; If the process performance of etching the target processed wafer does not meet the process specifications, the adjusted target waferless cleaning process will be used as the target waferless cleaning process, and the process will return to the step of adjusting the cleaning intensity of the target waferless cleaning process until the chamber of the reaction chamber is waferless cleaned according to the adjusted target waferless cleaning process, and after the process performance of etching the next product wafer of the target product wafer meets the process specifications, the unprocessed product wafers in the batch of wafers will be etched in sequence according to the adjusted waferless cleaning process.

4. The method according to claim 1, wherein The method of adjusting the cleaning intensity of the waferless cleaning process also includes one or more of the following methods: Adjusting the cleaning recipe of the waferless cleaning process; Adjusting the radio frequency performance or microwave performance of the waferless cleaning process; Adjusting the gas pressure of the waferless cleaning process; The gas flow rate of the waferless cleaning process is adjusted.

5. The method according to claim 4, wherein The adjusting of the cleaning formula of the waferless cleaning process includes: If the etching depth of the first product wafer is greater than the etching depth specification, adjusting the first cleaning recipe of the waferless cleaning process to a second cleaning recipe, wherein the cleaning intensity of the second cleaning recipe is less than the cleaning intensity of the first cleaning recipe; If the etching depth of the first product wafer is less than the etching depth specification, the first cleaning recipe of the waferless cleaning process is adjusted to a third cleaning recipe, and the cleaning intensity of the third cleaning recipe is greater than the cleaning intensity of the first cleaning recipe.

6. The method according to claim 1, wherein The step of sequentially etching the unprocessed product wafers in the batch of wafers according to the adjusted wafer-free cleaning process comprises: For the first product wafer among the unprocessed product wafers in the batch of wafers, after processing of the previous product wafer of the first product wafer is completed, the chamber of the reaction chamber is waferless cleaned using the adjusted waferless cleaning process, and the first product wafer is etched after the waferless cleaning, and the first product wafer is any one of the unprocessed product wafers.

7. The method according to claim 1, wherein The step of adjusting the reaction chamber and verifying the process parameters of the etching process includes: When a first silicon wafer is placed in the chamber of the reaction chamber, cleaning the chamber of the reaction chamber using a chamber cleaning process; processing at least one first conditioning wafer to perform chamber conditioning on the reaction chamber; Performing each process step of the repolymerization etching process on the second silicon wafer to verify the process parameters of each step in the repolymerization etching process; The patterned wafer is etched according to the repolymerization etching process flow to verify the process parameters of the repolymerization etching process flow.

8. The method according to claim 7, wherein The repolymerization etching process is a Bosch process, and each process step of the repolymerization etching process is performed on the second silicon wafer to verify the process parameters of each step in the repolymerization etching process, including: performing polymer deposition on the second silicon wafer to verify the deposition rate and uniformity of the polymer deposition step; performing isotropic etching on the second silicon wafer after polymer deposition to verify the etching rate and uniformity of the isotropic etching step; The second silicon wafer after polymer deposition was unidirectionally etched to verify the etching rate and uniformity of the unidirectional etching step.

9. The method according to claim 8, wherein Etching the patterned wafer according to the repolymerization etching process to verify the process parameters of the repolymerization etching process includes: Etch patterned or structured wafers according to the re-polymerization etch process flow to verify the etch depth, size, profile, striations, surface roughness, and residue of the re-polymerization etch process.

10. The method according to any one of claims 1 to 9, characterized in that: The etching process for the batch wafers adopts a heavy polymerization etching process.

11. The method according to claim 10, wherein The repolymerization etching process is a Bosch process.

12. The method according to claim 10, wherein The method further comprises: If the etching process for the batch wafers adopts a light polymer etching process, the chamber of the reaction chamber is cleaned using a chamber cleaning process when a third silicon wafer is placed in the chamber of the reaction chamber; processing at least one second conditioning wafer to perform chamber conditioning on the reaction chamber; Etching the oxide-covered wafer and the patterned wafer respectively according to the light polymer etching process to verify the process parameters of the light polymer etching process; The batches of wafers are etched sequentially according to the verified light polymerization etching process flow.

13. The method according to any one of claims 1 to 9, characterized in that: The step of adjusting the chamber conditions of the reaction chamber comprises: acquiring an optical emission spectrum from an optical emission spectroscopy system connected to the reaction chamber; The chamber conditions of the reaction chamber are adjusted according to the acquired optical emission spectrum.

14. The method according to any one of claims 1 to 9, wherein: The step of sequentially etching the unprocessed product wafers in the batch of wafers according to the adjusted wafer-free cleaning process comprises: acquiring an optical emission spectrum from an optical emission spectroscopy system connected to the reaction chamber; According to the acquired optical emission spectrum and the adjusted wafer-free cleaning process, unprocessed product wafers in the batch of wafers are etched in sequence.

15. An etching system, characterized in that: The etching system includes a controller, a reaction chamber, a cleaning system and an etching tool, wherein the controller is connected to the reaction chamber, the cleaning system and the etching tool respectively, the cleaning system is used to clean the reaction chamber, the etching tool is used to etch the wafer placed in the reaction chamber, and the controller is used to control the reaction chamber, the cleaning system and the etching tool respectively; The controller includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the etching system implements the method according to any one of claims 1 to 14.

16. The system according to claim 15, wherein: The etching system further comprises an optical emission spectroscopy system, wherein the optical emission spectroscopy system is connected to the controller and the reaction chamber respectively; The controller is used to obtain the optical emission spectrum of the reaction chamber from an optical emission spectrum system connected to the reaction chamber, and adjust the chamber conditions of the reaction chamber according to the obtained optical emission spectrum.

17. The system according to claim 16, wherein: The controller is further configured to obtain an optical emission spectrum of the reaction chamber from an optical emission spectrum system connected to the reaction chamber, and control the reaction chamber and the etching tool to sequentially etch batches of wafers based on the obtained optical emission spectrum.

18. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 14 is implemented.

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