Method for manufacturing split-gate trench MOSFET

Abstract

The present invention relates to a method for manufacturing a separated gate trench MOSFET, comprising: providing a substrate; forming a patterned oxide mask layer on the upper surface of the substrate; etching the substrate based on the patterned oxide mask layer to form a first trench in the substrate; forming a first gate oxide layer and shielding gate polysilicon in the first trench; forming an isolation material layer; etching the isolation material layer, and leaving the remaining isolation material layer inside the first trench as an isolation structure; forming a second gate oxide layer and gate polysilicon in the first trench; and performing ion implantation on the substrate to form source regions on both sides of the first trench. The present application adopts a patterned oxide mask layer to replace a traditional ONO hard mask layer, so the degree of freedom is relatively high in the subsequent process processing, avoiding the risk of SiN online contamination.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method for manufacturing a separated-gate trench MOSFET. Background Art

[0002] The existing split-gate trench MOSFET manufacturing process is mainly divided into two major process schools, one with a split gate with a top-bottom structure, and the other with a split gate with a sandwiched structure on both sides. The former can achieve a higher cell density than the latter, so it can provide a higher current density and better performance.

[0003] For MOSFETs with separated gates and upper and lower structures, isolation materials are needed to isolate the upper and lower polysilicon. In the traditional manufacturing process, the "oxide layer + silicon nitride + oxide layer" ONO hard mask layer is used as an etching barrier layer. In the subsequent CMP process, due to some defects or other problems, the oxide layer on the silicon nitride in the ONO hard mask layer cannot be completely removed in some areas. The residual oxide layer on the silicon nitride will hinder the full stripping of the silicon nitride, resulting in residual silicon nitride after the full stripping step of the silicon nitride. The residual silicon nitride will fall off in the subsequent process steps, causing a peeling defect (peeling) of the device.

[0004] At the same time, in the traditional manufacturing process, after all gates are made, the source region injection needs to be formed through an additional photolithography process to form a patterned photoresist layer, and then ion implantation is performed using the patterned photoresist layer as an injection barrier to form the source region. The process flow is complicated and the production efficiency is low. Summary of the invention

[0005] Based on this, it is necessary to provide a method for manufacturing a split-gate trench MOSFET to address the technical problems in the prior art.

[0006] A method for manufacturing a split-gate trench MOSFET, comprising:

[0007] providing a substrate;

[0008] forming a patterned oxide mask layer on the upper surface of the substrate, wherein the patterned oxide mask layer includes an opening pattern, and the opening pattern defines the shape and position of the first trench;

[0009] patterning the substrate based on the patterned oxide mask layer to form a first trench in the substrate;

[0010] forming a first gate oxide layer and a shielding gate polysilicon in the first trench, wherein an upper surface of the shielding gate polysilicon is lower than an upper surface of the substrate, and the first gate oxide layer is formed between the shielding gate polysilicon and an inner wall of the first trench;

[0011] forming an isolation material layer, wherein the isolation material layer fills the first trench and covers the substrate;

[0012] Etching the isolation material layer, leaving a portion of the isolation material layer inside the first trench as an isolation structure, wherein the upper surface of the isolation structure is lower than the upper surface of the substrate;

[0013] forming a second gate oxide layer and gate polysilicon in the first trench, wherein the gate polysilicon is located on the upper surface of the isolation structure, and the second gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench;

[0014] Ion implantation is performed on the substrate to form source regions on both sides of the first trench.

[0015] In one embodiment,

[0016] The etching of the isolation material layer forms a self-aligned pattern structure on the remaining portion of the isolation material layer inside the first trench as an isolation structure, and also forms a self-aligned pattern structure on the remaining portion of the isolation material layer outside the first trench, wherein the self-aligned pattern structure is spaced apart from the first trench;

[0017] The step of implanting ions into the substrate to form source regions on both sides of the first trench includes:

[0018] Ion implantation is performed on the substrate based on the self-aligned pattern structure to form source regions on both sides of the first trench.

[0019] In one embodiment,

[0020] Before etching away a portion of the isolation material layer, the thickness of the isolation material layer inside the first trench is T1;

[0021] After etching away a portion of the isolation material layer, the thickness of the isolation structure inside the first trench is T2;

[0022] The groove opening width of the first groove is W;

[0023] T1>T2+0.5W.

[0024] In one embodiment,

[0025] The step of forming a first gate oxide layer and a shielding gate polysilicon in the first trench, wherein the upper surface of the shielding gate polysilicon is lower than the upper surface of the substrate, and the first gate oxide layer is formed between the shielding gate polysilicon and the inner wall of the first trench, comprises:

[0026] removing the patterned oxide mask layer;

[0027] forming a first oxide material layer on the upper surface of the substrate and the inner wall of the first trench;

[0028] Filling a shielding gate polysilicon material layer in the first trench;

[0029] Carving back the shielding gate polysilicon material layer to form the shielding gate polysilicon, wherein the upper surface of the shielding gate polysilicon is lower than the upper surface of the substrate;

[0030] The first oxide material layer is etched to form the first gate oxide layer, and the first gate oxide layer is formed between the shielding gate polysilicon and the inner wall of the first trench.

[0031] In one embodiment, before forming the isolation material layer, wherein the isolation material layer fills the first trench and covers the substrate, the method further includes:

[0032] The shielding gate polysilicon is additionally etched to eliminate the step difference between the upper surface of the shielding gate polysilicon and the first gate oxide layer.

[0033] In one embodiment,

[0034] The step of etching back the shielding gate polysilicon material layer to form the shielding gate polysilicon, wherein the upper surface of the shielding gate polysilicon is lower than the upper surface of the substrate, further comprises:

[0035] Ion implantation is performed on the substrate to form a first well region in the substrate; the depth of the first well region is less than the depth of the first trench.

[0036] In one embodiment,

[0037] After the first oxide material layer is etched to form the first gate oxide layer, and the first gate oxide layer is formed between the shielding gate polysilicon and the inner wall of the first trench, the method further includes:

[0038] forming a low temperature oxide layer on the surface of the shield gate polysilicon, and simultaneously performing a first well push to transform the first well region into a second well region, wherein the depth of the second well region is greater than the depth of the first well region and less than the depth of the first trench;

[0039] The second gate oxide layer and gate polysilicon are formed in the first trench, the gate polysilicon is located on the upper surface of the isolation structure, and the second gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench, and further includes:

[0040] A second well push-up is performed while the inner wall of the first trench is thermally oxidized to form the second gate oxide layer, so as to transform the second well region into a third well region, the depth of which is greater than that of the second well region and less than that of the first trench.

[0041] In one embodiment, the forming of a second gate oxide layer and gate polysilicon in the first trench, the gate polysilicon being located on the upper surface of the isolation structure, and the second gate oxide layer being formed between the gate polysilicon and the inner wall of the first trench, comprises:

[0042] forming a second gate oxide layer on an inner wall of the first trench;

[0043] forming a gate polysilicon material, wherein the gate polysilicon material fills the first trench and covers the substrate and the self-aligned pattern structure;

[0044] planarizing the gate polysilicon material;

[0045] The gate polysilicon material is etched back to expose the substrate and the self-aligned pattern structure, and the gate polysilicon material in the first trench is gate polysilicon.

[0046] In one embodiment, after the substrate is ion implanted based on the self-aligned pattern structure to form source regions on opposite sides of the first trench, the method further includes:

[0047] forming a dielectric layer, wherein the dielectric layer covers the second gate oxide layer, the gate polysilicon and the self-aligned pattern structure;

[0048] forming an interconnection through hole in the dielectric layer, wherein the interconnection through hole extends into the substrate and is located between source regions between adjacent first trenches;

[0049] A conductive plug is formed in the interconnection through hole.

[0050] In one embodiment, forming interconnection vias in the dielectric layer includes:

[0051] The dielectric layer, the self-aligned pattern structure and the substrate are sequentially etched from the surface of the dielectric layer to form the interconnection through-holes.

[0052] In one embodiment, the substrate has an active area and a terminal area located outside the active area; the first trench is formed in the active area;

[0053] forming a second trench in the terminal region while forming the first trench;

[0054] While forming a first gate oxide layer on the inner wall of the first trench, a terminal region isolation oxide layer is also formed on the inner wall of the second trench and the surface of the substrate;

[0055] While forming shielding gate polysilicon in the first trench, terminal region polysilicon is also formed in the second trench, wherein the terminal region polysilicon is surrounded by the terminal region isolation oxide layer;

[0056] The etching of the isolation material layer uses the remaining portion of the isolation material layer inside the first trench as an isolation structure, and also uses the remaining portion of the isolation material layer in the terminal area as a terminal protection structure, and the terminal protection structure covers the second trench in the terminal area.

[0057] The above-mentioned separated-gate trench MOSFET and the preparation method thereof adopt a patterned oxide mask layer to replace the traditional ONO hard mask layer, so the degree of freedom is relatively high in the subsequent process treatment, avoiding the risk of SiN online contamination. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 is a flow chart of a method for preparing a split-gate trench MOSFET provided in one embodiment;

[0060] Figure 2 This is a schematic diagram of a substrate structure in one embodiment;

[0061] Figure 3-Figure 20 Schematic diagram of the relevant structures in the preparation process of the split-gate trench MOSFET.

[0062] Description of reference numerals:

[0063] Explanation of the accompanying drawings: 100-base, 110-substrate, 120-epitaxial layer, 201-oxide mask material layer, 200-patterned oxide mask layer, 301-first oxide material layer, 310-first gate oxide layer, 320-thinned oxide layer, 330-terminal region isolation oxide layer, 401-shielding gate polysilicon material layer, 410-shielding gate polysilicon, 420-terminal region polysilicon, 501-isolation material layer, 510-isolation structure, 520-self-aligned graphic structure, 530-terminal protection structure, 600-second gate oxide layer, 701-polysilicon material, 700-gate polysilicon, 800-low-temperature oxide layer, 900-dielectric layer, 1000-conductive plug. DETAILED DESCRIPTION

[0064] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0066] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0067] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0068] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0069] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0070] Please refer to Figure 1 The present invention provides a method for preparing a split-gate trench MOSFET, comprising the following steps:

[0071] Step S1, providing a substrate 100;

[0072] Step S2, forming a patterned oxide mask layer 200 on the upper surface of the substrate 100, please refer to Figure 3 ;

[0073] Step S3, patterning the substrate 100 based on the patterned oxide mask layer 200 to form a first trench 100a in the substrate, please continue to refer to Figure 3 ;

[0074] Step S4, forming a first gate oxide layer 310 and a shielding gate polysilicon 410 in the first trench 100a, please refer to Fig. 9 ;

[0075] Step S5, forming an isolation material layer 501, please refer to Fig.10 ;

[0076] Step S6, etching the isolation material layer 501, and leaving the isolation material layer 501 inside the first trench 100a as the isolation structure 510, please refer to Fig.11 ;

[0077] Step S7, forming a second gate oxide layer 600 and a gate polysilicon layer 700 in the first trench 100a, please refer to Fig.15 ;

[0078] Step S8, ion implantation is performed on the substrate 100 to form source regions 10 on both sides of the first trench 100a. Fig.16 .

[0079] In step S1: Please refer to Figure 2The provided substrate 100 may have an active area A1 and a terminal area A2 distributed in a lateral direction. In addition, the substrate 100 may include a substrate 110 and an epitaxial layer 120 .

[0080] As an example, the substrate 110 may include but is not limited to a silicon substrate, a silicon carbide substrate or a silicon germanium substrate. Specifically, the substrate 10 may be formed by ion implantation into an intrinsic substrate.

[0081] The epitaxial layer 120 is formed on the substrate 110 .

[0082] As an example, an epitaxial layer 120 may be formed by epitaxial growth on the surface of the substrate 110 using an epitaxial process.

[0083] In step S2, please refer to Figure 3 , an oxide mask material layer may be first formed on the surface of the substrate 100. As an example, the oxide mask material layer may be formed by thermally oxidizing the substrate 100. Alternatively, an oxide layer may be deposited on the substrate 100 as the oxide mask material layer.

[0084] Afterwards, a photoresist may be formed on the surface of the oxide mask material layer, and a photolithography process may be performed to pattern the oxide mask material layer to form a patterned oxide mask layer 200. The patterned oxide mask layer 200 includes an opening pattern, and the opening pattern defines the shape and position of the first trench 100a to be formed subsequently.

[0085] Afterwards, the photoresist is removed.

[0086] In step S3, please continue to refer to Figure 3 , the first trench 100 a is specifically located in the active area A1 of the substrate 100 , and is formed in the epitaxial layer 120 .

[0087] Here, a patterned oxide mask layer 200 is used to replace a conventional ONO hard mask layer, and the substrate 100 is etched to form a first trench 100 a.

[0088] In step S4, please refer to Fig. 9 The upper surface of the shielding gate polysilicon 410 is lower than the upper surface of the substrate 100 , and the first gate oxide layer 310 is formed between the shielding gate polysilicon 410 and the inner wall of the first trench 100 a .

[0089] In step S5, please refer to Fig.10 , the isolation material layer 501 fills the first trench 100 a and covers the substrate 100 .

[0090] It is worth noting that the isolation material layer 501 is not necessarily directly connected to the substrate 100, and there may be other film layers (such as Fig.10Of course, the isolation material layer 501 and the substrate 100 may also be directly connected, and this application does not limit this.

[0091] As an example, the isolation material layer 501 may be formed by a high density plasma chemical vapor deposition (HDP CVD) process.

[0092] The isolation material layer 501 may not fill up the first trench 100a, thereby reducing production costs and improving production efficiency. Of course, the isolation material layer 501 may also fill up the isolation material layer 501, and the present application has no limitation on this.

[0093] In step S6, please refer to Fig.11 The isolation structure 510 is located on the upper surface of the shielding gate polysilicon 410 . Also, the upper surface of the isolation structure 510 is lower than the upper surface of the substrate 100 .

[0094] As an example, wet etching may be used to remove part of the isolation material layer 501 to form the isolation structure 510 . The isolation structure 510 is used to isolate the shielding gate polysilicon 410 and the gate polysilicon 700 .

[0095] In step S7, please refer to Fig.15 The gate polysilicon 700 is located on the upper surface of the isolation structure 510, and the second gate oxide layer 600 is formed between the gate polysilicon 700 and the inner wall of the first trench 100a. At this time, the gate polysilicon 700, the isolation structure 510 and the shielding gate polysilicon 410 constitute a split gate of the upper and lower structures.

[0096] In step S8, please refer to Fig.16 , ion implantation may be performed from above the substrate 100 using an ion implantation process.

[0097] In this embodiment, the patterned oxide mask layer 200 is used to replace the traditional ONO hard mask layer, so the degree of freedom in the subsequent process is relatively high, and the risk of SiN online contamination is avoided.

[0098] In one embodiment, please refer to Fig.11 In step S6, the isolation material layer 501 is etched. The remaining portion of the isolation material layer 501 inside the first trench 100a is used as an isolation structure 510. At the same time, the remaining portion of the isolation material layer 501 outside the first trench 100a is used as a self-aligned graphic structure 520. The self-aligned graphic structure 520 is spaced apart from the first trench 100a.

[0099] Different from the conventional method, the isolation material layer 501 on the substrate 100 is not completely removed here, but a self-aligned pattern structure 520 is simultaneously formed outside the first trench 100a.

[0100] Therefore, the present embodiment may include, in step S8: performing ion implantation on the substrate 100 based on the self-aligned pattern structure 520 to form source regions 10 on both sides of the first trench 100a. At this time, step S8 uses the self-aligned pattern structure 520 as an implantation protection layer to perform ion implantation to form source regions 10 on opposite sides of the first trench 100a.

[0101] Specifically, in step S8, please refer to Fig.16 , ion implantation can be performed from above the substrate 100, and the upper portion of the substrate 100 outside the self-aligned pattern structure 520 receives the implanted ions because there is no self-aligned pattern structure 520 to block it, so that a source region 10 is formed near the upper surface of the substrate 100 at this location.

[0102] In this embodiment, self-aligned implantation of the source region 10 is achieved through the self-aligned pattern structure 520. Therefore, compared with the source region formation process of the traditional device, the present embodiment can omit the photolithography, thereby improving the production efficiency and reducing the production cost.

[0103] In one embodiment, after etching away a portion of the isolation material layer 501, the thickness of the isolation structure 510 inside the first trench is set to T2. The trench opening width of the first trench 100a is W.

[0104] At this time, the thickness of the isolation material layer 501 inside the first trench 100a is set to T1 before etching away a portion of the isolation material layer 501. That is, in step S5, the filling height of the isolation material layer 501 in the first trench 100a is T1, and T1>T2+0.5W, thereby ensuring that after etching away a portion of the isolation material layer 501 in the subsequent step S6, the desired structure (isolation structure 510 or isolation structure 510 and self-aligned pattern structure 520, etc.) can be obtained.

[0105] In one embodiment, the method for manufacturing a split-gate trench MOSFET comprises, in step S4:

[0106] Step S41 , removing the patterned oxide mask layer 200 .

[0107] Step S42, forming a first oxide material layer 301 on the upper surface of the substrate 100 and the inner wall of the first trench 100a, please refer to Figure 4 ;

[0108] Step S43, filling the first trench 100a with a shielding gate polysilicon material layer 401, see Figure 5 ;

[0109] Step S44, etching back the shielding gate polysilicon material layer 401 to form a shielding gate polysilicon 410, please refer to Figure 7 ;

[0110] Step S45, etching the first oxide material layer 301 to form a first gate oxide layer 310, please refer to Fig. 9 .

[0111] Step S41: After the first trench 100a is formed by patterning the oxide mask layer 200 in step S3, the patterned oxide mask layer 200 is completely stripped off to facilitate the formation of subsequent device structures.

[0112] In step S42 , a first oxide material layer 301 may be formed by thermally oxidizing the side of the substrate 100 where the first trench 100 a is formed.

[0113] In step S44 , the upper surface of the shielding gate polysilicon 410 is lower than the upper surface of the substrate 100 .

[0114] In step S45, as an example, please refer to Fig. 9 , the first oxide material layer 301 is etched to form a first gate oxide layer 310, and a thinned oxide layer 320 connecting adjacent first gate oxide layers 310 is formed. The first gate oxide layer 310 is located between the shielding gate polysilicon 410 and the inner wall of the first trench 100a. The thickness of the thinned oxide layer 320 is less than the thickness of the first gate oxide layer 310.

[0115] That is, step S45 is to etch and thin the first oxide material layer 301 on the surface of the substrate 100 and the inner wall surface of the first trench 100a above the shielding gate polysilicon 410, and the thinned first oxide material layer 301 is used as the thinned oxide layer 320. The remaining first oxide material layer 301 that has not been thinned is used as the first gate oxide layer 310. At this time, while ensuring the performance of the device, the groove width of the upper half of the first trench 100a can be effectively widened, thereby greatly reducing the difficulty and entry threshold of the filling process of the isolation material layer 501, and facilitating the subsequent formation of the isolation material layer 501 in the first trench 100a. As an example, the thickness of the thinned oxide layer 320 can be

[0116] Of course, in the embodiment of the present application, the first oxide material layer 301 may not be etched to form a thinned oxide layer 320, or the thinned oxide layer 320 may be completely etched away, and the present application has no limitation on this.

[0117] In one embodiment, when the first gate oxide layer 310 is formed in step S4 , there may be a step difference between the upper surface of the shielding gate polysilicon 410 and the first gate oxide layer 310 .

[0118] Therefore, before step S5 , this embodiment further includes: performing additional etching on the shielding gate polysilicon 410 to eliminate the step difference between the upper surface of the shielding gate polysilicon 410 and the first gate oxide layer 310 .

[0119] For example, see Figure 8 In the above embodiment, when the first oxide material layer 301 is etched in step S45 to form the first gate oxide layer 310 and the thinned oxide layer 320, the upper surface of the shielding gate polysilicon 410 formed in step S44 may be slightly higher than the height of the first gate oxide layer 310 adjacent to it, thereby forming a step.

[0120] Therefore, after step S45 and before step S5, the shielding gate polysilicon 410 may be etched to remove the step, see Fig. 9 .

[0121] In one embodiment, before step S44, the process further includes: performing ion implantation on the substrate 100 to form a first well region 20 in the substrate 100. Figure 6 .

[0122] Ion implantation may be performed in the epitaxial layer 120 to form the first well region 20. The depth of the first well region 20 is less than the depth of the first trench 100a. In this case, the device well region may be formed simply and effectively.

[0123] In one embodiment, after step S45, the method further includes:

[0124] The structure obtained in step S45 (reference Fig. 9 ) is subjected to low temperature oxidation to form a low temperature oxide layer 800 on the surface of the shield gate polysilicon 410. While forming the low temperature oxide layer 800, a first well push is performed to transform the first well region 20 into the second well region 30 (reference Fig.10 ). The depth of the second well region 30 is greater than the depth of the first well region 20 and less than the depth of the first trench 100a.

[0125] At this time, on the one hand, the formation of the low temperature oxide layer 800 improves the device performance. On the other hand, the low temperature oxidation needs to heat the system, so the first well region 20 can be pushed to form the second well region 30.

[0126] The low temperature oxidation layer 800 may be made of the same material as the first oxidation material layer 301 and the isolation material layer 501. Fig.11In the subsequent step S6, when etching away a portion of the isolation material layer 501, the relevant portion of the thinned oxide layer 320 formed by the first oxide material layer 301 may also be etched away. Of course, the present application is not limited thereto, and the low temperature oxide layer 800 may also be made of different materials from the first oxide material layer 301 and the isolation material layer 501.

[0127] Further, step S7 may include: forming a second gate oxide layer 600 on the inner wall of the first trench 100a by thermal oxidation, and performing a second well push while forming the second gate oxide layer 600 to transform the second well region 30 into the third well region 40, please refer to Fig.12 .

[0128] Here, the depth of the third well region 40 is greater than the depth of the second well region 30 and less than the depth of the first trench 100a. Since the system needs to be heated during the thermal oxidation process, the second well region 30 can be further pushed to form the third well region 40. The source region 10 in the subsequent step can be specifically formed in the third well region 40.

[0129] At this time, the device well region can be fabricated through two well-pushing processes (the first well-pushing process and the second well-pushing process), thereby eliminating a separate well-pushing process and improving production efficiency.

[0130] In one embodiment, step S7 includes:

[0131] Step S71, forming a second gate oxide layer on the inner wall of the first trench 100a;

[0132] Step S72, forming a gate polysilicon material, the gate polysilicon material fills the first trench and covers the substrate and the self-aligned pattern structure, please refer to Fig.13 ;

[0133] Step S73, planarizing the polysilicon material 701, please refer to Fig.14 ;

[0134] Step S74, etching back the polysilicon material 701 to expose the substrate 100 and the self-aligned pattern structure 520. The gate polysilicon material 701 in the first trench 100a is the gate polysilicon. Fig.15 .

[0135] It is understandable that the polysilicon material 701 formed in step S72 is higher than the surface of the first trench 100a. In addition, after the polysilicon material 701 is formed, the top of the polysilicon material 701 is usually uneven due to the shape of the film structure of the remaining layer.

[0136] At this time, if the polysilicon material 701 outside the first trench 100a is directly etched back to remove, the polysilicon material 701 may remain on the inner wall of the self-aligned pattern structure 520, thereby causing device failure.

[0137] Therefore, in this embodiment, before the polysilicon material 701 outside the first trench 100 a is removed by etching back, the polysilicon material 701 is first planarized, thereby effectively avoiding the inner wall residue phenomenon and further improving the product yield.

[0138] As an example, a chemical mechanical polishing (CMP) process may be used to planarize the polysilicon material 701. Fig.14 , the isolation material layer 501 can be used as a grinding stop layer. The isolation material layer 501 is relatively thick, so the CMP can stop on the relatively thick isolation material layer 501, thereby reducing the process difficulty.

[0139] Of course, the planarization method of the polysilicon material 701 is not limited thereto, and it can also be planarized by other isotropic dry etching or wet etching methods, and this application is not limited thereto.

[0140] In one embodiment, after step S8, the method further includes:

[0141] Step S9, forming a dielectric layer 900, please refer to Fig.18 ;

[0142] Step S10, forming interconnection vias in the dielectric layer 900, please refer to Fig.19 ;

[0143] Step S11, forming a conductive plug 1000 in the interconnection through hole, please refer to Fig. 20 .

[0144] As an example, in step S9, please refer to Fig.17 , a covering dielectric material layer 901 may be formed first to cover the second gate oxide layer 600, the gate polysilicon 700 and the self-aligned pattern structure 520. Then, the covering dielectric material layer 901 is planarized to form a dielectric layer 900, which covers the second gate oxide layer 600, the gate polysilicon 700 and the self-aligned pattern structure 520. Please refer to Fig.18 .

[0145] As an example, in step S10, a photoresist may be first formed on the dielectric layer 900. Then, a photolithography process is performed to form interconnection vias in the dielectric layer 900. The interconnection vias extend into the substrate 100 (as an example, may extend to the third well region 40) and are located between the source regions 10 between adjacent first trenches 100a.

[0146] Further, step S10 may include: etching the dielectric layer 900, the self-aligned pattern structure 520 and the substrate 100 in sequence from the surface of the dielectric layer 900 to form interconnection vias. At this time, the removal of the self-aligned pattern structure 520 and the formation of the interconnection vias may be performed in the same step, thereby reducing the process steps.

[0147] As an example, in step S11 , the conductive plug 1000 may be a tungsten plug. The conductive plug 1000 is connected to the source region 10 so that the source region 10 receives a source voltage.

[0148] As an example, after step S11, processes such as front metal interconnection, passivation layer fabrication, back side thinning and metal fabrication may be performed to form a MOSFET.

[0149] In the above embodiment, the relevant contents in the active area A1 of the substrate 100 are mainly introduced. As mentioned above, in addition to the active area A1, the substrate 100 generally further has a terminal area A2 located outside the active area A1.

[0150] Based on this, in the embodiment of the present application, while forming the first trench 100a in step S3, a second trench 100b is also formed in the terminal area A2 (please refer to Figure 3 Step S4 forms a first gate oxide layer 310 on the inner wall of the first trench 100a and forms a terminal region isolation oxide layer 330 on the inner wall of the second trench 100b and the surface of the substrate 100 (see Fig. 9 Step S4 forms the shielding gate polysilicon 410 in the first trench 100a and forms the termination region polysilicon 420 in the second trench 100b (see Figure 7 ), the terminal region polysilicon 420 is surrounded by the terminal region isolation oxide layer 330 (please refer to Figure 8 Step S6 is to etch the isolation material layer 501. The remaining portion of the isolation material layer 501 in the first trench 100a is used as the isolation structure 510. The remaining portion of the isolation material layer 501 in the terminal area A2 is used as the terminal protection structure 530 (see Fig.11 ). The terminal protection structure 530 covers the second trench 100b of the terminal area A2.

[0151] It is worth noting here that in the manufacturing process of the separated-gate trench MOSFET in the embodiment of the present application, under corresponding process conditions, it is possible to simultaneously form the isolation structure 510, the self-aligned graphic structure 520 and the terminal protection structure 530, or it is possible to form only the isolation structure 510 and the terminal protection structure 530 without forming the self-aligned graphic structure 520.

[0152] When only the isolation structure 510 and the terminal protection structure 530 are formed without forming the self-aligned graphic structure 520, after ion implantation is performed on the substrate 100 in step S8 to form the source region 10 on both sides of the first trench 100a, when the interconnection through hole is formed in step S10, the dielectric layer 900 and the substrate 100 can be etched in sequence from the surface of the dielectric layer 900 to form the interconnection through hole.

[0153] It should be understood that, although the steps in the flowchart of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0154] In the description of this specification, please refer to the description of the terms "one embodiment", "ideal embodiment", etc. to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0155] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for manufacturing a split-gate trench MOSFET, characterized in that: include: providing a substrate; forming a patterned oxide mask layer on the upper surface of the substrate, wherein the patterned oxide mask layer includes an opening pattern, and the opening pattern defines the shape and position of the first trench; patterning the substrate based on the patterned oxide mask layer to form a first trench in the substrate; forming a first gate oxide layer and a shielding gate polysilicon in the first trench, wherein an upper surface of the shielding gate polysilicon is lower than an upper surface of the substrate, and the first gate oxide layer is formed between the shielding gate polysilicon and an inner wall of the first trench; forming an isolation material layer, wherein the isolation material layer fills the first trench and covers the substrate; Etching the isolation material layer, leaving a portion of the isolation material layer inside the first trench as an isolation structure, wherein the upper surface of the isolation structure is lower than the upper surface of the substrate; forming a second gate oxide layer and gate polysilicon in the first trench, wherein the gate polysilicon is located on the upper surface of the isolation structure, and the second gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; Performing ion implantation on the substrate to form source regions on both sides of the first trench; Before etching away a portion of the isolation material layer, the thickness of the isolation material layer inside the first trench is T1; After etching away a portion of the isolation material layer, the thickness of the isolation structure inside the first trench is T2; The groove opening width of the first groove is W; T1>T2+0.5W.

2. The method for manufacturing a split-gate trench MOSFET according to claim 1, wherein: The etching of the isolation material layer forms a self-aligned pattern structure on the remaining portion of the isolation material layer inside the first trench as an isolation structure, and also forms a self-aligned pattern structure on the remaining portion of the isolation material layer outside the first trench, wherein the self-aligned pattern structure is spaced apart from the first trench; The step of implanting ions into the substrate to form source regions on both sides of the first trench includes: Ion implantation is performed on the substrate based on the self-aligned pattern structure to form source regions on both sides of the first trench.

3. The method for manufacturing a split-gate trench MOSFET according to claim 1, wherein: The step of forming a first gate oxide layer and a shielding gate polysilicon in the first trench, wherein the upper surface of the shielding gate polysilicon is lower than the upper surface of the substrate, and the first gate oxide layer is formed between the shielding gate polysilicon and the inner wall of the first trench, comprises: removing the patterned oxide mask layer; forming a first oxide material layer on the upper surface of the substrate and the inner wall of the first trench; Filling a shielding gate polysilicon material layer in the first trench; Carving back the shielding gate polysilicon material layer to form the shielding gate polysilicon, wherein the upper surface of the shielding gate polysilicon is lower than the upper surface of the substrate; The first oxide material layer is etched to form the first gate oxide layer, and the first gate oxide layer is formed between the shielding gate polysilicon and the inner wall of the first trench.

4. The method for manufacturing a split-gate trench MOSFET according to claim 1 or 3, characterized in that: Before forming the isolation material layer, wherein the isolation material layer fills the first trench and covers the substrate, the method further comprises: The shielding gate polysilicon is additionally etched to eliminate the step difference between the upper surface of the shielding gate polysilicon and the first gate oxide layer.

5. The method for manufacturing a split-gate trench MOSFET according to claim 3, wherein: The step of etching back the shielding gate polysilicon material layer to form the shielding gate polysilicon, wherein the upper surface of the shielding gate polysilicon is lower than the upper surface of the substrate, further comprises: Ion implantation is performed on the substrate to form a first well region in the substrate; the depth of the first well region is less than the depth of the first trench.

6. The method for manufacturing a split-gate trench MOSFET according to claim 5, wherein: After the first oxide material layer is etched to form the first gate oxide layer, and the first gate oxide layer is formed between the shielding gate polysilicon and the inner wall of the first trench, the method further includes: forming a low temperature oxide layer on the surface of the shield gate polysilicon, and simultaneously performing a first well push to transform the first well region into a second well region, wherein the depth of the second well region is greater than the depth of the first well region and less than the depth of the first trench; The second gate oxide layer and gate polysilicon are formed in the first trench, the gate polysilicon is located on the upper surface of the isolation structure, and the second gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench, and further includes: A second well push-up is performed while the inner wall of the first trench is thermally oxidized to form the second gate oxide layer, so as to transform the second well region into a third well region, the depth of which is greater than that of the second well region and less than that of the first trench.

7. The method for manufacturing a split-gate trench MOSFET according to claim 2, wherein: The second gate oxide layer and gate polysilicon are formed in the first trench, the gate polysilicon is located on the upper surface of the isolation structure, and the second gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench, comprising: forming a second gate oxide layer on an inner wall of the first trench; forming a gate polysilicon material, wherein the gate polysilicon material fills the first trench and covers the substrate and the self-aligned pattern structure; planarizing the gate polysilicon material; The gate polysilicon material is etched back to expose the substrate and the self-aligned pattern structure, and the gate polysilicon material in the first trench is gate polysilicon.

8. The method for manufacturing a split-gate trench MOSFET according to claim 2, wherein: After the substrate is ion-implanted based on the self-aligned pattern structure to form source regions on opposite sides of the first trench, the method further includes: forming a dielectric layer, wherein the dielectric layer covers the second gate oxide layer, the gate polysilicon and the self-aligned pattern structure; forming an interconnection through hole in the dielectric layer, wherein the interconnection through hole extends into the substrate and is located between source regions between adjacent first trenches; A conductive plug is formed in the interconnection through hole.

9. The method for manufacturing a split-gate trench MOSFET according to claim 8, wherein: The forming of interconnection vias in the dielectric layer comprises: The dielectric layer, the self-aligned pattern structure and the substrate are sequentially etched from the surface of the dielectric layer to form the interconnection through-holes.

10. The method for manufacturing a split-gate trench MOSFET according to claim 1, wherein: The substrate has an active area and a terminal area located outside the active area; the first trench is formed in the active area; forming a second trench in the terminal region while forming the first trench; While forming a first gate oxide layer on the inner wall of the first trench, a terminal region isolation oxide layer is also formed on the inner wall of the second trench and the surface of the substrate; While forming shielding gate polysilicon in the first trench, terminal region polysilicon is also formed in the second trench, wherein the terminal region polysilicon is surrounded by the terminal region isolation oxide layer; The etching of the isolation material layer uses the remaining portion of the isolation material layer inside the first trench as an isolation structure, and also uses the remaining portion of the isolation material layer in the terminal area as a terminal protection structure, and the terminal protection structure covers the second trench in the terminal area.

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