Encapsulation structure

Abstract

The present invention provides a packaging structure, which includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive pin, and a packaging colloid. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive pin contacts at least one of the second circuit layer and the third circuit layer. The conductive pin has a vertical height, and the vertical height is greater than the vertical distance between the second circuit layer and the third circuit layer. The packaging colloid covers the first circuit board, the second circuit board, the electronic component, and the conductive pin. The packaging colloid exposes the first circuit layer and the fourth circuit layer, and the conductive pin extends outside the packaging colloid. The packaging structure of the present invention does not require the use of conductive gaskets, and can have a thinner packaging thickness and better heat dissipation effect.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a packaging structure. Background Art

[0002] To solve the heat dissipation problem, the new power module packaging structure has evolved to adopt a double-sided heat dissipation solution. Generally, because the power of the power module is large, relatively thick conductive pins (thickness greater than 0.5 mm) are required for signal transmission. However, the thickness of the power chip is only about 100 microns. Therefore, a conductive spacer is added between the upper and lower circuit boards to widen the distance between the upper and lower circuit boards to accommodate the conductive pins. In this way, in addition to increasing the overall thickness of the power module, the conductive spacer itself also has a thermal resistance, which affects the overall heat dissipation efficiency of the power module. Summary of the Invention

[0003] The present invention is directed to a packaging structure that does not require the use of a conductive spacer and can have a thinner packaging thickness and better heat dissipation effect.

[0004] According to an embodiment of the present invention, the packaging structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive pin, and a packaging colloid. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The second circuit layer and the third circuit layer are located between the first circuit layer and the fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board and is electrically connected to the second circuit layer and the third circuit layer. The conductive pin contacts at least one of the second circuit layer and the third circuit layer. The conductive pin has a vertical height, and the vertical height is greater than the vertical distance between the second circuit layer and the third circuit layer. The packaging colloid covers the first circuit board, the second circuit board, the electronic component, and the conductive pin. The packaging colloid exposes the first circuit layer and the fourth circuit layer, and the conductive pin extends outside the packaging colloid.

[0005] In the packaging structure according to an embodiment of the present invention, the above-mentioned first circuit board further includes a dielectric layer having an upper surface and a lower surface opposite to each other. The first circuit layer is disposed on the upper surface, and the second circuit layer is disposed on the lower surface.

[0006] In the packaging structure according to an embodiment of the present invention, the material of the above-mentioned dielectric layer includes a ceramic material or a thermal interface material (TIM).

[0007] In the packaging structure according to an embodiment of the present invention, the above-mentioned second circuit board further includes a dielectric layer having an upper surface and a lower surface opposite to each other. The third circuit layer is disposed on the upper surface, and the fourth circuit layer is disposed on the lower surface.

[0008] In the encapsulation structure according to an embodiment of the present invention, the material of the dielectric layer includes a ceramic material or a thermal interface material.

[0009] In the encapsulation structure according to an embodiment of the present invention, the first circuit board has a first edge and a second edge opposite to each other. The second circuit board has a third edge and a fourth edge opposite to each other. There is a first horizontal spacing between the first edge and the third edge, and a second horizontal spacing between the second edge and the fourth edge.

[0010] In the encapsulation structure according to an embodiment of the present invention, the size of the first circuit board is the same as the size of the second circuit board. At least one conductive pin includes a first conductive pin and a second conductive pin. The first conductive pin is relatively adjacent to the first edge of the first circuit board and contacts the second circuit layer. The second conductive pin is relatively adjacent to the fourth edge of the second circuit board and contacts the third circuit layer.

[0011] In the encapsulation structure according to an embodiment of the present invention, the first horizontal spacing is equal to the second horizontal spacing.

[0012] In the encapsulation structure according to an embodiment of the present invention, the size of the first circuit board is smaller than the size of the second circuit board. At least one conductive pin includes a first conductive pin and a second conductive pin. The first conductive pin is relatively adjacent to the third edge of the second circuit board and contacts the third circuit layer. The second conductive pin is relatively adjacent to the fourth edge of the second circuit board and contacts the third circuit layer.

[0013] In the encapsulation structure according to an embodiment of the present invention, the orthographic projection of the first circuit board on the second circuit board does not overlap with the orthographic projection of the first conductive pin on the second circuit board and the orthographic projection of the second conductive pin on the second circuit board.

[0014] In the encapsulation structure according to an embodiment of the present invention, the first horizontal spacing is greater than the second horizontal spacing.

[0015] In the encapsulation structure according to an embodiment of the present invention, the encapsulation structure further includes a solder layer, which is disposed between the second circuit layer of the first circuit board and the electronic component and between the electronic component and the third circuit layer of the second circuit board.

[0016] In the encapsulation structure according to an embodiment of the present invention, the encapsulation structure further includes a bonding wire, which electrically connects the electronic component and the third circuit layer of the second circuit board.

[0017] In the encapsulation structure according to an embodiment of the present invention, the electronic component includes at least one bare die or at least one package.

[0018] In the encapsulation structure according to an embodiment of the present invention, the above-mentioned encapsulation colloid has a top surface and a bottom surface that face each other. The top surface is flush with the first surface of the first circuit layer that is relatively far from the second circuit layer. The bottom surface is flush with the second surface of the fourth circuit layer that is relatively far from the third circuit layer.

[0019] Based on the above, in the design of the encapsulation structure of the present invention, the conductive pin contacts at least one of the second circuit layer of the first circuit board and the third circuit layer of the second circuit board, and the vertical height of the conductive pin is greater than the vertical distance between the second circuit layer and the third circuit layer. Thereby, the present invention does not need to use a conductive gasket to expand the distance between the first circuit board and the second circuit board. Therefore, the encapsulation structure of the present invention can have a thinner encapsulation thickness. In addition, since the encapsulation colloid exposes the first circuit layer of the first circuit board and the fourth circuit layer of the second circuit board, the encapsulation structure of the present invention can have a better heat dissipation effect. Description of the Drawings

[0020] Figure 1 is a schematic cross-sectional view of an encapsulation structure according to an embodiment of the present invention;

[0021] Figure 2 is a schematic cross-sectional view of an encapsulation structure according to another embodiment of the present invention.

[0022] Description of the Reference Numerals

[0023] 100a, 100b: Encapsulation structure;

[0024] 110a, 110b: First circuit board;

[0025] 111: Upper surface;

[0026] 112a, 112b: Dielectric layer;

[0027] 113: Lower surface;

[0028] 114a, 114b: First circuit layer;

[0029] 115: First surface;

[0030] 116a, 116b: Second circuit layer;

[0031] 120a, 120b: Second circuit board;

[0032] 121: Upper surface;

[0033] 122a, 122b: Dielectric layer;

[0034] 123: Lower surface;

[0035] 124a, 124b: Third circuit layer;

[0036] 125: The second surface;

[0037] 126a, 126b: The fourth circuit layer;

[0038] 130a, 130b: Conductive pins;

[0039] 132a, 132b: The first conductive pins;

[0040] 134a, 134b: The second conductive pins;

[0041] 140a, 140b, 150: Electronic components;

[0042] 145, 155: Solder layers;

[0043] 147: Bonding wires;

[0044] 160: Encapsulation gel;

[0045] 162: The top surface;

[0046] 164: The bottom surface;

[0047] D11, D12: The first horizontal spacing;

[0048] D21, D22: The second horizontal spacing;

[0049] H1, H2: Vertical heights;

[0050] G1, G2: Vertical spacings;

[0051] S1, S1’: The first edge;

[0052] S2, S2’: The second edge;

[0053] S3, S3’: The third edge;

[0054] S4, S4’: The fourth edge. Detailed implementation manners

[0055] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0056] Figure 1 is a schematic cross-sectional view of a packaging structure according to an embodiment of the present invention. Please refer to Figure 1, in this embodiment, the encapsulation structure 100a includes a first circuit board 110a, a second circuit board 120a, at least one conductive pin 130a, at least one electronic component (two electronic components 140a and 150 are schematically shown), and encapsulation colloid 160.

[0057] Specifically, the first circuit board 110a includes a dielectric layer 112a, a first circuit layer 114a, and a second circuit layer 116a. The dielectric layer 112a has an upper surface 111 and a lower surface 113 opposite to each other. The material of the dielectric layer 112a is, for example, a ceramic material or a thermal interface material. The thermal interface material is, for example, inorganic filler mixed in an organic resin, but is not limited thereto. The first circuit layer 114a is disposed on the upper surface 111 of the dielectric layer 112a and completely covers the upper surface 111. That is, the first circuit layer 114a is a non-patterned circuit layer as a whole. The second circuit layer 116a is disposed on the lower surface 113 of the dielectric layer 112a and exposes a part of the lower surface 113. That is, the second circuit layer 116a is a patterned circuit layer.

[0058] Furthermore, the second circuit board 120a of this embodiment includes a dielectric layer 122a, a third circuit layer 124a, and a fourth circuit layer 126a. The dielectric layer 122a has an upper surface 121 and a lower surface 123 opposite to each other. The material of the dielectric layer 122a is, for example, a ceramic material or a thermal interface material. The thermal interface material is, for example, inorganic filler mixed in an organic resin, but is not limited thereto. The third circuit layer 124a is disposed on the upper surface 121 of the dielectric layer 122a and exposes a part of the upper surface 121. That is, the third circuit layer 124a is a patterned circuit layer. The fourth circuit layer 126a is disposed on the lower surface 123 of the dielectric layer 122a and completely covers the lower surface 123. That is, the fourth circuit layer 126a is a non-patterned circuit layer as a whole.

[0059] As Figure 1As shown, the second circuit layer 116a of the first circuit board 110a in this embodiment and the third circuit layer 124a of the second circuit board 120a are located between the first circuit layer 114a and the fourth circuit layer 126a. Here, the size of the first circuit board 110a is substantially the same as that of the second circuit board 120a. Further, the first circuit board 110a has a first edge S1 and a second edge S2 that are opposite to each other. The second circuit board 120a has a third edge S3 and a fourth edge S4 that are opposite to each other. There is a first horizontal distance D11 between the first edge S1 and the third edge S3, and there is a second horizontal distance D21 between the second edge S2 and the fourth edge S4. Here, the first horizontal distance D11 is substantially equal to the second horizontal distance D21. That is to say, the first circuit board 110a and the second circuit board 120a in this embodiment are arranged in a staggered manner. On the other hand, the orthographic projection of the first circuit board 110a on the second circuit board 120a partially overlaps the second circuit board 120a.

[0060] Furthermore, the electronic components 140a and 150 in this embodiment are disposed between the first circuit board 110a and the second circuit board 120a and are electrically connected to the second circuit layer 116a and the third circuit layer 124a. Here, the electronic components 140a and 150 are, for example, bare chips or packages, which are not limited herein. More specifically, the packaging structure 100a in this embodiment further includes a solder layer 145 and a solder layer 155. The solder layer 145 is disposed between the second circuit layer 116a of the first circuit board 110a and the electronic component 140a and between the electronic component 140a and the third circuit layer 124a of the second circuit board 120a. The solder layer 155 is disposed between the second circuit layer 116a of the first circuit board 110a and the electronic component 150 and between the electronic component 150 and the third circuit layer 124a of the second circuit board 120a. In other words, the electronic components 140a and 150 in this embodiment are electrically connected to the first circuit board 110a and the second circuit board 120a through the solder layers 145 and 155.

[0061] Please refer to Figure 1, the conductive pins 130a of this embodiment are in contact with at least one of the second circuit layer 116a and the third circuit layer 124a. Specifically, the conductive pins 130a of this embodiment include a first conductive pin 132a and a second conductive pin 134a. The first conductive pin 132a has a vertical height H1, and there is a vertical spacing G1 between the second circuit layer 116a and the third circuit layer 124a. In particular, the vertical height H1 is greater than the vertical spacing G1. Similarly, the vertical height of the second conductive pin 134a is also greater than the vertical spacing G1. In other words, the conductive pins 130a of this embodiment are not located between the second circuit layer 116a of the first circuit board 110a and the third circuit layer 124a of the second circuit board 120a. Specifically, the first conductive pin 132a is relatively close to the first edge S1 of the first circuit board 110a and is in direct contact with the second circuit layer 116a. The second conductive pin 134a is relatively close to the fourth edge S4 of the second circuit board 120a and is in direct contact with the third circuit layer 124a. That is to say, the first conductive pin 132a is electrically connected to the second circuit layer 116a of the first circuit board 110a, and the second conductive pin 134a is electrically connected to the third circuit layer 124a of the second circuit board 120a. In other words, the first conductive pin 132a and the second conductive pin 134a are respectively connected to different circuit boards.

[0062] In addition, the encapsulation colloid 160 of this embodiment covers the first circuit board 110a, the second circuit board 120a, the electronic components 140a, 150, the first conductive pin 132a, and the second conductive pin 134a. In particular, the encapsulation colloid 160 exposes the first circuit layer 114a and the fourth circuit layer 126a, and the first conductive pin 132a and the second conductive pin 134a extend outside the encapsulation colloid 160. Further, the encapsulation colloid 160 has a top surface 162 and a bottom surface 164 that are opposite to each other. The top surface 162 is flush with the first surface 115 of the first circuit layer 114a that is relatively far from the second circuit layer 116a. The bottom surface 164 is flush with the second surface 125 of the fourth circuit layer 126a that is relatively far from the third circuit layer 124a. That is to say, the encapsulation colloid 160 of this embodiment does not completely cover the first circuit board 110a and the second circuit board 120a, but exposes the first circuit layer 114a and the fourth circuit layer 126a, which can effectively increase the heat dissipation effect of the encapsulation structure 100a. On the other hand, the encapsulation colloid 160 also does not completely cover the conductive pins 130a, and the part of the conductive pins 130a that extends outside the encapsulation colloid 160 can be used to transmit signals.

[0063] In short, the conductive pin 130a of the present embodiment contacts the second circuit layer 116a of the first circuit board 110a and the third circuit layer 124a of the second circuit board 120a, and the vertical height H1 of the first conductive pin 132a is greater than the vertical distance G1 between the second circuit layer 116a and the third circuit layer 124a. Thus, the present embodiment does not need to use a conductive gasket to open up the distance between the first circuit board 110a and the second circuit board 120a, so the package structure 100a of the present embodiment can have a thinner package thickness. In addition, because the packaging colloid 160 exposes the first circuit layer 114a of the first circuit board 110a and the fourth circuit layer 126a of the second circuit board 120a, the package structure 100a of the present embodiment can have a better heat dissipation effect.

[0064] It must be noted that the following embodiments use the same component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0065] Figure 2 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 1 as well as Figure 2 The packaging structure 100b of this embodiment is similar to the above-mentioned packaging structure 100a, and the difference between the two is that: in this embodiment, the size of the first circuit board 110b is smaller than the size of the second circuit board 120b.

[0066] In detail, the first circuit board 110b includes a dielectric layer 112b and a first circuit layer 114b and a second circuit layer 116b located on opposite sides of the dielectric layer 112b. The second circuit board 120b includes a dielectric layer 122b and a third circuit layer 124b and a fourth circuit layer 126b located on opposite sides of the dielectric layer 122b. A first horizontal distance D12 is provided between the first edge S1' of the first circuit board 110b and the third edge S3' of the second circuit board 120b, and a second horizontal distance D22 is provided between the second edge S2' of the first circuit board 110b and the fourth edge S4' of the second circuit board 120b. Here, the first horizontal distance D12 is greater than the second horizontal distance D22.

[0067] Furthermore, the conductive pins 130b of this embodiment include a first conductive pin 132b and a second conductive pin 134b. The first conductive pin 132b is relatively adjacent to the third edge S3' of the second circuit board 120b and directly contacts the third circuit layer 124b. The second conductive pin 134b is relatively adjacent to the fourth edge S4' of the second circuit board 120b and directly contacts the third circuit layer 124b. That is to say, the first conductive pin 132b and the second conductive pin 134b are electrically connected to the same circuit board (i.e., the second circuit board 120b). In particular, the first conductive pin 132b has a vertical height H2, there is a vertical spacing G2 between the second circuit layer 116b and the third circuit layer 124b, and the vertical height H2 is greater than the vertical spacing G2. Similarly, the vertical height of the second conductive pin 134b is also greater than the vertical spacing G2. That is to say, the first conductive pin 132b and the second conductive pin 134b are not located between the second circuit layer 116b of the first circuit board 110b and the third circuit layer 124b of the second circuit board 120b.

[0068] On the other hand, the orthographic projection of the first circuit board 110b of this embodiment on the second circuit board 120b does not overlap with the orthographic projection of the first conductive pin 132b on the second circuit board 120b and the orthographic projection of the second conductive pin 134b on the second circuit board 120b. As Figure 2 shown, the first circuit board 110b of this embodiment is located between the first conductive pin 132b and the second conductive pin 134b. In addition, the package structure 100b of this embodiment further includes a bonding wire 147, wherein the bonding wire 147 is electrically connected to the electronic component 140b and the third circuit layer 124b of the second circuit board 120b. That is to say, in addition to being electrically connected to the second circuit layer 116b and the third circuit layer 124b through the solder layer 145, the electronic component 140b of this embodiment is also electrically connected to the third circuit layer 124b through the bonding wire 147.

[0069] In short, in the design of the package structure 100b of this embodiment, the conductive pins 130b directly contact the third circuit layer 124b of the second circuit board 120b, and the vertical height H2 of the first conductive pin 132b is greater than the vertical spacing G2 between the second circuit layer 116b and the third circuit layer 124b. Thereby, the package structure 100b of this embodiment does not need to use conductive gaskets and can have a thinner package thickness. In addition, since the encapsulation colloid 160 exposes the first circuit layer 114b of the first circuit board 110b and the fourth circuit layer 126b of the second circuit board 120b, the package structure 100b of this embodiment can have better heat dissipation effect.

[0070] In summary, in the design of the packaging structure of the present invention, the conductive pin at least contacts one of the second circuit layer of the first circuit board and the third circuit layer of the second circuit board, and the vertical height of the conductive pin is greater than the vertical spacing between the second circuit layer and the third circuit layer. Thus, the present invention does not need to use a conductive gasket to open the distance between the first circuit board and the second circuit board, so the packaging structure of the present invention can have a thinner packaging thickness. In addition, because the packaging colloid exposes the first circuit layer of the first circuit board and the fourth circuit layer of the second circuit board, the packaging structure of the present invention can have a better heat dissipation effect.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An encapsulation structure, characterized in that, it includes: A first circuit board, including a first circuit layer and a second circuit layer; A second circuit board, including a third circuit layer and a fourth circuit layer, the second circuit layer and the third circuit layer being located between the first circuit layer and the fourth circuit layer; At least one electronic component, disposed between the first circuit board and the second circuit board, and electrically connected to the second circuit layer and the third circuit layer; At least one conductive pin, at least contacting one of the second circuit layer and the third circuit layer, wherein the at least one conductive pin has a vertical height, and the vertical height is greater than the vertical distance between the second circuit layer and the third circuit layer; and An encapsulation colloid, covering the first circuit board, the second circuit board, the at least one electronic component, and the at least one conductive pin, the encapsulation colloid exposing the first circuit layer and the fourth circuit layer, and the at least one conductive pin extending outside the encapsulation colloid.

2. The encapsulation structure according to claim 1, characterized in that, The first circuit board further includes a dielectric layer, having an upper surface and a lower surface opposite to each other, the first circuit layer being disposed on the upper surface, and the second circuit layer being disposed on the lower surface.

3. The encapsulation structure according to claim 2, characterized in that, The material of the dielectric layer includes a ceramic material or a thermal interface material.

4. The encapsulation structure according to claim 1, characterized in that, The second circuit board further includes a dielectric layer, having an upper surface and a lower surface opposite to each other, the third circuit layer being disposed on the upper surface, and the fourth circuit layer being disposed on the lower surface.

5. The encapsulation structure according to claim 4, characterized in that, The material of the dielectric layer includes a ceramic material or a thermal interface material.

6. The encapsulation structure according to claim 1, characterized in that, The first circuit board has a first edge and a second edge opposite to each other, the second circuit board has a third edge and a fourth edge opposite to each other, there is a first horizontal distance between the first edge and the third edge, and there is a second horizontal distance between the second edge and the fourth edge.

7. The encapsulation structure according to claim 6, characterized in that, The size of the first circuit board is the same as the size of the second circuit board, the at least one conductive pin includes a first conductive pin and a second conductive pin, the first conductive pin is relatively close to the first edge of the first circuit board and contacts the second circuit layer, and the second conductive pin is relatively close to the fourth edge of the second circuit board and contacts the third circuit layer.

8. The encapsulation structure according to claim 7, characterized in that, The first horizontal distance is equal to the second horizontal distance.

9. The encapsulation structure according to claim 6, characterized in that, The size of the first circuit board is smaller than that of the second circuit board. The at least one conductive pin includes a first conductive pin and a second conductive pin. The first conductive pin is relatively adjacent to the third edge of the second circuit board and contacts the third circuit layer, while the second conductive pin is relatively adjacent to the fourth edge of the second circuit board and contacts the third circuit layer.

10. The package structure according to claim 9, wherein, the orthographic projection of the first circuit board on the second circuit board does not overlap with the orthographic projection of the first conductive pin on the second circuit board and the orthographic projection of the second conductive pin on the second circuit board.

11. The package structure according to claim 9, wherein, the first horizontal spacing is greater than the second horizontal spacing.

12. The package structure according to claim 1, wherein, further comprising: a solder layer disposed between the second circuit layer of the first circuit board and the at least one electronic component and between the at least one electronic component and the third circuit layer of the second circuit board.

13. The package structure according to claim 12, wherein, further comprising: bonding wires electrically connecting the at least one electronic component and the third circuit layer of the second circuit board.

14. The package structure according to claim 1, wherein, the at least one electronic component includes at least one bare die or at least one package.

15. The package structure according to claim 1, wherein, the encapsulation colloid has a top surface and a bottom surface opposite to each other. The top surface is flush with the first surface of the first circuit layer relatively far from the second circuit layer, and the bottom surface is flush with the second surface of the fourth circuit layer relatively far from the third circuit layer.

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