Heterojunction bipolar transistor with buried trap-rich isolation region

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to a heterojunction bipolar transistor (HBT) with a buried trap-rich isolation region and a method for manufacturing the same. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap-rich isolation region embedded in a substrate below both the first and second heterojunction bipolar transistors.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to heterojunction bipolar transistors (HBTs) with buried trap-rich isolation regions and methods of fabricating the same. Background Art

[0002] A heterojunction bipolar transistor (HBT) is a type of bipolar junction transistor (BJT) that uses different semiconductor materials for the emitter and base regions, or the collector and base regions, to form a heterojunction. Si / SiGe HBTs are used in power amplifier applications due to their good RF performance, high breakdown voltage, and integration with CMOS.

[0003] High-performance devices can be implemented using HBTs. They are used in bipolar-based analog chips such as operational amplifiers, wideband variable-gain amplifiers, high-performance data converters (ADCs, DACs), etc. Due to latch-up and leakage issues, these high-performance devices require silicon-on-insulator (SOI) technology. For example, SOI can significantly improve latch-up sensitivity because there are no longer concerns about complex parasitic npnp structures and injection current paths. However, using SOI wafers significantly increases the cost of the manufacturing process, increases self-heating, and may produce stress-induced yield interactions. In addition, for simpler circuits with lower performance designs, SOI wafers are not required. Summary of the Invention

[0004] In an aspect of the present disclosure, a structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap-rich isolation region embedded in a substrate below both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

[0005] In aspects of the present disclosure, a structure includes: a bipolar heterojunction transistor; a field effect transistor adjacent to the bipolar heterojunction transistor; a shallow trench isolation structure separating the bipolar heterojunction transistor from the field effect transistor; and a trap-rich isolation region located below the bipolar heterojunction transistor and the field effect transistor and below the shallow trench isolation structure.

[0006] In aspects of the present disclosure, a structure includes: a first type of heterojunction bipolar transistor; a second type of heterojunction bipolar transistor, which is different from the first type of heterojunction bipolar transistor; a trap-rich isolation region embedded in a substrate below both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor; and an isolation region located within the substrate and below the trap-rich isolation region and the second type of heterojunction bipolar transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0008] Figure 1 A substrate having a trap-rich isolation region (eg, layer) and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0009] Figure 2 Shown are, among other features, a sub-collector region defined by a shallow trench isolation structure and a corresponding fabrication process according to aspects of the present disclosure.

[0010] Figure 3 Various devices over a trap-rich isolation region (eg, layer) and corresponding fabrication processes are shown, among other features, according to aspects of the present disclosure.

[0011] Figure 4 An alternative structure in which an n-type isolation region contacts the trap-rich isolation region and the sub-collector region of an HBT device and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0012] Figure 5-13 An alternative fabrication process and resulting structure including a complementary HBT device located above a trap-rich isolation region according to aspects of the present disclosure is shown ( Figure 13 ).

[0013] Figure 14 An alternative structure including a complementary HBT and a FET, each having an underlying trap-rich isolation region, is shown according to aspects of the present disclosure. DETAILED DESCRIPTION

[0014] The present disclosure relates to semiconductor structures, and more specifically, to heterojunction bipolar transistors (HBTs) with buried trap-rich isolation regions and methods for their fabrication. More specifically, the present disclosure relates to SiGe PNP HBTs and complementary SiGe NPN HBTs located above the trap-rich regions. Advantageously, the present disclosure provides improved thermal PNP and NPN solutions compared to SOI technology. Furthermore, the use of buried trap-rich isolation regions reduces and / or eliminates latch-up issues, leakage, and high-voltage swing compared to bulk technology. High-performance technology can also be integrated with FET switches and other devices (e.g., logic and low-noise amplifiers, etc.).

[0015] In an embodiment, a trap-rich isolation region, such as polysilicon, may be provided on a handle wafer below the crystalline silicon layer and below the PNP device and / or NPN device. For example, a SiGe PNP HBT and / or NPN HBT may be provided on a bulk wafer, such as one comprised of crystalline silicon, with the trap-rich isolation region located below the PNP device and / or NPN device. In an embodiment, the trap-rich isolation region contacts the shallow trench isolation structure of the two devices. The subcollector of the HBT may be contained within the shallow trench isolation structure, vertically separated from the trap-rich isolation region. In addition, a low-concentration doped region, such as an n-type isolation region, may be provided below the trap-rich isolation region of the HBT; although other alternative integration schemes are contemplated herein. As an example, the trap-rich isolation region may further separate regions for switches, logic, and low-power amplifier (LNA) FETs.

[0016] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. The methods, i.e., techniques, for manufacturing the structures disclosed herein have been adopted from integrated circuit (IC) technology. For example, these structures are built on wafers and are implemented as a film of material patterned on top of the wafer by a photolithographic process. Specifically, the fabrication of the structures uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film according to the mask.

[0017] Figure 1 A substrate having a trap-rich isolation region (eg, layer) and a corresponding fabrication process are shown, among other features. More specifically, Figure 1 The structure 10 includes a bulk substrate 12, which is preferably composed of a single-crystal Si material having any suitable crystal orientation (e.g., a (100), (110), (111), or (001) crystal orientation). The substrate 12 can have a high resistivity (e.g., 100 ohm-cm or greater) and can also be composed of other bulk single-crystal semiconductor materials, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. For discussion purposes, the substrate 12 is shown as having three distinct device regions: an HBT device region 100, a switch / LNA FET region 200, and a logic FET region 300.

[0018] Still refer to Figure 1, a shallow trench isolation structure 14 can be formed in the substrate 12. For example, a shallow trench isolation structure 14 can be formed in the HBT device region 100, the switch / LNA FET region 200, and the logic FET region 300. The shallow trench isolation structure 14 can be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art. By way of example, a resist formed above the substrate 12 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), can be used to form one or more trenches in the substrate 12 through the openings in the resist. After the resist is removed by a conventional oxygen ashing process or other known strippers, an insulator material, such as SiO2, can be deposited by any conventional deposition process, such as chemical vapor deposition (CVD), to form the shallow trench isolation structure 14. Any residual insulating material on the surface of the substrate 12 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0019] An isolation region 16 may be provided below the shallow trench isolation structure 14 in the HBT device region 100. In an embodiment, the isolation region 16 may be a highly doped region, such as an n-type implanted region. As shown, the isolation region 16 may be vertically located below the shallow trench isolation structure 14 and not contact it; instead, the substrate 12 separates the shallow trench isolation structure 14 from the isolation region 16. The isolation region 16 also extends to the surface of the substrate 12 located on one side of the shallow trench isolation structure 14 and is formed using a high-dose implantation process.

[0020] In an embodiment, the isolation region 16 can be formed by an implantation process, such as using n-type implantation. N-type dopants include, for example, arsenic (As), phosphorus (P), and Sb. In the implantation process, a patterned implantation mask can be used to define selected areas exposed for implantation of the isolation region 16, such as the HBT device region 100. The implantation mask can include a layer of photosensitive material, such as an organic photoresist, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and then developed with a chemical developer. The implantation mask also has a thickness and stopping capability sufficient to block the masked area from receiving a certain dose of implanted ions. The implantation mask can be stripped after implantation. Depending on the parameters of the implantation process, the isolation region 16 can diffuse into the substrate 12 to different depths below the shallow trench isolation structure 14 and not contact it.

[0021] Figure 1Also shown are separated trap-rich isolation regions 18 located in both the HBT device region 100 and the switch / LNA FET region 200. In one embodiment, the trap-rich isolation region 18 is discontinuous, for example, separated by the substrate 12, wherein the isolation region 16 can surround the trap-rich isolation region 18 in the device region 100. The trap-rich isolation region 18 can be a high-resistivity region, for example, higher than the resistivity of the substrate 12. In one embodiment, the trap-rich isolation region 18 contacts the shallow trench isolation structure 14 in both the HBT device region 100 and the switch / LNA FET region 200 to improve device-to-device isolation and significantly reduce substrate leakage. Furthermore, as shown, the trap-rich isolation region 18 in the HBT device region 100 can be vertically separated from the isolation region 16 by the material of the substrate 12. In this way, the trap-rich isolation region 18 in the HBT device region 100 does not contact the isolation region 16.

[0022] The trap-rich isolation region 18 may be a damaged silicon layer with high resistivity, such as a polycrystalline semiconductor material. In an embodiment, the trap-rich isolation region 18 is formed by an argon implantation process that uses a patterned implantation mask to define selected areas exposed for implantation, such as the HBT device region 100 and the switch / LNA FET region 200. Alternatively, the implantation process may use any non-dopant or inert gas element (e.g., Xe). The dose of the implant damages the substrate 12 while also ensuring recrystallization of any damaged semiconductor material that can be repaired in the regions 100, 200 by subsequent annealing. For example, the substrate 12 may be subjected to an argon implantation process of less than 1.0×10 17 cm -2 By way of further illustrative example, other implantation parameters are contemplated herein, including, for example, ion doses that may be less than or greater than 1.25×10 15 cm -2 or in 1×10 13 cm -2 to 5×10 16 cm -2 The depth of the trap-rich isolation region 14 can be adjusted according to the dose of the implantation process.

[0023] After the implantation process, an annealing process can be used to recrystallize the substrate 12 in the HBT device region 100 and the switch / LNA FET region 200. For example, the annealing process recrystallizes the trap-rich isolation region 14 into a single crystalline region. In particular, the thermal process repairs or heals damage to the semiconductor material of the modified layer (i.e., recrystallization or regrowth). For example, the annealing process can be a rapid thermal anneal (RTA) with a peak temperature in the range of 860°C to 1125°C and a dwell time at the peak temperature of 34 milliseconds to 60 seconds. In particular, the peak temperature can be 1000°C and the dwell time can be 5 seconds. In this way, the HBT device region 100 and the switch / LNA FET region 200 include the trap-rich isolation region 18 in contact with the shallow trench isolation structure 14.

[0024] Figure 2 A sub-collector region 20 in the HBT device region 100 is shown. The sub-collector region 20 can be a p-type sub-collector formed by an implantation process. In an embodiment, the p-type implant can be, for example, boron (B), which can be confined or constrained within the shallow trench isolation structure 14. To achieve this integration scheme, the patterned implant mask defines (e.g., exposes) the area between the shallow trench isolation structures 14 of the HBT device region 100. In addition, the energy and dose of the implant can be adjusted to ensure that there is no contact between the sub-collector region 20 and the trap-rich isolation region 18. Therefore, the trap-rich isolation region 18 in the HBT device region 100 can be vertically separated from the sub-collector region 20 by the substrate 12 (e.g., a single crystal semiconductor material).

[0025] Figure 3 Devices in each of regions 100, 200, and 300 are shown. For example, device regions 200 and 300 each include transistors 30 and 30a, respectively; while HBT device region 100 includes a SiGe PNP bipolar heterojunction transistor 32. In an embodiment, transistor 30 may be a switch or LNA FET disposed above a trap-rich isolation region 18; while transistor 30a may be a logic transistor without any trap-rich isolation region. Furthermore, as an example, SiGe bipolar heterojunction transistor 32 may be a SiGe power amplifier located above trap-rich isolation region 18.

[0026] Referring to regions 200, 300, transistors (e.g., FETs) 30, 30a each include a source / drain region 34 formed in an N-well 36. The source / drain regions 34 and the N-well 36 can be formed by conventional ion implantation processes well known in the art and require no further explanation for a complete understanding of the present disclosure. In an alternative example, the source / drain regions 34 can be elevated source and drain regions formed by a doped epitaxial process.

[0027] As further shown, the source / drain regions 34 and N-well 36 of transistors 30, 30a may be isolated by shallow trench isolation structure 14. Furthermore, the N-well 36 of transistor 30 may be isolated from the trap-rich isolation region 18; that is, the N-well 36 of transistor 30 does not contact the trap-rich isolation region 18.

[0028] The transistors 30, 30a can be formed using conventional gate formation processes, such as a gate first process or a replacement gate process. For example, in a gate first process, the gate dielectric material and the work function material are deposited and patterned using conventional CMOS manufacturing processes known in the art, so that no further explanation is required to fully understand the present disclosure. Sidewall materials, such as oxides or nitrides, can be formed on the patterned gate dielectric material and work function material using conventional deposition processes followed by anisotropic etching processes. The gate dielectric material can be a high-k gate dielectric material, such as HfO2. Examples of work function materials for p-channel FETs include Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co. Examples of work function materials for n-channel FETs include TiN, TaN, TaAlC, TiC, TiAl, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC. The work function material may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0029] In the HBT device region 100, the bipolar heterojunction transistor 32 includes an intrinsic layer 22 of Si material, such as a collector region, in direct contact with the sub-collector region 20. An insulator material 24 also surrounds a portion of the intrinsic layer 22 of Si material. A base region 38 can be formed on the intrinsic layer 22 of Si material, and an emitter region 40 can be formed on the base region 38. The base region 38 and the intrinsic layer 22 of Si material can be deposited by a conventional CVD process, followed by conventional photolithography and etching (e.g., patterning) processes. The base region 38 can be composed of a doped SiGe material, for example, a p-type dopant such as boron (B). It should be understood that the base region 38 can also have an intrinsic base and an extrinsic base layer.

[0030] As an example, the emitter region 40 can be a Si material. In an embodiment, the Si material can be doped with an n-type dopant, such as arsenic (As), phosphorus (P), and Sb, among other suitable examples. The emitter region 40 can be formed by a conventional CVD process, such as deposition, followed by conventional photolithography and etching (e.g., patterning) processes. As is well known in the art, sidewalls 42 are formed on the emitter region 40 (e.g., an oxide material).

[0031] After forming the corresponding devices in regions 100, 200, 300, a silicide process can be provided to form contacts to appropriate active regions, such as source / drain regions 34, base region 38, emitter region 40, isolation region 16, collector region 20, etc. As will be appreciated by those skilled in the art, the silicide process begins by depositing a thin layer of transition metal, such as nickel, cobalt, or titanium, on the fully formed and patterned device. After depositing the material, the structure can be heated to allow the transition metal to react with exposed silicon (or other semiconductor materials described herein) in the active regions (e.g., source, drain, etc.) of the semiconductor device to form a low-resistance transition metal silicide. After the reaction, any remaining transition metal can be removed by chemical etching, leaving silicide contacts in the active regions of the device.

[0032] Interlayer dielectric material 44 may be deposited over the device, with contacts 46 formed therein, such as to the silicide contacts in source / drain regions 34, base region 38, emitter region 40, isolation region 16, and collector region 20. Interlayer dielectric material 44 may be an oxide material deposited by a CVD process. Contacts 46 may be a metal or metal alloy material, preferably composed of tungsten. Contacts 46 are formed by forming trenches through interlayer dielectric material 44 using conventional photolithography and etching processes, followed by deposition of a conductive material within the trenches. Any residual material on interlayer dielectric material 44 may be removed by a CMP process.

[0033] Therefore, if Figure 3 As shown, n-type isolation region 16 and trap-rich isolation region 18 are vertically positioned below the PNP collector of HBT device 32, with n-type isolation region 16 not contacting trap-rich isolation region 18. The high-resistance regions of n-type isolation region 16 and trap-rich isolation region 18 reduce substrate leakage, device-to-device leakage, and improve collector-substrate breakdown and collector-to-subcollector capacitance (Ccs). Furthermore, the high-resistivity regions improve latch-up issues associated with bulk PNP HBTs. For example, by using buried trap-rich regions, Ccs can be reduced by approximately 27%, and substrate leakage can be reduced by a factor of 20, compared to conventional SiGe HBT devices.

[0034] Figure 4An alternative structure 10a is shown in which an isolation region 16a, such as an n-type isolation region, can be a well that contacts the trap-rich isolation region 18 and the sub-collector region 20 in the HBT device region 100. In this embodiment, the substrate 12 can be doped with n-type dopants to form an n-well, such as the isolation region 16a, which surrounds the shallow trench isolation structure 14 in the HBT device region 100. The trap-rich isolation region 18 and the sub-collector region 20 can be formed in the well 16a. The trap-rich isolation region 18 can be formed by argon implantation (or other non-dopant or inert gas); while the sub-collector region 20 can be formed by a p-type dopant implantation process. Figure 4 The remaining features with the same reference numerals as in Figure 3 The descriptions are similar such that no further explanation is necessary to fully understand the structure 10a.

[0035] Figure 5-13 The fabrication process and the resulting complementary HBT device located above the trap-rich isolation region are shown. More specifically, Figure 5 A structure 10b is shown including a substrate 12 having a trap rich isolation region 18 (e.g., a layer) embedded therein. As in previously disclosed embodiments, the substrate 12 can be composed of a single crystalline semiconductor material. In this embodiment, the trap rich isolation region 18 can be formed by a blanket ion implantation process of argon, a non-dopant, or an inert gas as already described herein. The depth of the trap rich isolation region 18 can be adjusted according to the parameters of the implantation process known in the art, such that no further explanation is required to fully understand the present disclosure. In an alternative embodiment, an ion implantation process of argon can be performed using a photomask to produce certain trap rich isolation regions on the wafer. After the implantation process, the substrate 12 undergoes an annealing process as already described herein to recrystallize the upper layer of the substrate 12 (e.g., the material above the trap rich isolation region 18).

[0036] Alternatively, a trap-rich isolation region 18 may be formed on the surface of substrate 12, followed by an epitaxial growth process to form another substrate material over the trap-rich isolation region 18. After the implantation process, substrate 12 may be subjected to a rapid annealing process to recrystallize the epitaxial substrate, leaving the trap-rich isolation region 18 embedded within the single-crystalline semiconductor material (and epitaxial substrate material) of substrate 12. In one embodiment, another epitaxial step may be implemented to grow single-crystalline silicon so that the sub-collector region 16 may be buried in the single-crystalline material. The thickness of this epitaxial step may be 0.1 μm to 2.0 μm, but other thicknesses are also possible.

[0037] like Figure 6As shown, a shallow trench isolation structure 14 can be formed in the HBT device regions 100a, 100b of the substrate 12. The shallow trench isolation structure 14 can be formed using conventional photolithography, etching, and deposition methods known to those skilled in the art and described above. A buried isolation region 16 can be provided below the shallow trench isolation structure 14 in the HBT device region 100b (e.g., the PNP device region). In an embodiment, the buried isolation region 16 can be an n-type implant and can be vertically separated from the trap-rich isolation region 18 by the substrate 12.

[0038] The n-type subcollector 50 can be formed between the shallow trench isolation structures 14 in the HBT device region 100a (e.g., the NPN device region). In addition, the p-type subcollector 52 can be formed between the shallow trench isolation structures 14 in the HBT device region 100b (e.g., the PNP device region). Similar to the other implantation processes described herein, the buried isolation region 16, the n-type subcollector 50, and the p-type subcollector 52 are formed by appropriately patterning the implantation mask and the corresponding dopant type. In an embodiment, both the n-type subcollector 50 and the p-type subcollector 52 can be confined or constrained within the shallow trench isolation structure 14 in addition to being separated from the trap-rich isolation region 18 below the shallow trench isolation structure 14. In an embodiment, the trap-rich isolation region 18 can be in contact with the shallow trench isolation structure 14.

[0039] Figure 7 The formation of the collector region according to aspects of the present disclosure, among other features, is shown. More specifically, as Figure 7 As shown, a hard mask 54 can be deposited on substrate 12, for example, above n-type sub-collector 50 and p-type sub-collector 52 in HBT device regions 100a, 100b. Hard mask 54 can be an oxide material deposited by a conventional CVD process. Conventional photolithography and etching processes known in the art can be used to form openings 56 in hard mask 54 to expose n-type sub-collector 50 in HBT device region 100a and p-type sub-collector 52 in HBT device region 100b. Collector regions 58, 58a can be epitaxially grown within openings 56 on the exposed semiconductor material of the respective n-type sub-collector 50 and p-type sub-collector 52. In an embodiment, collector regions 58, 58a can be an intrinsic semiconductor material, such as a Si material. A stack of materials, such as a nitride material 60 and an oxide material 62, is deposited over collector regions 58, 58a and hard mask material 54.

[0040] Figure 8A base region 38 is shown formed on the n-type sub-collector 50 in the HBT device area 100a. In an embodiment, the base region 38 can be an epitaxially grown single crystal SiGe material. The epitaxially grown SiGe material can be a doped p-type SiGe material. To grow the SiGe material, an opening 64 can be formed in the nitride material 60 and the oxide material 62 using conventional photolithography and etching processes to expose the underlying n-type sub-collector 50. The SiGe material can be epitaxially grown on the exposed n-type collector 58 to form a single crystal layer base region 38, wherein a polysilicon-based material 38a is formed on the oxide material 62. After the epitaxial growth process, a hard mask layer 66, such as a stack of nitride and oxide, can be deposited on the epitaxially grown materials 38, 38a by a conventional CVD process.

[0041] like Figure 9 As further shown, hard mask 66 and polysilicon-based material 38a can be patterned, for example, partially etched, to expose underlying mask, such as oxide material 62, over HBT device region 100b. An opening 70 can be formed in the stack of materials, such as nitride material 60 and oxide material 62, to expose underlying collector region 58a in HBT device region 100b. Base region 72 can be formed by growing semiconductor material in opening 70 and in contact with underlying collector region 58a for a PNP device. In an embodiment, the deposition process can be an epitaxial deposition process that forms single-crystalline material 72 within opening 70 and polysilicon material 72a on other surfaces of the mask. In an embodiment, the material used for base region 72 can be a doped or undoped SiGe material. In an integration scheme using doped SiGe material, the dopant will be an n-type dopant.

[0042] exist Figure 10A and Figure 10B In the embodiment, the mask 66 and polysilicon materials 38a and 72a in the HBT device region 100a are removed by photolithography and etching processes. In an embodiment, the polysilicon-based material 72a may remain on the oxide material 62 in the HBT device region 100b. Those skilled in the art will appreciate that the photolithography process includes a mask that blocks or prevents material from being etched above the HBT device region 100b. In addition, the etching process may be a selective etching process, which may be any known combination of dry and wet etching chemistries, so that the base region 38 above the HBT device region 100a is not corroded or removed.

[0043] After the material removal process, a polysilicon-based material 76 and an insulator material 74, such as an oxide, may be deposited and patterned on the exposed surfaces in the HBT device regions 100a and 100b. The patterning of these materials 74 and 76 forms a portion of an emitter region 78 on the base region 38 for the NPN device in the HBT device region 100a. The patterned materials 74 and 76 may also remain on the base region 72 of the PNP device in the HBT device region 100b. A semiconductor material 80 may be formed (e.g., deposited) over the base region 72 and the patterned materials 74 and 76. In one embodiment, the material 80 forms the emitter region of the PNP device in the HBT region 100b and the extrinsic base of the NPN device in the HBT device region 100a. The material 80 may be a P+-type material, such as silicon or SiGe, or a combination thereof, and may be doped with a p-type dopant, such as B. A capping layer 82 may be formed (e.g., deposited) over the metal material 80 using a conventional CVD process.

[0044] exist Figure 11 In the embodiment, a removal process, such as an etching process, forms trenches 84 in both HBT regions 100a and 100b. In one embodiment, the trenches 84 for the NPN device in HBT device region 100a expose the underlying oxide material 76 in the emitter region 78; while the trenches 84 for the PNP device in HBT device region 100b expose the oxide material 62. The etching process can be performed using conventional photolithography and etching processes, with the aid of a mask blocking the areas that are not removed. Sidewall material 86 can be formed (e.g., deposited) within the trenches, followed by an anisotropic etching process to remove material on any horizontal surfaces.

[0045] exist Figure 12 In the embodiment of the present invention, the etching process continues to remove oxide material 74 in emitter region 78, thereby exposing underlying base region 38. Additionally, the etching process removes exposed oxide material 62 in HBT device region 100b. Following this removal process, trench 84 for the NPN device in HBT device region 100a can be filled with semiconductor material 90 to complete emitter region 78. The semiconductor material can be an n-doped Si material deposited via a selective epitaxial growth process. Advantageously, the deposition process can also grow semiconductor material 90 on the exposed semiconductor material in base region 72 to form an extrinsic base region 91 for the PNP device in HBT device region 100b. Thus, a single deposition process can be used for both the extrinsic base region 91 of the PNP device and the emitter region 78 of the NPN device. Trench 84 can extend in both HBT device regions 100a and 100b to expose the n-type subcollector 50 and the p-type subcollector 56, respectively.

[0046] Figure 13The formation of contacts to the NPN and PNP devices in the HBT device regions 100a, 100b is shown. More specifically, after forming each device, a silicide process can be provided to form silicide contacts 92 to appropriate active regions of the two devices, such as the emitter, base, and collector regions. An interlayer dielectric material 94 can be deposited over the devices, wherein contacts 96 are formed to the silicide contacts in the emitter, base, and collector regions. The silicide contacts 92 and subsequently formed contacts 96 can be manufactured in the conventional manner already described above.

[0047] Figure 14 An alternative structure is shown including a complementary HBT and a FET, each of which has an underlying trap-rich isolation region. More specifically, Figure 14 The structure 10b includes an HBT region 100a, an HBT region 100b and a FET region 100c. In an embodiment, the HBT region 100a and the HBT region 100b include corresponding NPN devices and PNP devices, which have the same Figure 5-13 However, in structure 10b, the trap-rich isolation region 18 is now a separate region, e.g., a discontinuous region, for the HBT device regions 100a, 100b; however, the trap-rich isolation region 18 can be shared by the HBT device region 100b and the FET region 100c. In this embodiment, the FET region includes a FET structure 30, which is similar to Figure 3 and Figure 4 Furthermore, in this integration scheme, for each of the structures in each of regions 100a, 100b, 100c, the trap-rich isolation region 18 remains in contact with the shallow trench isolation structure 14 while also being separated from the well region 36 of the FET 30.

[0048] In addition, the buried isolation region 16b includes a shallow implant portion 16c extending to the surface of the substrate 12 ( Figure 1-3 ). Furthermore, in this integration scheme, the shallow implanted portion 16c of the isolation region 16b may be located between the shallow trench isolation structures 14. Furthermore, the contact 96 extends to the shallow implanted portion of the isolation region 16b and may make electrical contact therewith.

[0049] These structures can be utilized in system-on-chip (SoC) technology. Those skilled in the art will understand that an SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, the SoC consumes much less power and occupies much less area than a multi-chip design with the same functionality. As a result, SoC is becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0050] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the chips are mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0051] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or process improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; a trap-rich isolation region embedded in the substrate below both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor; as well as An isolation region is located in the substrate and below the trap-rich isolation region and the second heterojunction bipolar transistor.

2. The semiconductor structure according to claim 1, wherein The first heterojunction bipolar transistor and the second heterojunction bipolar transistor are complementary heterojunction bipolar transistors.

3. The semiconductor structure according to claim 2, wherein: The trap-rich isolation region includes a polysilicon crystalline semiconductor material embedded within a single crystalline semiconductor material.

4. The semiconductor structure according to claim 3, wherein: The polysilicon crystalline semiconductor material is located below shallow trench isolation structures for both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor, and the isolation region includes an n-type isolation region located below and separated from the polysilicon crystalline semiconductor material.

5. The semiconductor structure according to claim 3, further comprising: A first sub-collector region located below the first heterojunction bipolar transistor and a second sub-collector region located below the second heterojunction bipolar transistor, wherein the first sub-collector region and the second sub-collector region are separated from the polycrystalline silicon crystalline semiconductor material by the single crystal semiconductor material and are contained in a shallow trench isolation structure. The semiconductor structure according to claim 5 , wherein: The first sub-collector region and the second sub-collector region have different dopant types.

7. The semiconductor structure according to claim 3, further comprising: The emitter region of the first heterojunction bipolar transistor and the base region of the second heterojunction bipolar transistor include the same material.

8. The semiconductor structure according to claim 3, wherein: The trap-rich isolation region includes a single trap-rich isolation region for both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

9. The semiconductor structure according to claim 8, wherein The isolation region includes a doped isolation region located below the second heterojunction bipolar transistor and separated from the second heterojunction bipolar transistor by the single crystalline semiconductor material.

10. The semiconductor structure according to claim 3, wherein The trap-rich isolation region includes an isolation region for separation of the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

11. The semiconductor structure according to claim 10, further comprising: A field effect transistor adjacent to the second heterojunction bipolar transistor, the field effect transistor, the first heterojunction bipolar transistor and the second heterojunction bipolar transistor share the trap-rich isolation region.

12. A semiconductor structure comprising: a first bipolar heterojunction transistor; a second bipolar heterojunction transistor; a field effect transistor adjacent to the second bipolar heterojunction transistor; a shallow trench isolation structure separating the first bipolar heterojunction transistor from the second bipolar heterojunction transistor and separating the second bipolar heterojunction transistor from the field effect transistor; a trap-rich isolation region located below the first bipolar heterojunction transistor, the second bipolar heterojunction transistor, and the field-effect transistor, and below the shallow trench isolation structure; as well as An n-type isolation region is located below the trap-rich isolation region and the second bipolar heterojunction transistor.

13. The semiconductor structure according to claim 12, wherein: The trap-rich isolation region contacts the shallow trench isolation structure.

14. The semiconductor structure according to claim 12, wherein: The trap-rich isolation region includes polysilicon crystalline material shared between the second bipolar heterojunction transistor and the field effect transistor.

15. The semiconductor structure according to claim 12, wherein: The second bipolar heterojunction transistor includes a p-type sub-collector region located between the shallow trench isolation structures.

16. The semiconductor structure according to claim 15, wherein A substrate material is vertically located between the p-type sub-collector region and the trap-rich isolation region such that the trap-rich isolation region does not contact the p-type sub-collector region.

17. The semiconductor structure according to claim 15, wherein The second bipolar heterojunction transistor is complementary to the first bipolar heterojunction transistor, wherein the trap-rich isolation region is located below and separated from the p-type sub-collector region of the second bipolar heterojunction transistor and above the n-type isolation region.

18. A semiconductor structure comprising: A first type of heterojunction bipolar transistor; a second type of heterojunction bipolar transistor, which is different from the first type of heterojunction bipolar transistor; a trap-rich isolation region embedded in the substrate below both the first type of heterojunction bipolar transistor and the second type of heterojunction bipolar transistor; as well as An isolation region is located in the substrate and below the trap-rich isolation region and the second-type heterojunction bipolar transistor.

19. The semiconductor structure according to claim 18, wherein The trap-rich isolation region includes a shared polysilicon crystal layer, and the second isolation region includes an n-type material separated from the shared polysilicon crystal layer.

20. The semiconductor structure of claim 18, wherein The trap-rich isolation region includes a separated polysilicon crystal layer, and the second isolation region includes an n-type material separated from the separated polysilicon crystal layer.

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