Semiconductor device and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof, which comprises a semiconductor substrate, a capacitive contact plug formed on the semiconductor substrate, and a capacitor formed on the capacitive contact plug and comprising a lower electrode, a capacitive dielectric layer and an upper electrode, wherein the lower electrode is stacked in the capacitive dielectric layer by using a damascene process, the capacitor manufacturing process is simplified, and the integration of the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Capacitors are indispensable important elements in DRAMs. With the increase of DRAM integration and the gradual reduction of size, capacitors need to be prepared in a small area, and the increase of capacitor aspect ratio and other situations finally make the production of capacitors extremely difficult. SUMMARY

[0003] The present application at least partially solves the above technical problems in the related art. To this end, the present application provides a semiconductor device and a preparation method thereof to solve the above technical problems.

[0004] To achieve the above object, the first aspect of the present application provides a semiconductor device, further comprising:

[0005] a semiconductor substrate;

[0006] a capacitor contact plug formed on the semiconductor substrate;

[0007] a capacitor formed on the capacitor contact plug, comprising a lower electrode, a capacitor dielectric layer and an upper electrode, the lower electrode is connected with the capacitor contact plug, wherein the lower electrode is stacked in the capacitor dielectric layer by using damascene process.

[0008] The second aspect of the present application provides a preparation method of a semiconductor device, comprising the following steps:

[0009] providing a semiconductor substrate;

[0010] forming a capacitor contact plug on the semiconductor substrate;

[0011] forming a multi-layer dielectric layer on the capacitor contact plug;

[0012] filling Cu in each of the dielectric layers by using damascene process to form a lower electrode;

[0013] forming an upper electrode. BRIEF DESCRIPTION OF DRAWINGS

[0014] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the present application. Moreover, the same reference numerals in the attached drawings indicate the same or similar components. In the drawings:

[0015] Figure 1 This illustration shows a schematic diagram of the structure after the first portion of the lower electrode is formed in one embodiment of this application;

[0016] Figure 2 It shows in Figure 1 A schematic diagram of the structure after the second etching stop layer is formed on the basis of the above.

[0017] Figure 3 It shows in Figure 2 A schematic diagram of the structure after the second trench is formed on the basis of the previous structure;

[0018] Figure 4 It shows in Figure 3 A schematic diagram of the structure after the third etching stop layer is formed on the basis of the above.

[0019] Figure 5 It shows in Figure 4 This is a schematic diagram of the structure after the final etch stop layer is formed on the basis of the previous layer.

[0020] Figure 6 It shows in Figure 5 A schematic diagram of the structure after forming electrode trenches based on the above;

[0021] Figure 7 It shows in Figure 6 A schematic diagram of the structure after the upper electrode is formed based on the above;

[0022] Figure 8 Another embodiment of this application is shown in Figure 2 A schematic diagram of the structure after the trench is formed based on the above.

[0023] Figure 9 It shows in Figure 8 Based on this, a schematic diagram of the structure after the first part of the upper electrode is formed;

[0024] Figure 10 It shows in Figure 9 A schematic diagram of the structure after the first part of the upper electrode has been processed by electrode separation based on the above;

[0025] Figure 11 It shows in Figure 10 A schematic diagram of the structure after depositing a dielectric layer and forming wiring trenches on the basis of the above.

[0026] Figure 12 It shows in Figure 11 Based on this, a schematic diagram of the structure after forming the second lower electrode and the trench is shown. Detailed Implementation

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary of the present disclosure, but not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known functions and constructions are omitted to avoid obscuring the concept of the present disclosure in unnecessary detail.

[0028] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are shown exaggerated in scale or omitted in the interest of clarity and conciseness, in which the shapes and relative sizes of the various regions, layers, and elements shown in the drawings are merely exemplary, and can be varied in actual implementation due to manufacturing tolerances and technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0029] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed.

[0030] Please refer to Figure 7 The first aspect of the present application provides a semiconductor device 100, wherein the semiconductor device 100 comprises a semiconductor substrate, a capacitor contact plug 11, a capacitor dielectric layer formed by a plurality of dielectric layers 12 stacked together, an etching stop layer 13, a lower electrode 14, and an upper electrode 15, wherein the etching stop layer 13 is disposed between adjacent two dielectric layers 12 and between the bottom dielectric layer and the capacitor contact plug 11, the lower electrode 14, the upper electrode 15, and the dielectric layer 12 capacitor contact plug 11 are formed on the semiconductor substrate, the dielectric layer 12 is formed on the semiconductor substrate, the material of the lower electrode 14 is Cu, the lower electrode 14 is embedded in the capacitor dielectric layer and penetrates the bottom etching stop layer 13 and the capacitor contact plug 11 to realize electrical connection, the lower electrode 14 is formed in the dielectric layer 12 by Damascene process, and the upper electrode 15 penetrates all the dielectric layers 12 and part of the etching stop layer until it contacts the bottom etching stop layer, so that the upper electrode 15, the dielectric layer 12, and the upper electrode 15 constitute a capacitor in the semiconductor device 100.

[0031] The dielectric layer 12 can be an interlayer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer, and can include oxide, nitride, oxynitride, or a combination thereof, or can include a low k material such as fluorinated silicate glass (FSG), carbon doped oxide, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), or fluorine tetra-ethyl-orthosilicate (FTEOS). The dielectric layer 12 can be formed using, for example, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), high density plasma CVD (HDPCVD), or other conventional deposition techniques.

[0032] The etching stop layer 13 is disposed between the dielectric layer 12 and the semiconductor substrate, and between two adjacent dielectric layers 12, and the lower electrode 14 is formed by a plurality of partial lower electrodes stacked in each dielectric layer 12, and vertically penetrates through the dielectric layers 12 and the etching stop layers 13, and a plurality of partial lower electrodes are embedded in each dielectric layer 12 by a damascene process, and the plurality of partial lower electrodes are stacked and connected end to end to form the entire lower electrode 14.

[0033] It is worth mentioning that the positions of the partial lower electrodes in the adjacent dielectric layers 12 correspond, and the upper electrode 15 includes a horizontal portion and a vertical portion, wherein the horizontal portion can cover the top dielectric layer, and the vertical portion penetrates through all the dielectric layers 12 and the partial etching stop layers 13 from top to bottom until it contacts the bottom etching stop layer.

[0034] It should be noted that the stacked structure formed by the plurality of partial lower electrodes in the dielectric layer 12 can all be used as the lower electrode 14 of the capacitor, as described above in the embodiment, of course, a part of the stacked structure can also be used as the lower electrode 14 of the capacitor, at this time, the penetration depth of the vertical portion of the upper electrode 15 needs to be adjusted, that is, the penetration depth of the upper electrode 15 is at the same level as the partial lower electrode required as the capacitor.

[0035] In this way, a capacitor is formed between the lower electrode 14, the multi-layer dielectric layer (i.e., the capacitor dielectric layer), and the upper electrode 15.

[0036] Compared with the prior art, the present embodiment utilizes the principle of forming Cu metal wiring by Damascene process to form a multi-segment Cu material portion lower electrode in each layer of dielectric layer 12 by using multiple Damascene process, thereby simplifying the manufacturing process of the lower electrode 14, and making the manufacturing of the capacitor not limited by height, thereby improving the integration of the semiconductor device.

[0037] The manufacturing method of the semiconductor device 100 in the present embodiment is described below.

[0038] The present application provides a manufacturing method of a semiconductor device 100, comprising the following steps:

[0039] As shown in Figure 1 A semiconductor substrate is provided, which can include, for example, a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V semiconductor compound such as GaP, GaAs, GaSb. In some embodiments, the semiconductor substrate can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0040] When the semiconductor substrate is a silicon-based semiconductor substrate, the semiconductor substrate can include, for example, dangling bond silicon atoms that do not bond with oxygen ions. The operating characteristics of the transistor can be stabilized by a hydrogen annealing process, in which hydrogen atoms bond with the dangling bond silicon atoms of the semiconductor substrate. In this case, the hydrogen atoms can easily separate from the silicon atoms, but boron can increase the binding energy between the silicon atoms and the hydrogen atoms. Therefore, the variable retention time or charge retention time of the capacitor can be improved.

[0041] Next, a capacitor contact plug 11 is formed on the semiconductor substrate by a conventional etching and deposition process.

[0042] Next, a layer of etching stop layer 13 can be formed on the semiconductor substrate by a deposition process, which can be defined as a first layer of etching stop layer 13.

[0043] Next, a layer of dielectric layer 12 can be formed on the etching stop layer 13 by depositing a low-k material having a dielectric constant lower than that of silicon oxide (SiO2). In an example embodiment, the dielectric layer 12 can be silicon oxide including carbon and hydrogen (SiCOH). For example, the dielectric layer 12 can include about 10% to about 50% carbon. In some example embodiments, the dielectric layer 12 can include fluorine-doped silicon oxide (F-SiO2) or porous silicon oxide.

[0044] Then, the dielectric layer 12 and the etching stop layer 13 are etched using an etching mask plate (not shown) to expose the upper surface of the capacitor contact plug 11, so as to form a first groove penetrating through the dielectric layer 12 and the etching stop layer 13, and form a partial lower electrode on the dielectric layer 12 and filling the first groove, which can be defined as a first partial lower electrode 140. In the example embodiment, Damascene process can be used to fill Cu as the first partial lower electrode 140 in the first groove.

[0045] Then, as shown in Figure 2 , the first partial lower electrode 140 above the dielectric layer 12 is planarized to expose the dielectric layer 12, and a layer of etching stop layer 13 is formed on the dielectric layer 12 using deposition process, which can be defined as a second layer of etching stop layer 13.

[0046] Then, as shown in Figure 3 , a dielectric layer 12 is formed on the etching stop layer 13 using deposition process, which can be defined as a second dielectric layer, and the second dielectric layer and the second layer of etching stop layer are etched using an etching mask plate 200 to expose the upper surface of the first partial lower electrode 140, so as to form a second groove penetrating through the second dielectric layer and the second layer of etching stop layer.

[0047] Then, as shown in Figure 4 , the etching mask plate 200 is removed, and Damascene process is continued to form a partial lower electrode 14 on the dielectric layer 12 covering the dielectric layer 12 and filling the second groove, which can be defined as a second partial lower electrode 141. Then, the second partial lower electrode 141 above the dielectric layer 12 is planarized to expose the dielectric layer 12, and a layer of etching stop layer 13 is formed on the dielectric layer 12 using deposition process, which can be defined as a third layer of etching stop layer.

[0048] Then, as shown in Figure 5 , the steps involved in Figure 3 , and Figure 4 are repeated several times until the last partial lower electrode and the last layer of etching stop layer are formed, and the first partial lower electrode 140 to the last partial lower electrode are stacked to form a stacked structure, reach a certain stacking height, and the adjacent partial lower electrodes are connected to form a complete capacitor lower electrode.

[0049] Then, as shown in Figure 6 , all the dielectric layers 12 and etching stop layers 13 are etched using the etching mask plate 200 until the surface of the first layer of etching stop layer is exposed to form an electrode groove 300.

[0050] Then, as shown in Figure 7As shown, an upper electrode 15 is deposited on the electrode trench 300 and the top dielectric layer, and a capacitor is formed between the lower electrode 14, the multilayer dielectric layer 12 (i.e., the capacitor dielectric layer) and the upper electrode 15.

[0051] It should be noted that in the above capacitor formation process, the upper electrode of the capacitor is formed after all the lower electrodes 14 and the etch stop layer 13 are stacked, and then... Figure 6 During the etching process, it is difficult to etch multiple dielectric layers 12 and etching stop layers 13. In order to simplify the etching process, this application proposes another method for fabricating a semiconductor device 100.

[0052] The methods for the first two steps can be referenced as follows: Figures 1-2 The method shown in this embodiment will not be described in detail here;

[0053] Next, as Figure 8 As shown, an etching mask 200 is used to etch the dielectric layer 12 and the etch stop layer 13, exposing the surface of the first etch stop layer to form a trench 16;

[0054] Next, as Figure 9 As shown, the etching mask 200 is removed, and a partial upper electrode is deposited on the trench 16 and the first dielectric layer, which can be defined here as the first partial upper electrode 150.

[0055] Next, as Figure 10 As shown, the first part of the upper electrode 150 is subjected to electrode separation processing. Specifically, the first part of the upper electrode 150 can be exposed by etching back or planarization processing.

[0056] Next, the above steps are repeated to form a second upper electrode 151 above the first upper electrode 150, including the following steps:

[0057] Next, as Figure 11 As shown, the dielectric layer 12 is deposited, and the dielectric layer 12 and the etching stop layer 13 are etched using the etching mask 200 to expose the surface of the first part of the lower electrode 140 to form a wiring trench 18.

[0058] Next, as Figure 12As shown, the etching mask plate 200 is removed, and a second partial lower electrode 141 is formed on the dielectric layer 12 and fills the wiring groove 18, specifically, in an example embodiment, a damascene process or a deposition process can be used to form a layer of the second partial lower electrode 141 in the wiring groove 18, and then the second partial lower electrode 141 is planarized to expose the dielectric layer 12, and a deposition process is used to form an etching stop layer 13 on the dielectric layer 12, which can be defined as a third etching stop layer;

[0059] Next, with reference to Figure 12 , the dielectric layer 12 and the etching stop layer 13 are etched using the etching mask plate 200 to expose the surface of the first partial upper electrode 150 to form a groove 16;

[0060] Next, the operations shown in Figure 9 , as shown in Figure 10 , the second partial upper electrode is formed above the first partial upper electrode.

[0061] Next, with reference to Figure 7 , the above steps are repeated multiple times, and when the last partial upper electrode is formed, only the electrode material is deposited without electrode segmentation processing, i.e., without the operation shown in Figure 10 , at this time, the first partial upper electrode and the last partial upper electrode are connected to form a complete capacitor upper electrode.

[0062] The semiconductor device in the embodiment can be a volatile memory device such as a DRAM device, an SRAM device, or a non-volatile memory device such as a Flash device, a PRAM device, an MRAM device, an RRAM device, etc.

[0063] Further, the chip with the above semiconductor device can be used in various electronic devices, specifically, the electronic device can be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, a mobile power supply, etc.

[0064] In the above description, the patterning, etching, and other technical details of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0065] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Also includes: Semiconductor substrate; Capacitive contact plugs are formed on the semiconductor substrate; A capacitor, formed on the capacitor contact plug, includes a lower electrode, a capacitor dielectric layer, and an upper electrode. The lower electrode is connected to the capacitor contact plug. The capacitor dielectric layer includes multiple layers of dielectric layers stacked together. Multiple segments of Cu material are formed in each dielectric layer using a multi-stage damascus inlay process. These multiple segments of lower electrodes are stacked together and connected end to end to form the entire lower electrode.

2. The semiconductor device according to claim 1, characterized in that, An etch stop layer is formed between two adjacent dielectric layers, and the lower electrode passes through the etch stop layer and is connected to the capacitor contact plug.

3. The semiconductor device according to claim 2, characterized in that, The upper electrode penetrates the dielectric layer and connects to the etch stop layer at the bottom.

4. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Provide a semiconductor substrate; A capacitive contact plug is formed on the semiconductor substrate; A multilayer dielectric layer is formed on the capacitor contact plug; Multiple segments of Cu are filled in each dielectric layer by employing a multi-stage damascus inlay process to form a partial lower electrode. Multiple partial lower electrodes are stacked and connected end to end to form the entire lower electrode. The upper electrode is formed.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, Forming an electric current The steps involved include: After each dielectric layer is formed, Cu is filled into the dielectric layer using a damascus inlay process to form a partial lower electrode. This process is repeated several times until a complete lower electrode is formed.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, After each partial lower electrode is formed, an etch barrier layer is formed on the partial lower electrode, the lower electrode penetrating each etch barrier layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The upper electrode is formed in one step, and the steps for forming the upper electrode include: All dielectric layers and part of the etching barrier layer are etched to expose the underlying etching barrier layer to form an upper electrode trench, and electrode material is formed on the lower electrode and within the upper electrode trench.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, Use a mask to etch all the dielectric layers and part of the etching barrier layer.

9. The method for fabricating a semiconductor device according to claim 6, characterized in that, The upper electrode is formed through multiple steps. The steps of forming the upper electrode include: after each etching barrier layer is formed on the dielectric layer, the dielectric layer and the etching barrier layer are etched from top to bottom to form a first upper electrode trench; electrode material is deposited in the dielectric layer and the first upper electrode trench; then electrode separation is performed to expose the dielectric layer to form a partial upper electrode; the above operation is repeated multiple times, wherein, in the last operation, only electrode material is deposited and no electrode separation is required, and finally a complete upper electrode is formed.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, A mask is used for each etching of the dielectric layer and the barrier layer.

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