A high radiation resistance SiC MOSFET device structure and preparation method

Abstract

The present invention belongs to the field of semiconductor technology, and specifically relates to a new structure of a SiC MOSFET device with high radiation resistance. The cell structure of the novel planar gate SiC MOSFET device includes: a drain metal electrode, an N+ type substrate and an N drift region; a carrier storage layer and a P base region are arranged on the top of the N drift region (3); a P type barrier region (6) and a P+ region (8) are arranged in the carrier storage layer one (4); a carrier storage layer two (41) is located between the P type barrier region (6) and the P+ region (8); an N+ region (7) and a P+ region (8) are arranged in the P base region (5), and the N+ region (7) and the P+ region (8) are connected to a source metal electrode (11). The present invention improves the total dose radiation (gamma rays, etc.) and single particle radiation resistance of the SiC MOSFET device, and can be applied in extreme space environments such as aerospace.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC MOSFET device structure with high radiation resistance and a preparation method thereof. Background Art

[0002] Traditional Si devices have already approached their theoretical limits and are difficult to operate in various harsh environments with extremely high temperature, high pressure, high frequency, and strong radiation. However, SiC has superior physical and electrical properties, such as high critical breakdown electric field, wide bandgap, and high electron saturation drift velocity, and is suitable for high-frequency, high-voltage, high-temperature, and high-radiation power electronics. Among them, SiC MOSFET is one of the fastest-growing power semiconductor devices.

[0003] At present, SiC MOSFET can be applied to various fields of national production, including aerospace exploration fields such as satellites, space stations and space probes. These fields are full of various radiations, mainly including photon radiation, neutron radiation and single particle radiation. Various high-energy radiation particles can penetrate and affect device characteristics, and seriously cause device failure or damage. How to improve the radiation resistance of SiC MOSFET has become one of the current research hotspots. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art, make improvements on the structure of the traditional planar gate SiC MOSFET, and provide a high radiation resistance SiC MOSFET device structure, whose radiation resistance is significantly improved compared with the traditional planar gate SiC MOSFET.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A SiC MOSFET device structure with high radiation resistance, wherein the cell structure of the planar gate SiC MOSFET device comprises: a drain metal electrode (1), an N+ type substrate (2) and an N-drift region (3);

[0007] A carrier storage layer and a P-base region (5) are provided on the top of the N-drift region (3), wherein the carrier storage layer is composed of a first carrier storage layer (4) and a second carrier storage layer (41), a P-type barrier region (6) and a P+ region (8) are provided in the first carrier storage layer (4), and the second carrier storage layer (41) is located between the P-type barrier region (6) and the P+ region (8);

[0008] An N+ region (7) and a P+ region (8) are provided in the P-base region (5), and the N+ region (7) and the P+ region (8) are connected to a source metal electrode (11).

[0009] Furthermore, a gate structure is provided between the N-drift region (3) and the source metal electrode (11), the gate structure comprising a polysilicon gate (9) and a gate oxide (10), the gate oxide (10) being located between the polysilicon gate (9) and the source metal electrode (11), the P-base region (5), the N+ region (7), the P+ region (8), a carrier storage layer 1 (4) and a P-type blocking region (6).

[0010] Furthermore, the P-type barrier region (6) is located in the first carrier storage layer (4) and is close to the P-base region (5), and the second carrier storage layer (41) is located between the P-type barrier region (6) and the P+ region (8) in the JFET region and is close to the JFET region.

[0011] Furthermore, the carrier storage layer 1 (4) and the carrier storage layer 2 (41) are both N-type doped with different doping concentrations, the doping concentration of the carrier storage layer 2 (41) is higher than that of the carrier storage layer 1 (4), and the doping concentration of the P+ region (8) above the carrier storage layer 2 (41) is higher than the doping concentration of the P-type blocking region (6) below it.

[0012] Furthermore, a metal layer is provided above the P+ region (8) in the JFET region and is in ohmic contact and connected to the source metal.

[0013] Based on a general inventive concept, another object of the present invention is to provide a method for preparing a SiC MOSFET device structure with high radiation resistance, so as to improve the total dose and single particle radiation resistance of SiC MOSFET, and the preparation method includes but is not limited to the following steps:

[0014] S01. Making a mask and forming an ion implantation window of a P-type barrier layer by photolithography;

[0015] S02. High energy ion implantation to form a P-type barrier layer;

[0016] S03. Making a second mask and forming an ion implantation window for a carrier storage layer by photolithography;

[0017] S04. High energy ion implantation to form a carrier storage layer;

[0018] S05. Making a mask three and forming an ion implantation window in the P-base region by photolithography;

[0019] S06. High energy ion implantation to form a P-base layer;

[0020] S07. Making a mask plate four and forming an ion implantation window in the N+ region by photolithography;

[0021] S08. High energy ion implantation to form an N+ layer;

[0022] S09. Making a mask plate five and forming an ion implantation window in the P+ region by photolithography;

[0023] S10. High energy ion implantation to form a P+ layer;

[0024] S11. Activating the injected high energy ions by high temperature annealing;

[0025] S12. Thermal oxidation forms a uniform and dense gate oxide layer, deposits polysilicon, makes a mask plate six and etches to form a gate structure;

[0026] S13. Depositing a thick oxide layer, making a mask plate seven and etching to form a source ohmic contact window;

[0027] S14. Using specific metal and high temperature annealing to form a good ohmic contact in the ohmic contact window;

[0028] S15. Making a mask plate eight and etching to form a Schottky contact window;

[0029] S16. Use a specific process to form a good Schottky contact;

[0030] S17. Depositing thick metal on the surface and back, making mask nine and etching to form source and drain electrodes;

[0031] S18. Apply PI glue, make a mask plate 10 and etch to form a metal pad.

[0032] Preferably, the P+ region above the second carrier storage layer and the P+ region in the P-base region are completed by the same step process or a multi-step process;

[0033] When high temperature annealing forms ohmic contacts at various electrode positions on the SiC surface, the ohmic contact at the P+ region in the JFET region shares the same metal with the source of the SiC MOSFET.

[0034] Preferably, the following operations are performed before forming ohmic contacts at electrode positions on the SiC surface by high temperature annealing: patterning contacts of various electrodes, and stripping off the photoresist to remove excess metal.

[0035] The present invention includes but is not limited to manufacturing MOSFET devices using this radiation-resistant structure on SiC materials. Si, GaN and other MOSFET devices using this structure are also within the scope of protection of this patent.

[0036] Compared with the existing traditional planar gate SiC MOSFET device structure, the present invention improves the total dose radiation resistance capability. Figure 2As shown, the principle is as follows: A large amount of research data shows that the impact of total dose radiation on MOSFET structure is mainly to generate a large number of electron-hole pairs in the gate oxide, and a large number of holes are captured by the gate oxide and interface defects, thereby changing its electrical characteristics, such as threshold voltage drift, etc. Compared with the traditional planar gate SiC MOSFET, the present invention adds an ohmic contact with the P+ region above the original JFET region, reduces the area of ​​the gate oxide, thereby reducing the hole capture under total dose radiation, and improves the ability to resist total dose radiation;

[0037] Compared with the existing traditional planar gate SiC MOSFET device structure, the present invention also improves the single particle radiation resistance capability. Figure 3 As shown, the principle is as follows: when high-energy radiation particles hit the device, a large number of electron-hole pairs will be generated inside the device. These electron-hole pairs have two main effects. First, under the drain bias, the device is changed from an off state to an on state, which may also generate local large currents and local high temperatures, seriously damaging the device; second, a large number of holes diffuse to the source under the action of the electric field, and a large number of holes are concentrated under the gate oxide, causing the gate oxide electric field to be too high and degraded, seriously causing gate oxide breakdown. Compared with the traditional planar gate SiC MOSFET, the carrier storage layer 2 of the present invention hinders the diffusion of holes and the concentration under the gate oxide, and the ohmic contact between the P+ of the JFET region and the source metal provides an additional path for hole extraction, thereby improving the ability to resist single particle radiation.

[0038] In summary, the present invention improves the total dose radiation (gamma rays, etc.) and single particle radiation resistance capabilities of SiC MOSFET devices, and can be used in extreme space environments such as aerospace. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of a SiC MOSFET device with high radiation resistance proposed by the present invention;

[0040] Figure 2 This is a comparison diagram of the effects of the present invention and the traditional planar gate MOSFET under total dose radiation;

[0041] Figure 3 A comparison diagram of the effects of the present invention and conventional planar gate MOSFET under single particle radiation;

[0042] Figure 4 The main process flow chart of the device of the present invention is prepared. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings. The description in this part is only exemplary and explanatory and should not have any limiting effect on the protection scope of the present invention.

[0044] The semiconductor device of this embodiment is described by taking silicon carbide MOSFET as an example, but the technology is also applicable to other wide bandgap semiconductor devices.

[0045] like Figure 1 As shown, a planar gate SiC MOSFET device provided in this embodiment, the cell structure of the planar gate SiC MOSFET device includes: a drain metal electrode 1, an N+ substrate 2, and an N-drift region 3 arranged in sequence from bottom to top, a clamp-shaped P-type barrier region 6 and a carrier storage layer 1 4 and a carrier storage layer 2 41 are arranged on the top of the N-drift region 3, a P-base region 5 is arranged on both sides of the carrier storage layer 1 4, a source metal electrode 11 is arranged on the surface of the P-base region 5, and a gate structure is arranged between the N-drift region 3 and the source metal electrode 11;

[0046] The P-base regions 5 on both sides of the cell structure have N+ regions 7, the P-base region 5 below the gate region 9 of the cell structure has N+ regions 7 and P+ regions 8, the P+ region 8 is located outside the N+ region 7, and the lead-out ends of the P+ region 8 and the N+ region 7 are both connected to the source metal electrode 11;

[0047] In the cell structure, two P-type barrier regions 6 are provided in the carrier storage layer 1 4 , and a P+ region is provided above the carrier storage layer 2 41 . The P+ region is in ohmic contact with the surface metal and is connected to the source metal.

[0048] The gate structure includes a polysilicon gate 9 and a gate oxide 10, wherein the gate oxide 10 is disposed between the polysilicon gate 9 and the metal source 11, the P-base region 5, the N+ region 7, and the carrier storage layer 4;

[0049] The carrier storage layer 2 41 and the P-type barrier region 6 have different sizes and doping concentrations to adjust the output characteristic curve of the device;

[0050] In a specific implementation, the relative position relationship and quantity ratio of the SiC MOSFET gate structure, the carrier storage layer and the P-type barrier region can be designed differently in the layout according to actual needs.

[0051] Due to the structural advantages, a split gate structure is adopted to reduce the drain-gate span length, thereby reducing the reverse transfer capacitance and greatly reducing the polar charge.

[0052] The above-mentioned method for preparing a planar gate SiC MOSFET device comprises the following steps:

[0053] Wafer preparation: inspect, clean, and dry the wafer;

[0054] First, a mask layer is deposited and the pattern is transferred to the wafer through multiple photolithography processes. Then, a highly doped carrier storage layer, a P-type barrier region, a P-base region, an N+ region, and a P+ region are formed through high-energy ion implantation. The implanted ions are activated by high-temperature annealing.

[0055] A gate oxide is formed by thermal oxidation, and then a gate structure is formed by etching, the gate structure is etched into two parts, and the SiC surface is exposed in the area between the two gates;

[0056] Then, a SiO2 layer is deposited through a deposition process, so that the oxide layer covers the gate polysilicon and the SiC surface is exposed in other areas except the oxide layer outside the gate polysilicon;

[0057] Deposit contact metal and pattern the source and drain contacts. After stripping the photoresist to remove excess metal, form ohmic contacts at each electrode position on the SiC surface by high temperature annealing.

[0058] The electrode metal is thickened and patterned, and PI glue is used for surface protection.

[0059] It should be noted that, in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus.

[0060] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. The above is only a preferred implementation of the present invention. It should be pointed out that due to the limitations of textual expression and the objective existence of infinite specific structures, ordinary technicians in this technical field can make several improvements, modifications or changes without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the inventive concept and technical solution to other occasions without improvement, should be regarded as the protection scope of the present invention.

[0061] The above embodiments are merely preferred implementations of the present invention. Any simple modification, amendment and substitution of the above embodiments based on the technical essence of the present invention shall fall within the scope of the technical solution of the present invention.

Claims

1. A SiC MOSFET device structure with high radiation resistance, characterized in that: The cell structure of the planar gate SiC MOSFET device includes: a drain metal electrode (1), an N+ type substrate (2) and an N-drift region (3); A carrier storage layer and a P-base region (5) are provided on the top of the N-drift region (3), wherein the carrier storage layer is composed of a first carrier storage layer (4) and a second carrier storage layer (41), a P-type barrier region (6) and a P+ region (8) are provided in the first carrier storage layer (4), and the second carrier storage layer (41) is located between the P-type barrier region (6) and the P+ region (8); An N+ region (7) and a P+ region (8) are provided in the P-base region (5), and the N+ region (7) and the P+ region (8) are connected to a source metal electrode (11); A gate structure is provided between the N-drift region (3) and the source metal electrode (11), the gate structure comprising a polysilicon gate (9) and a gate oxide (10), the gate oxide (10) being located between the polysilicon gate (9) and the source metal electrode (11), the P-base region (5), the N+ region (7), the P+ region (8), a carrier storage layer 1 (4) and a P-type blocking region (6); The P-type barrier region (6) is located in the first carrier storage layer (4) and is close to the P-base region (5), and the second carrier storage layer (41) is located between the P-type barrier region (6) and the P+ region (8) in the JFET region and is close to the JFET region; The carrier storage layer 1 (4) and the carrier storage layer 2 (41) are both N-type doped with different doping concentrations, the doping concentration of the carrier storage layer 2 (41) is higher than that of the carrier storage layer 1 (4), and the doping concentration of the P+ region (8) above the carrier storage layer 2 (41) is higher than the doping concentration of the P-type blocking region (6) below it; A metal layer is provided above the P+ region (8) in the JFET region and is in ohmic contact and connected to the source metal.

2. The method for preparing a SiC MOSFET device structure with high radiation resistance according to claim 1, characterized in that: Including but not limited to the following steps: S01. Making a mask and forming an ion implantation window of a P-type barrier layer by photolithography; S02. High energy ion implantation to form a P-type barrier layer; S03. Making a second mask and forming an ion implantation window for a carrier storage layer by photolithography; S04. High energy ion implantation to form a carrier storage layer; S05. Making a mask three and forming an ion implantation window in the P-base region by photolithography; S06. High energy ion implantation to form a P-base layer; S07. Making a mask plate four and forming an ion implantation window in the N+ region by photolithography; S08. High energy ion implantation to form an N+ layer; S09. Making a mask plate five and forming an ion implantation window in the P+ region by photolithography; S10. High energy ion implantation to form a P+ layer; S11. Activating the injected high energy ions by high temperature annealing; S12. Thermal oxidation forms a uniform and dense gate oxide layer, deposits polysilicon, makes a mask plate six and etches to form a gate structure; S13. Depositing a thick oxide layer, making a mask plate seven and etching to form a source ohmic contact window; S14. Using specific metal and high temperature annealing to form a good ohmic contact in the ohmic contact window; S15. Making a mask plate eight and etching to form a Schottky contact window; S16. Use a specific process to form a good Schottky contact; S17. Depositing thick metal on the surface and back, making mask nine and etching to form source and drain electrodes; S18. Apply PI glue, make a mask plate 10 and etch to form a metal pad.

3. The method for preparing a SiC MOSFET device structure with high radiation resistance according to claim 2, characterized in that: The P+ region above the second carrier storage layer and the P+ region in the P-base region are completed by a same-step process or a multi-step process; When high temperature annealing forms ohmic contacts at various electrode positions on the SiC surface, the ohmic contacts at the P+ region in the JFET region share the same metal as the source of the SiC MOSFET.

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