Split-gate flash memory cell and method for manufacturing the same

Abstract

The present invention provides a split-gate flash memory cell and a manufacturing method thereof, comprising: a substrate; a trench located within the substrate; a source region located within the substrate at the bottom of the trench; a source line layer located within the trench to be electrically connected to the source region and separating the trench into two sub-trenches; a first split-gate structure and a second split-gate structure, both including a floating gate and a control gate arranged from bottom to top, the floating gates of the first split-gate structure and the second split-gate structure respectively fill the two sub-trenches and extend to cover a partial surface of the substrate, and the top of the floating gate is higher than the source line layer; an erase gate located on the source line layer; the present invention is conducive to reducing the size of the split-gate flash memory cell.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a split-gate flash memory cell and a method for manufacturing the same. Background Art

[0002] As a non-volatile memory, flash memory controls the switching of the gate channel by changing the critical voltage of the transistor or storage cell to achieve the purpose of storing data, so that the data stored in the memory will not be lost due to power interruption. And as a special structure of electrically erasable and programmable read-only memory, flash memory has now occupied most of the market share of non-volatile semiconductor memories and has become the fastest-growing non-volatile semiconductor memory.

[0003] Figure 1 It is a cross-sectional schematic diagram of a split-gate flash memory cell. Please refer to Figure 1 , in terms of the device structure, it is required that the source region 10' and the floating gate 20' have a certain width overlap in the transverse direction as a coupling part (shown in the dashed box in the figure). This coupling part is a planar structure, and the coupling part is used to ensure the coupling coefficient between the source region 10' and the floating gate 20', which is beneficial for the split-gate flash memory cell to be programmed. In order to ensure a certain width overlap between the source region 10' and the floating gate 20' in the transverse direction, the width of the floating gate cannot be too small, making it difficult to reduce the size of the device structure. Summary of the Invention

[0004] The purpose of the present invention is to provide a split-gate flash memory cell and a method for manufacturing the same, which are beneficial to reducing the size of the split-gate flash memory cell.

[0005] To achieve the above purpose, the present invention provides a split-gate flash memory cell, including:

[0006] A substrate;

[0007] A trench, located in the substrate;

[0008] A source region, located in the substrate at the bottom of the trench;

[0009] A source line layer, located in the trench to be electrically connected to the source region, and separating the trench into two sub-trenches;

[0010] A first split-gate structure and a second split-gate structure, both including a floating gate and a control gate arranged from bottom to top. The floating gates of the first split-gate structure and the second split-gate structure respectively fill the two sub-trenches and extend to cover a part of the surface of the substrate, and the top of the floating gate is higher than the source line layer;

[0011] An erase gate, located on the source line layer.

[0012] Optionally, the first split gate structure and the second split gate structure also each include a dielectric layer that wraps the outer walls of the floating gate and the control gate.

[0013] Optionally, the dielectric layer includes a first sidewall and a second sidewall. The first sidewall is located on the corresponding control gate, and the second sidewall covers the corresponding first sidewall and the side of the control gate close to the erase gate.

[0014] Optionally, the dielectric layer further includes a third sidewall that covers the corresponding first sidewall, the floating gate, and the side of the control gate away from the erase gate; and,

[0015] The first split gate structure and the second split gate structure also each include a word line gate that covers at least a portion of the surface of the corresponding third sidewall.

[0016] Optionally, there are also two drain regions, which are respectively located in the substrate outside the word line gates of the first split gate structure and the second split gate structure.

[0017] Optionally, the material of the source line layer includes polysilicon.

[0018] A method for fabricating a split gate flash memory cell includes:

[0019] Providing a substrate and forming a trench in the substrate; and,

[0020] Forming a source region in the substrate at the bottom of the trench, forming a source line layer in the trench, forming parts of the first split gate structure and the second split gate structure in the trench, and forming an erase gate on the source line layer;

[0021] Wherein, the source line layer is electrically connected to the source region and divides the trench into two sub-trenches;

[0022] The first split gate structure and the second split gate structure each include a floating gate and a control gate arranged from bottom to top. The floating gates of the first split gate structure and the second split gate structure respectively fill the two sub-trenches and extend to cover a part of the surface of the substrate, and the top of the floating gate is higher than the source line layer.

[0023] Optionally, the steps of forming the source region, the source line layer, the erase gate, the floating gate, and the control gate include:

[0024] Sequentially forming a floating gate material layer, a control gate material layer, and a mask layer on the substrate, and the floating gate material layer also fills the trench;

[0025] Sequentially etching the mask layer, the control gate material layer, and the floating gate material layer to form an opening that exposes the bottom of the trench;

[0026] Ion implant the substrate at the bottom of the opening to form the source region in the substrate at the bottom of the opening;

[0027] Fill a portion of the depth of the opening to form the source line layer, and fill the remaining depth of the opening to form the erase gate; and,

[0028] Etch away the mask layer, the floating gate material layer and the control gate material layer directly under the mask layer, and the remaining floating gate material layer serves as the floating gate, and the remaining control material layer serves as the control gate.

[0029] Optionally, the step of sequentially etching the mask layer, the control gate material layer and the floating gate material layer to form an opening exposing the bottom of the trench includes:

[0030] Etch the mask layer to form a first opening exposing the control gate material layer, and the first opening is located above the trench;

[0031] Form a first sidewall on the sidewall of the first opening;

[0032] Use the first sidewall as a mask to etch the control gate material layer to form a second opening exposing the floating gate material layer;

[0033] Form the second sidewall on the sidewall of the second opening, and the second sidewall covers a portion of the surface of the first sidewall; and,

[0034] Use the first sidewall and the second sidewall as masks to etch the floating gate material layer to form a third opening exposing the substrate at the bottom of the trench, and the first opening, the second opening and the third opening constitute the opening.

[0035] Optionally, after forming the floating gate and the control gate, further includes:

[0036] Form a third sidewall on the side of the corresponding first sidewall, control gate and floating gate away from the erase gate;

[0037] Form a word line gate on at least a portion of the surface of the corresponding third sidewall; and,

[0038] Ion implant the substrate outside the word line gate respectively to form drain regions in the substrate.

[0039] In the split-gate flash memory cell and its manufacturing method provided by the present invention, the source region is located in the substrate at the bottom of the trench, the source line layer is located in the trench to be electrically connected to the source region, and the trench is divided into two sub-trenches; both the first split-gate structure and the second split-gate structure include a floating gate and a control gate arranged from bottom to top. The floating gates of the first split-gate structure and the second split-gate structure respectively fill the two sub-trenches and extend to cover a part of the surface of the substrate, and the top of the floating gate is higher than the source line layer; in the present invention, since the source line layer is located in the trench, the floating gates of the first split-gate structure and the second split-gate structure respectively fill the two sub-trenches, and the source line layer is electrically connected to the source region, the coupling part between the source region and the floating gate can be changed from a planar structure to a three-dimensional structure. While ensuring a good coupling coefficient between the floating gate and the source region, the planar width of the floating gate can be reduced, which is beneficial to the size reduction of the split-gate flash memory cell. Description of the Drawings

[0040] Figure 1 It is a cross-sectional schematic diagram of a split-gate flash memory cell;

[0041] Figure 2 It is a flowchart of the manufacturing method of the split-gate flash memory cell provided by an embodiment of the present invention;

[0042] Figures 3A - 3K It is a cross-sectional schematic diagram of the corresponding steps in the manufacturing method of the split-gate flash memory cell provided by an embodiment of the present invention, where, Figure 3K It is a cross-sectional schematic diagram of the split-gate flash memory cell provided by an embodiment of the present invention;

[0043] Among them, the reference numerals are:

[0044] 10’ - source region; 20’ - floating gate; 10 - substrate; 11 - trench; 21 - first oxide layer; 22 - ONO structure layer; 23 - second oxide layer; 24 - third oxide layer; 31 - floating gate material layer; 32 - control gate material layer; 40 - mask layer; 51 - first opening; 52 - second opening; 53 - third opening; 61 - first sidewall; 62 - second sidewall; 63 - third sidewall; 71 - source region; 72 - drain region; 80 - source line layer; 90 - erase gate; 220 - inter-gate structure layer; 310 - floating gate; 320 - control gate; 100 - word line gate; T1 - first split-gate structure; T2 - second split-gate structure. Detailed Description of the Embodiments

[0045] The following will describe the specific embodiments of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0046] Figure 3KThe cross-sectional schematic diagram of the split-gate flash memory cell provided in this embodiment. Please refer to Figure 3K , this embodiment provides a split-gate flash memory cell, including: a substrate 10, a trench, a first split-gate structure T1, a second split-gate structure T2, a source line layer 80, an erase gate 90, and a source region 71. The trench (not marked in the figure) is located in the substrate 10, and the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen, or carbon.

[0047] The source line layer 80 is located in the trench, separating the trench into two sub-trenches (not marked in the figure). The erase gate 90 is located on the source line layer 80. In this embodiment, the material of the source line layer 80 is polysilicon.

[0048] Both the first split-gate structure T1 and the second split-gate structure T2 include a floating gate 310 and a control gate 320 arranged from bottom to top. The floating gates 310 of the first split-gate structure T1 and the second split-gate structure T222 respectively fill the two sub-trenches and extend to cover a part of the surface of the substrate 10. The top of the floating gate 310 is higher than the top of the source line layer 80. Further, a first oxide layer 21 is formed between the floating gate 310 and the sidewall of the trench and between a part of the surface of the substrate 10, and the first oxide layer 21 extends to cover the surface of the substrate 10; a second oxide layer 23 is formed between the source line layer 80 and the floating gate 310, and an inter-gate structure layer 220 is formed between the floating gate 310 and the control gate 320, and the widths of the control gate 320 and the gate structure layer 220 are smaller than the width of the floating gate 310.

[0049] Furthermore, both the first split-gate structure T1 and the second split-gate structure T2 also include a dielectric layer, and the dielectric layer wraps the outer wall of the floating gate and a part of the outer wall of the control gate. Specifically, the dielectric layer includes a first sidewall 61 and a second sidewall 62. The first sidewall 61 is located on the corresponding control gate 320, and the first sidewalls 61 of the first split-gate structure T1 and the second split-gate structure T2 cover two side surfaces of the erase gate 90; the second sidewall 62 is located on the floating gate 310 and covers the side of the corresponding control gate 320 close to the erase gate 90 and a part of the surface of the corresponding first sidewall 61. In this embodiment, a third oxide layer 24 is formed between the erase gate 90 and the source line layer 80, and the third oxide layer 24 covers a part of the surface of the second oxide layer 23 and the second sidewall 62.

[0050] The source region 71 is located in the substrate 10 at the bottom of the trench, and the source region 71 is electrically connected to the source line layer 80. The area where the source line layer 80 and the floating gate 310 are relatively close to each other is the coupling surface between the source region 71 and the floating gate 310, that is, the coupling part. The size of the coupling surface represents the coupling coefficient between the source region 71 and the floating gate 310. A relatively large coupling coefficient between the source region 71 and the floating gate 310 is beneficial to increasing the erasing efficiency. Moreover, changing the coupling part from a planar structure to a three-dimensional structure, that is, changing the planar coupling structure to a longitudinal three-dimensional coupling structure, can reduce the planar width of the floating gate 310 while ensuring a good coupling coefficient between the floating gate 310 and the source region 71, which is beneficial to reducing the device size.

[0051] Further, the dielectric layer further includes a third sidewall 63, and the third sidewall 63 covers the corresponding first sidewall 61, the floating gate 310, and the side of the control gate 320 away from the erasing gate 90.

[0052] Further, the first split-gate structure T1 and the second split-gate structure T2 both further include a word line gate 100, and the word line gate 100 covers at least a part of the surface of the corresponding third sidewall 63. In this embodiment, the first split-gate structure T1 and the second split-gate structure T2 are symmetrically arranged with respect to the source line layer 80 and the erasing gate 90. The first split-gate structure T1 and the second split-gate structure T2 both include a first sidewall 61, a control gate 320, an inter-gate structure layer 220, a floating gate 310, a gate oxide layer 210, a second sidewall 62, a third sidewall 63, and a word line gate 100. In Figure 3K order to facilitate the illustration, the first split-gate structure T1 and the second split-gate structure T2 are simply circled by a rectangular dashed box. The circled part does not represent all that belongs to the first split-gate structure T1 and the second split-gate structure T2. For the specific parts included in the first split-gate structure T1 and the second split-gate structure T2, please refer to the text description of this embodiment.

[0053] Further, there are also two drain regions, which are respectively located in the substrate 10 outside the word line gates 100 of the first split-gate structure T1 and the second split-gate structure T2.

[0054] In this embodiment, a split-gate flash memory device can be formed by using multiple split-gate flash memory cells. There is no limitation in this description on how the multiple split-gate flash memory cells are arranged.

[0055] Figure 2 This is a flowchart of the manufacturing method of the split-gate flash memory cell provided in this embodiment. Please refer to Figure 2 In this embodiment, a manufacturing method of a split-gate flash memory cell is provided, including:

[0056] Step S1: Provide a substrate and form a trench in the substrate; and,

[0057] Step S2: Form a source region in the substrate at the bottom of the trench, form a source line layer in the trench, form a first split gate structure and a partial second split gate structure in the trench, and form an erase gate on the source line layer;

[0058] Wherein, the source line layer is electrically connected to the source region and divides the trench into two sub-trenches;

[0059] Both the first split gate structure and the second split gate structure include a floating gate and a control gate arranged from bottom to top. The floating gates of the first split gate structure and the second split gate structure respectively fill the two sub-trenches and extend to cover a partial surface of the substrate, and the top of the floating gate is higher than the source line layer.

[0060] Figures 3A - 3K is a schematic cross-sectional view of the corresponding step in the manufacturing method of the split gate flash memory cell provided in this embodiment. Refer to Figures 3A - 3K for a detailed description of the manufacturing method of the split gate flash memory cell provided in this embodiment.

[0061] Please refer to Figure 3A , and perform step S1: Provide a substrate 10, the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon, and etch the substrate 10 to form a trench 11 in the substrate 10.

[0062] The steps of performing step S2: forming the source region, the source line layer, the erase gate, the floating gate and the control gate include:

[0063] Please refer to Figure 3B , and sequentially form a first oxide layer 21, a floating gate material layer 31, an ONO structure layer 22, a control gate material layer 32 and a mask layer 40 on the substrate 10. The first oxide layer 21 covers the inner wall of the trench and the surface of the substrate 10, and the floating gate material layer 31 also fills the trench.

[0064] Please refer to Figure 3C , form a first patterned photoresist layer (not shown in the figure) on the mask layer 40, etch the mask layer 40 using the first patterned photoresist layer as a mask to form a first opening 51 exposing the control gate material layer 32. The first opening 51 is located above the trench, and remove the first patterned photoresist layer after etching; furthermore, form a first sidewall 61 on the sidewall of the first opening 51.

[0065] Please refer to Figure 3D , etch the control gate material layer 32 and the ONO structure layer 22 using the first sidewall 61 as a mask to form a second opening 52 exposing the floating gate material layer 31; furthermore, form a second sidewall 62 on the sidewall of the second opening 52, and the second sidewall 62 covers a partial surface of the first sidewall 61.

[0066] Please refer to Figure 3E, using the first sidewall 61 and the second sidewall 62 as masks to etch the floating gate material layer 31 to form a third opening 53 that exposes the bottom of the trench. The first opening 51, the second opening 52, and the third opening 53 constitute the opening. In this embodiment, after etching, the first oxide layer 21 at the bottom of the third opening 53 can be retained (such as Figure 3E ), or the first oxide layer 21 at the bottom of the third opening 53 can be synchronously etched away to expose the substrate 10 at the bottom of the trench. Furthermore, the substrate 10 at the bottom of the opening is ion-implanted to form a source region 71 in the substrate 10 at the bottom of the opening.

[0067] Please refer to Figure 3F , a second oxide layer 23 is formed on the inner wall of the third opening 53, and the second oxide layer 23 covers the bottom of the third opening 53 (which has been etched away in Figure 3F ); then, the second oxide layer 23 at the bottom of the third opening 53 is etched away. If the first oxide layer 21 is retained at the bottom of the third opening 53, the second oxide layer 23 and the first oxide layer 21 at the bottom of the third opening 53 are etched away to expose the substrate 10.

[0068] Please refer to Figure 3G , a source connection material layer (not labeled in the figure) is filled in the opening, and a part of the depth of the source connection material layer in the opening is etched away. The remaining source connection material layer serves as the source line layer 80. The source line layer 80 fills a part of the depth of the third opening 53. The top of the source line layer 80 is lower than the top of the floating gate material layer 31. The source line layer 80 is electrically connected to the source region 71. The material of the source line layer 80 is preferably polysilicon.

[0069] Please refer to Figure 3H , a third oxide layer 24 is formed on the source line layer 80, and the third oxide layer 24 covers the second oxide layer 23 and a part of the surface of the second sidewall 62.

[0070] Please refer to Figure 3I , the remaining depth of the opening is filled to form an erase gate 90. The material of the erase gate 90 is polysilicon, and a protective layer (not shown in the figure) can be formed on the erase gate 90 to protect the erase gate 90 from the influence of subsequent processes.

[0071] Please continue to refer to Figure 3I and refer to Figure 3J, a second patterned photoresist layer (not shown in the figure) is formed on the mask layer 40. Using the second patterned photoresist layer as a mask, the mask layer 40, the control gate material layer 32 directly below the mask layer 40, the ONO structure layer 22, and the floating gate material layer 31 are etched away in sequence. The etching stops on the first oxide layer 21. After etching, the second patterned photoresist layer is removed; the remaining floating gate material layer after etching serves as the floating gate 310, the remaining control material layer serves as the control gate 320, the remaining ONO structure layer serves as the inter-gate structure layer 220, and the first oxide layer 21 serves as the gate oxide layer. The etching can stop on the first oxide layer 21, or the first oxide layer 21 can be etched synchronously using the second patterned photoresist layer as a mask until the surface of the substrate 10 is exposed.

[0072] Please refer to Figure 3K , third sidewalls 63 are formed on the sides of the corresponding first sidewalls 61, control gates 320, inter-gate structure layers 220, floating gates 310, and gate oxide layers 210 that are away from the erase gate 90. Further, word line gates 100 are formed on at least part of the surfaces of the corresponding third sidewalls 63. In this embodiment, the first split gate structure T1 and the second split gate structure T2 are symmetrically arranged with respect to the source line layer 80 and the erase gate 90. The first split gate structure T1 and the second split gate structure T2 both include first sidewalls 61, control gates 320, inter-gate structure layers 220, floating gates 310, gate oxide layers 210, second sidewalls 62, third sidewalls 63, and word line gates 100.

[0073] Please continue to refer to Figure 3K , after the word line gates 100 are formed, ion implantation is performed on the substrate 10 outside the word line gates 100 of the first split gate structure T1 and the second split gate structure T2 respectively to form two drain regions 72 in the substrate 10.

[0074] In summary, in the split gate flash memory cell and its manufacturing method provided by the present invention, the source region is located in the substrate at the bottom of the trench, the source line layer is located in the trench to be electrically connected to the source region, and the trench is divided into two sub-trenches; both the first split gate structure and the second split gate structure include a floating gate and a control gate arranged from bottom to top. The floating gates of the first split gate structure and the second split gate structure respectively fill the two sub-trenches and extend to cover part of the surface of the substrate, and the top of the floating gate is higher than the source line layer; in the present invention, since the source line layer is located in the trench, the floating gates of the first split gate structure and the second split gate structure respectively fill the two sub-trenches, and the source line layer is electrically connected to the source region, the coupling part between the source region and the floating gate can be changed from a planar structure to a three-dimensional structure. While ensuring a good coupling coefficient between the floating gate and the source region, the planar width of the floating gate can be reduced, which is beneficial to reducing the size of the split gate flash memory cell.

[0075] The above are only the preferred embodiments of the present invention and do not impose any restrictive effect on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A split-gate flash memory cell, characterized in that, comprising: a substrate; a trench located within the substrate; a source region located within the substrate at the bottom of the trench; a source line layer located within the trench to be electrically connected to the source region, and dividing the trench into two sub-trenches; a first split-gate structure and a second split-gate structure, both comprising a dielectric layer, a floating gate and a control gate arranged from bottom to top, the floating gates of the first split-gate structure and the second split-gate structure respectively fill the two sub-trenches and extend to cover a part of the surface of the substrate, and the top of the floating gate is higher than the source line layer, the dielectric layer wraps the outer walls of the floating gate and the control gate, wherein the dielectric layer includes a first sidewall and a second sidewall, the first sidewall is located on the corresponding control gate, and the second sidewall covers the corresponding first sidewall and the side of the control gate close to the erase gate; an erase gate located on the source line layer.

2. The split-gate flash memory cell according to claim 1, characterized in that, the dielectric layer further includes a third sidewall, and the third sidewall covers the corresponding first sidewall, the floating gate and the side of the control gate away from the erase gate; and, the first split-gate structure and the second split-gate structure further both include a word line gate, and the word line gate covers at least a part of the surface of the corresponding third sidewall.

3. The split-gate flash memory cell according to claim 2, characterized in that, it further includes two drain regions respectively located within the substrate outside the word line gates of the first split-gate structure and the second split-gate structure.

4. The split-gate flash memory cell according to claim 1, characterized in that, the material of the source line layer includes polysilicon.

5. A method for manufacturing a split-gate flash memory cell, characterized in that, comprising: providing a substrate and forming a trench within the substrate; and, forming a source region within the substrate at the bottom of the trench, forming a source line layer within the trench, forming parts of the first split-gate structure and the second split-gate structure within the trench, and forming an erase gate on the source line layer; wherein, the source line layer is electrically connected to the source region and divides the trench into two sub-trenches; the first split-gate structure and the second split-gate structure both include a dielectric layer, a floating gate and a control gate arranged from bottom to top, the floating gates of the first split-gate structure and the second split-gate structure respectively fill the two sub-trenches and extend to cover a part of the surface of the substrate, and the top of the floating gate is higher than the source line layer, the dielectric layer wraps the outer walls of the floating gate and the control gate, wherein the dielectric layer includes a first sidewall and a second sidewall, the first sidewall is located on the corresponding control gate, and the second sidewall covers the corresponding first sidewall and the side of the control gate close to the erase gate.

6. The method for manufacturing a split-gate flash memory cell according to claim 5, characterized in that, the steps of forming the source region, the source line layer, the erase gate, the floating gate and the control gate include: sequentially forming a floating gate material layer, a control gate material layer and a mask layer on the substrate, and the floating gate material layer also fills the trench; Etch the mask layer, the control gate material layer, and the floating gate material layer in sequence to form an opening exposing the bottom of the trench; Perform ion implantation on the substrate at the bottom of the opening to form the source region in the substrate at the bottom of the opening; Fill a part of the depth of the opening to form the source line layer, and fill the remaining depth of the opening to form the erase gate; and, Etch away the mask layer and the floating gate material layer and the control gate material layer directly under the mask layer, and the remaining floating gate material layer serves as the floating gate, and the remaining control material layer serves as the control gate.

7. The method for manufacturing a split-gate flash memory cell according to claim 6, wherein, The step of etching the mask layer, the control gate material layer, and the floating gate material layer in sequence to form an opening exposing the bottom of the trench includes: Etch the mask layer to form a first opening exposing the control gate material layer, and the first opening is located above the trench; Form the first sidewall on the sidewall of the first opening; Use the first sidewall as a mask to etch the control gate material layer to form a second opening exposing the floating gate material layer; Form the second sidewall on the sidewall of the second opening, and the second sidewall covers a part of the surface of the first sidewall; and, Use the first sidewall and the second sidewall as masks to etch the floating gate material layer to form a third opening exposing the substrate at the bottom of the trench, and the first opening, the second opening, and the third opening constitute the opening.

8. The method for manufacturing a split-gate flash memory cell according to claim 6, wherein, After forming the floating gate and the control gate, it further includes: Form a third sidewall on the side of the corresponding first sidewall, control gate, and floating gate away from the erase gate; Form a word line gate on at least a part of the surface of the corresponding third sidewall; and, Perform ion implantation on the substrate outside the word line gate respectively to form drain regions in the substrate.

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