vibrating device

Abstract

Vibration device. Downsizing can be achieved when viewed in plan. The vibration device (1) includes: a semiconductor substrate (4) having a first face (4h) provided with an integrated circuit (41) and a second face (4r) in positive and negative relation to the first face (4h); a vibration element (5) disposed on the first face (4h); a cover (3) having a recess (32) opening on the first face (4h) side and an abutting face (31) abutting the first face (4h) and engaging the first face (4h) at the abutting face (31); and a metal layer (6) disposed between the first face (4h) and the abutting face (31), at least a portion of the integrated circuit (41) overlapping the metal layer (6) when viewed in plan from the normal direction of the first face (4h).

Description

Technical Field

[0001] This invention relates to vibration devices. Background Technology

[0002] Previously, vibrating devices using piezoelectric oscillators such as quartz oscillators were widely used in electronic devices such as mobile phones. With the miniaturization of electronic devices, there is a demand for further miniaturization of vibrating devices. Moreover, in order to miniaturize vibrating devices, a technology has been proposed that mounts piezoelectric oscillators on a semiconductor substrate containing integrated circuits, and then arranges a cover on the semiconductor substrate as a cover to cover the piezoelectric oscillators.

[0003] For example, Patent Document 1 discloses a piezoelectric oscillator with the following structure: a piezoelectric vibrator is directly mounted on and connected to a semiconductor integrated component, a cover is configured to cover the piezoelectric vibrator from the semiconductor integrated component, and an adhesive is used to fix the cover to the semiconductor integrated component.

[0004] Furthermore, Patent Document 2 discloses a piezoelectric oscillator with the following structure: a first substrate having a circuit portion formed on its surface side and a vibration element mounted on its back side; and a second substrate serving as a cover substrate having a recess for accommodating the vibration element, wherein the first substrate and the second substrate are joined together with the vibration element housed within the recess.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2004-128591

[0006] Patent Document 2: Japanese Patent Application Publication No. 2017-139717 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] However, in the structure described in Patent Document 1, since an adhesive is used to fix the cover, it is necessary to apply pressure to the cover and the semiconductor integrated component while fixing them at high temperature. The semiconductor integrated circuit is prone to breakage during the fixing process. Therefore, there is a problem that, when using an adhesive to fix the cover, the areas where the cover and the semiconductor integrated component are fixed need to be configured so that they do not overlap, thus increasing the size of the piezoelectric oscillator.

[0009] Furthermore, in the structure described in Patent Document 2, when grinding and polishing the first substrate to make the piezoelectric oscillator thinner, it is not possible to grind and polish the surface side of the first substrate where the circuit portion is formed. Therefore, there is a problem that the back side of the first substrate where the vibration element is mounted needs to be ground and polished before mounting the vibration element, making it difficult to make the piezoelectric oscillator thinner.

[0010] means for solving problems

[0011] The semiconductor substrate has a first surface on which an integrated circuit is disposed and a second surface opposite to the first surface; a vibrating element disposed on the first surface; a cover having a recess with an opening on the first surface and an abutting surface that abuts against the first surface in such a way as to receive the vibrating element in the recess, and is engaged with the first surface at the abutting surface; and a metal layer disposed between the first surface and the abutting surface, wherein at least a portion of the integrated circuit overlaps with the metal layer when viewed from the normal direction of the first surface. Attached Figure Description

[0012] Figure 1 This is a perspective view showing the vibration device of Embodiment 1.

[0013] Figure 2 yes Figure 1 A cross-sectional view at line AA in the diagram.

[0014] Figure 3 This is a top view showing the outline structure of the vibration device according to Embodiment 1.

[0015] Figure 4 This is a flowchart illustrating the main manufacturing processes of the vibration device according to Embodiment 1.

[0016] Figure 5 This is a cross-sectional schematic diagram showing the manufacturing process of the vibration device according to Embodiment 1.

[0017] Figure 6 This is a cross-sectional schematic diagram showing the manufacturing process of the vibration device according to Embodiment 1.

[0018] Figure 7 This is a cross-sectional schematic diagram showing the manufacturing process of the vibration device according to Embodiment 1.

[0019] Figure 8 This is a cross-sectional schematic diagram showing the manufacturing process of the vibration device according to Embodiment 1.

[0020] Figure 9 This is a cross-sectional schematic diagram showing the manufacturing process of the vibration device according to Embodiment 1.

[0021] Label Explanation

[0022] 1 Vibrating device; 2 Package; 3 Cover; 4 Semiconductor substrate; 4h First surface; 4r Second surface; 5 Vibrating element; 6 Metal layer; 31 Abutting surface; 32 Recess; 40 Base substrate; 41 Integrated circuit; 42 Insulating layer; 45 Wiring; 61 First metal layer; 62 Second metal layer; 63 Third metal layer; 64 Fourth metal layer; 321 Bottom surface; 322 Side surface; 70 External terminal; 400 Through hole; 402 Through electrode. Detailed Implementation

[0023] 1. Implementation Method 1

[0024] Reference Figures 1-3 The vibration device 1 of Embodiment 1 will be described below. Furthermore, to facilitate the explanation of the internal structure of the vibration device 1, Figure 3 The diagram shows the state with cover 3 removed. Additionally, the dimensional ratios of the components in the diagram differ from the actual dimensions.

[0025] In the coordinate system shown in the attached diagram, the three mutually orthogonal axes are designated as the X-axis, Y-axis, and Z-axis. The direction along the X-axis is defined as the "X-direction," the direction along the Y-axis as the "Y-direction," and the direction along the Z-axis as the "Z-direction," with the arrow pointing in the positive direction. Furthermore, the Z-direction is designated as the "normal direction," with the positive Z-direction defined as "up" or "above," and the negative Z-direction defined as "down" or "below." Additionally, in a top-down view from the Z-direction, the surface on the positive side of the Z-direction is designated as the upper surface, and the surface on the opposite side (the surface on the negative Z-direction) is designated as the lower surface.

[0026] like Figure 1 as well as Figure 2 As shown, the vibration device 1 has a vibration element 5 and a package 2 for housing the vibration element 5. The package 2 has a semiconductor substrate 4, a cover 3, and a metal layer 6.

[0027] The semiconductor substrate 4 has a first surface 4h on which an integrated circuit 41 is disposed and a second surface 4r opposite to the first surface 4h.

[0028] The cover 3 is a box-shaped cover having a recess 32 with an opening on the first surface 4h side of the semiconductor substrate 4 and an abutting surface 31 that abuts against the first surface 4h of the semiconductor substrate 4. Furthermore, the fact that the abutting surface 31 of the cover 3 abuts against the first surface 4h of the semiconductor substrate 4 does not necessarily mean that the abutting surface 31 of the cover 3 is in direct contact with the first surface 4h of the semiconductor substrate 4; it includes the case where the first surface 4h of the semiconductor substrate 4 and the abutting surface 31 of the cover 3 are in contact through a metal layer 6 or similar material.

[0029] The metal layer 6 is a bonding portion that joins the semiconductor substrate 4 and the cover 3, and is disposed between the first surface 4h of the semiconductor substrate 4 and the abutting surface 31 of the cover 3. The cover 3 is bonded to the first surface 4h of the semiconductor substrate 4 via the metal layer 6 on the abutting surface 31.

[0030] At least a portion of the integrated circuit 41 overlaps with the metal layer 6 when viewed from above in the Z direction, which is the normal direction of the first surface 4h of the semiconductor substrate 4. In other words, at least a portion of the integrated circuit 41 overlaps with the metal layer 6, i.e., the junction of the semiconductor substrate 4 and the cover 3, when viewed from above.

[0031] The vibrating element 5 is disposed on the first surface 4h of the semiconductor substrate 4. By joining the first surface 4h of the semiconductor substrate 4 and the abutting surface 31 of the cover 3, the vibrating element 5 is housed in the recess 32 of the cover 3. In other words, the opening of the recess 32 of the cover 3 is closed by the semiconductor substrate 4, and a housing space S for housing the vibrating element 5 is formed on the first surface 4h of the semiconductor substrate 4.

[0032] like Figure 2 and Figure 3 As shown, the semiconductor substrate 4 is flat and has a first surface 4h as its upper surface and a second surface 4r as its lower surface. The second surface 4r and the first surface 4h are opposite to each other. A frame-shaped first metal layer 61 is provided on the first surface 4h of the semiconductor substrate 4, which is arranged along the outer edge of the first surface 4h.

[0033] In this embodiment, the first metal layer 61 is formed of gold (Au) with a thickness of 100 nm. The first metal layer 61 may also be made of a metal other than gold (Au), such as copper (Cu).

[0034] In this embodiment, a bonding layer (not shown) is provided between the first metal layer 61 and the first surface 4h of the semiconductor substrate 4. The bonding layer improves the adhesion between the first metal layer 61 and the first surface 4h of the semiconductor substrate 4. The bonding layer is formed of titanium (Ti) with a thickness of 5 nm. Alternatively, a metal other than titanium (Ti), such as tungsten (W), may be used for the bonding layer. Alternatively, the bonding layer may not be provided.

[0035] The cover 3 has a bottomed recess 32 that opens below the first surface 4h of the semiconductor substrate 4, and an abutment surface 31 formed in a frame shape along the outer edge of the recess 32 and abutting against the first surface 4h of the semiconductor substrate 4. In this embodiment, the cover 3 is formed of a silicon substrate. However, the cover 3 may also be formed of a material other than silicon, such as glass or ceramic.

[0036] A second metal layer 62 is provided on the contact surface 31.

[0037] In this embodiment, the second metal layer 62 is formed of gold (Au) with a thickness of 20 nm. Alternatively, a metal other than gold (Au), such as copper (Cu), may be used as the second metal layer 62.

[0038] In this embodiment, a sealing layer (not shown) is provided between the second metal layer 62 and the contact surface 31 of the cover 3. This sealing layer improves the adhesion between the second metal layer 62 and the contact surface 31 of the cover 3. The sealing layer is formed of titanium (Ti) with a thickness of 5 nm. Alternatively, a metal other than titanium (Ti), such as tungsten (W), can be used for the sealing layer. Alternatively, the sealing layer may not be provided.

[0039] A first metal layer 61 disposed on the first surface 4h of the semiconductor substrate 4 and a second metal layer 62 disposed on the abutment surface 31 are joined by active bonding to form a metal layer 6. In this way, the abutment surface 31 of the cover 3 and the first surface 4h of the semiconductor substrate 4 are joined via the metal layer 6.

[0040] Activation bonding is a method of bonding by irradiating the first metal layer 61 and the second metal layer 62 with a neutral argon ion beam or the like, thereby activating the surfaces of the first metal layer 61 and the second metal layer 62, and then bringing the first metal layer 61 into contact with the second metal layer 62. Through this activation bonding, metal atoms on the surfaces of the first metal layer 61 and the second metal layer 62—in this embodiment, gold (Au) atoms—diffuse and recombine at the contact surface between the first metal layer 61 and the second metal layer 62, thus achieving a strong bond without a bonding interface. Furthermore, by smoothing the surfaces of the first metal layer 61 and the second metal layer 62, bonding can be performed using only the free surface energy of the surfaces of the first metal layer 61 and the second metal layer 62; therefore, bonding can be performed at room temperature without active pressure.

[0041] In this way, excessive pressure or heat is not applied during bonding, so even when at least a portion of the integrated circuit 41 overlaps with the metal layer 6, i.e., the bonding portion of the semiconductor substrate 4 and the cover 3, when viewed from above, damage to the integrated circuit 41 during bonding can be reduced. Thus, since at least a portion of the integrated circuit 41 can overlap with the bonding portion of the semiconductor substrate 4 and the cover 3 when viewed from above, the vibration device 1 can be miniaturized.

[0042] In this embodiment, the first metal layer 61 of the semiconductor substrate 4 and the second metal layer 62 of the cap 3 are joined by active bonding, but atomic diffusion bonding can also be used. Similar to active bonding, atomic diffusion bonding allows the first metal layer 61 of the semiconductor substrate 4 and the second metal layer 62 of the cap 3 to be joined without applying excessive pressure or heat during bonding.

[0043] Furthermore, as described above, in this embodiment, the first metal layer 61 and the second metal layer 62 contain gold (Au). Specifically, the first metal layer 61 and the second metal layer 62 are formed of gold (Au). By using gold (Au), no metal oxide film is formed on the surface of the first metal layer 61 and the second metal layer 62. Therefore, in active bonding or atomic diffusion bonding, it is not necessary to remove the metal oxide film, so bonding can be easily performed.

[0044] Furthermore, a third metal layer 63 is provided on the bottom surface 321 of the recess 32 of the cover 3. The third metal layer 63 is provided across the entire surface of the bottom surface 321, and overlaps with at least a portion of the vibrating element 5 when viewed from above in the Z direction (normal direction) from the first surface 4h of the semiconductor substrate 4. Additionally, a fourth metal layer 64 is provided on the entire surface of the side surface 322 of the recess 32. The third metal layer 63 is electrically connected to the metal layer 6 via the fourth metal layer 64. By providing the third metal layer 63 and the fourth metal layer 64, they function as shielding layers, protecting the integrated circuit 41 and the vibrating element 5 from unwanted radiation and other interference.

[0045] In this embodiment, the fourth metal layer 64 is disposed on the entire surface of the side surface 322 of the recess 32, but it may not be disposed on the entire surface of the side surface 322 of the recess 32. The fourth metal layer 64 makes the metal layer 6 and the third metal layer 63 electrically conductive, and the third metal layer 63 functions as a shielding layer, thus protecting the integrated circuit 41 and the vibration element 5 from unnecessary radiation and other interference.

[0046] In this embodiment, the third metal layer 63 and the fourth metal layer 64 are formed of gold (Au), just like the second metal layer 62. In addition, a close-fitting layer (not shown) made of titanium (Ti) is provided between the third metal layer 63 and the bottom surface 321 of the recess 32, and between the fourth metal layer 64 and the side surface 322 of the recess 32.

[0047] By setting the thickness of the third metal layer 63 to 20 nm or less, infrared light can pass through the third metal layer 63. As described above, the cover 3 is formed of a silicon substrate, and silicon allows infrared light to pass through. Therefore, by setting the thickness of the third metal layer 63 to 20 nm or less, infrared light can be used to inspect the interior of the vibrating device 1 through the cover 3 and the third metal layer 63. Specifically, for example, it is possible to inspect the vibrating element 5 housed in the storage space S. In addition, infrared laser light can be irradiated onto the vibrating element 5 through the cover 3 and the third metal layer 63 to remove a portion of the vibrating element 5 and adjust the resonant frequency of the vibrating element 5.

[0048] The semiconductor substrate 4 includes: a flat base substrate 40; an integrated circuit 41 disposed on the upper surface of the base substrate 40; and an insulating layer 42 disposed on the upper surface of the integrated circuit 41. In other words, the integrated circuit 41 and the insulating layer 42 are disposed on the first surface 4h of the semiconductor substrate 4. In this embodiment, the base substrate 40 is a silicon substrate. However, the base substrate 40 may also be formed of a semiconductor other than silicon, such as gallium nitride.

[0049] An insulating layer 42, formed of 1 μm thick SiO2, covers the upper surface of the integrated circuit 41. The insulating layer 42 serves to protect the integrated circuit 41. Alternatively, the insulating layer 42 may not be provided.

[0050] A mounting electrode 72 is provided on the upper surface of the insulating layer 42 of the semiconductor substrate 4. The mounting electrode 72 is electrically connected to the integrated circuit 41 via a wiring 404 penetrating the insulating layer 42 and a terminal (not shown) provided on the upper surface of the integrated circuit 41. The mounting electrode 72 is used for electrically connecting the vibration element 5 (described later) and the integrated circuit 41.

[0051] Integrated circuit 41 is a circuit in which multiple active components, such as transistors (not shown), are electrically connected by wiring (not shown). Furthermore, the circuit is not particularly limited; examples include an oscillation circuit that causes the vibrating element 5 to oscillate to generate a reference signal such as a clock signal, a temperature compensation circuit that corrects the vibration characteristics of the vibrating element 5 according to temperature changes, a processing circuit that processes the output signal from the oscillation circuit, and an electrostatic discharge protection circuit.

[0052] Integrated circuit 41 has a plurality of terminals (not shown). The plurality of terminals are formed on the upper and lower surfaces of integrated circuit 41 and are electrically connected to integrated circuit 41. The plurality of terminals include terminals connected to power supply potential, terminals connected to ground potential, terminals for outputting oscillation signals, etc.

[0053] Furthermore, in a top view taken from the Z direction, which is the normal direction of the first surface 4h of the semiconductor substrate 4, in the region where the integrated circuit 41 and the metal layer 6 overlap, the integrated circuit 41 has wiring 45 as part of the integrated circuit 41. The wiring 45 included in the integrated circuit 41 is arranged in a frame shape, i.e., a closed curve shape, along the outer edge of the integrated circuit 41.

[0054] Wiring 45 functions as a power supply wiring that supplies power potential via a terminal connected to the power supply potential of integrated circuit 41, and as a grounding wiring that supplies ground potential via a terminal connected to the ground potential or an electrostatic discharge protection circuit. This protects integrated circuit 41 and vibration element 5 from unwanted radiation and other interference. Furthermore, by arranging wiring 45 in a closed curve shape, the effect of further protecting integrated circuit 41 and vibration element 5 from unwanted radiation and other interference can be improved. Additionally, wiring 45 can be a constant potential wiring supplying a constant potential such as power supply potential or ground potential, or it may not be a power supply wiring or a grounding wiring.

[0055] In addition, by using wiring (not shown) that penetrates the insulating layer 42 to electrically connect the wiring 45 and the metal layer 6, the effect of protecting the integrated circuit 41 and the vibration element 5 from unnecessary radiation and other interference can be further improved.

[0056] The base substrate 40 of the semiconductor substrate 4 has: a through hole 400 that penetrates the base substrate 40 in the Z direction, which is the thickness direction; an insulating layer 401 disposed on the inner wall surface of the through hole 400; and a through electrode 402 inserted into the through hole 400.

[0057] Furthermore, the base substrate 40 of the semiconductor substrate 4 has an insulating layer 46 disposed on the lower surface of the base substrate 40 and an external terminal 70 disposed on the lower surface of the insulating layer 46. In other words, the insulating layer 46 and the external terminal 70 are disposed on the second surface 4r of the semiconductor substrate 4.

[0058] The upper surface of the through electrode 402 is electrically connected to the integrated circuit 41 via a terminal (not shown) disposed on the lower surface of the integrated circuit 41. The lower surface of the through electrode 402 is electrically connected to an external terminal 70. The external terminal 70 and the integrated circuit 41 are electrically connected via the through electrode 402 and the terminal (not shown), thereby enabling the supply of power supply potential or ground potential to the integrated circuit 41 via the external terminal 70, or the output of clock signals from the integrated circuit 41, etc.

[0059] In this way, the external terminal 70 provided on the second surface 4r of the semiconductor substrate 4 is electrically connected to the integrated circuit 41 through the through electrode 402. As a result, in a top view viewed from the Z direction, the size of the vibration device 1 can be set to be approximately the same as that of the integrated circuit 41, and the vibration device 1 can be miniaturized.

[0060] The vibrating element 5 includes: a vibrating substrate 51, excitation electrodes 52 disposed on the upper and lower surfaces of the vibrating substrate 51, a pair of terminals 53 disposed on the lower surface of the vibrating substrate 51, and wiring 54 electrically connecting the excitation electrodes 52 and the terminals 53. In this embodiment, the vibrating substrate 51 is a quartz substrate. However, the vibrating substrate 51 is not limited to a quartz substrate; for example, it may be a piezoelectric crystal such as lithium niobate or lithium tantalate.

[0061] A pair of terminals 53 disposed on the lower surface of the vibrating element 5 are joined to a mounting electrode 72 disposed on the first surface 4h of the semiconductor substrate 4 using a conductive bonding member 56. Thus, the vibrating element 5 is fixed and disposed on the first surface 4h of the semiconductor substrate 4. Furthermore, as described above, the mounting electrode 72 is electrically connected to the integrated circuit 41. Therefore, the excitation electrodes 52 disposed on the upper and lower surfaces of the vibrating substrate 51 of the vibrating element 5 are electrically connected to the integrated circuit 41 via the mounting electrode 72, the conductive bonding member 56, the terminals 53 of the vibrating substrate 51, and the wiring 54 of the excitation electrode 52. The vibrating element 5 is oscillated using an oscillation signal output from the integrated circuit 41.

[0062] In addition, the conductive bonding component 56 may be made of various metal bumps such as gold bumps and solder bumps, or conductive adhesives obtained by dispersing conductive fillers such as silver fillers in epoxy-based or silicone-based resin adhesives.

[0063] Next, refer to Figures 4-9 The manufacturing method of the vibrating device 1 will be described. For example... Figure 4 As shown, the manufacturing method of the vibration device 1 includes a semiconductor substrate forming process, a vibration element mounting process, a cover forming process, a bonding process, and a monolithic process.

[0064] 1.1 Semiconductor substrate formation process

[0065] like Figure 4 and Figure 5 As shown, in step S1, a semiconductor substrate 4 is formed. A silicon wafer SW1, in which multiple base substrates 40 are integrated, is prepared, and through-holes 400 are formed using silicon etching techniques such as the Bosch process. After forming an insulating layer 401 on the inner wall surface of the through-holes 400, polysilicon implanted with boron ions is buried in the through-holes 400, thereby forming through electrodes 402. After forming the through electrodes 402, an integrated circuit 41, including wiring 45, is formed on the upper surface of the multiple base substrates 40. After forming the integrated circuit 41, insulating layers 42 and 46 are formed, and then external terminals 70, wiring 404, mounting electrodes 72, and a first metal layer 61 are formed.

[0066] In addition, the insulating layer 46 and the external terminal 70 disposed on the lower surface of the base substrate 40 can also be formed after the bonding process described later.

[0067] In addition, in step S1, for example, a gold (Au) film is formed by sputtering, and the film is patterned by photolithography and etching techniques, so that the mounting electrode 72 and the first metal layer 61 can be formed simultaneously.

[0068] 1.2 Vibration Component Installation Procedure

[0069] like Figure 4 and Figure 6 As shown, in step S2, the terminal 53 disposed on the lower surface of the vibration element 5 is joined to the mounting electrode 72 disposed on the first surface 4h of the semiconductor substrate 4 via the conductive bonding member 56. Thus, the vibration element 5 is fixed to the first surface 4h of the semiconductor substrate 4.

[0070] 1.3 Cap Forming Process

[0071] like Figure 4 and Figure 7As shown, in step S3, a cover 3 is formed. A silicon wafer SW2 with multiple covers 3 integrated is prepared. Using silicon etching techniques such as the Bosch process, a recess 32 is formed on the lower surface of the silicon wafer SW2, i.e., the lower surface of the cover 3. After forming the recess 32, a second metal layer 62 is formed on the abutment surface 31 provided along the outer edge of the recess 32 of the cover 3, a third metal layer 63 is formed on the bottom surface 321 of the recess 32 of the cover 3, and a fourth metal layer 64 is formed on the side surface 322 of the recess 32. For example, a gold (Au) film can be formed on the entire lower surface of the silicon wafer SW2 using a sputtering method, thereby simultaneously forming the second metal layer 62, the third metal layer 63, and the fourth metal layer 64.

[0072] 1.4 Joining process

[0073] like Figure 4 and Figure 8 As shown, in step S4, the first surface 4h of the semiconductor substrate 4 and the abutment surface 31 of the cover 3 are bonded via the first metal layer 61 and the second metal layer 62. As a bonding method, in this embodiment, activated bonding is used as described above. Through activated bonding, the first metal layer 61 and the second metal layer 62 are bonded to form a metal layer 6. In this manner, silicon wafer SW1 and silicon wafer SW2 are bonded together, thereby obtaining a silicon wafer in which a plurality of vibrating devices 1 are integrally formed.

[0074] In addition, after the bonding process, the silicon wafer can be thinned by grinding and polishing, thereby making the vibrating device 1 thinner. Specifically, the upper surface of the silicon wafer, i.e., the upper surface of the cover 3, on which multiple vibrating devices 1 are integrally formed, can be thinned by grinding and polishing, and the lower surface of the silicon wafer, i.e., the second surface 4r of the semiconductor substrate 4, can also be thinned by grinding and polishing.

[0075] In this embodiment, the integrated circuit 41 and the vibration element 5 are disposed on the first surface 4h of the semiconductor substrate 4. Therefore, by grinding and polishing the second surface 4r, which is opposite to the first surface 4h of the semiconductor substrate 4, the vibration device 1 can be made thinner. In this way, it is not necessary to grind and polish the first surface 4h of the semiconductor substrate 4 on which the vibration element 5 is mounted before mounting the vibration element 5, and thus the vibration device 1 can be easily made thinner.

[0076] In addition, if the second surface 4r of the semiconductor substrate 4 is ground and polished after the bonding process to make the silicon wafer thinner, an insulating layer 46 and an external terminal 70 are formed on the second surface 4r of the semiconductor substrate 4 after thinning.

[0077] 1.5 Single-piece manufacturing process

[0078] like Figure 4 as well as Figure 9As shown, in step S5, each vibrating device 1 is monolithized from the silicon wafer using cutting or other cutting methods.

[0079] Through the above manufacturing processes, the vibration device 1 can be manufactured.

[0080] As described above, the following effects can be obtained according to this embodiment. It includes: a semiconductor substrate 4 having a first surface 4h on which an integrated circuit 41 and a vibrating element 5 are disposed; a cover 3 having an abutting surface 31 that abuts against the first surface 4h and is bonded to the first surface 4h at the abutting surface 31; and a metal layer 6 disposed between the first surface 4h and the abutting surface 31. In a top view taken from the Z direction, which is the normal direction of the first surface 4h, at least a portion of the integrated circuit 41 overlaps with the metal layer 6 at the junction of the semiconductor substrate 4 and the cover 3, thereby enabling miniaturization of the vibrating device 1.

[0081] Furthermore, the second surface 4r of the semiconductor substrate 4, which does not have the integrated circuit 41 and the vibration element 5, can be ground and polished, thus making the vibration device 1 easily thinner.

[0082] Furthermore, the aforementioned vibration device 1 can preferably be used as an oscillator, an acceleration sensor, an angular velocity sensor, or other inertial sensor.

Claims

1. A vibrating device, comprising: A semiconductor substrate having a first side on which an integrated circuit is disposed and a second side opposite to the first side; A vibrating element, which is disposed on the first surface; The cover has a recess that opens on the first side and an abutting surface that abuts against the first surface in such a way as to receive the vibrating element in the recess, and engages with the first surface at the abutting surface; as well as A metal layer disposed between the first surface and the abutment surface. When viewed from the normal direction of the first surface, at least a portion of the integrated circuit overlaps with the metal layer. An insulating layer is provided between the metal layer and the integrated circuit.

2. A vibrating device, comprising: A semiconductor substrate having a first side on which an integrated circuit is disposed and a second side opposite to the first side; A vibrating element, which is disposed on the first surface; The cover has a recess that opens on the first side and an abutting surface that abuts against the first surface in such a way as to receive the vibrating element in the recess, and engages with the first surface at the abutting surface; as well as A metal layer disposed between the first surface and the abutment surface. When viewed from the normal direction of the first surface, at least a portion of the integrated circuit overlaps with the metal layer. An external terminal is provided on the second surface, and the integrated circuit and the external terminal are electrically connected via a through electrode disposed on the semiconductor substrate.

3. The vibration device according to claim 1 or 2, wherein, The metal layer is formed by the activation bonding of a first metal layer disposed on the first surface and a second metal layer disposed on the abutting surface.

4. The vibration device according to claim 1 or 2, wherein, The metal layer contains Au.

5. The vibration device according to claim 1 or 2, A third metal layer electrically connected to the metal layer is provided on the bottom surface of the recess of the cover.

6. The vibration device according to claim 5, wherein, The thickness of the third metal layer is less than 20 nm.

7. The vibration device according to claim 1 or 2, wherein, In the top view, wiring, which is part of the integrated circuit, is provided in at least a portion of the region where the integrated circuit overlaps with the metal layer. The wiring is constant potential wiring.

8. The vibration device according to claim 1 or 2, wherein, In the top view, wiring, which is part of the integrated circuit, is provided in at least a portion of the region where the integrated circuit overlaps with the metal layer. The wiring is power supply wiring.

9. The vibration device according to claim 7, wherein, The wiring appears as a closed curve when viewed from above.

Images