Fractional-N phase-locked loop and its charge pump control method

By using a split charge pump and a frequency divider clock controller with variable delay, the phase noise problem of fractional-N phase-locked loops when synthesizing non-integer multiples of the reference clock frequency is solved, achieving noise reduction and improved overall performance without increasing area and power consumption.

CN114389599BActive Publication Date: 2026-05-26MEDIATEK INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MEDIATEK INC
Filing Date
2021-10-18
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

Existing fractional-N phase-locked loops are prone to introducing phase noise when synthesizing reference clock frequencies that are not integer multiples of the reference clock frequency, and existing noise reduction methods require complex calibration mechanisms or increase circuit area and power consumption.

Method used

By employing a split charge pump approach, the current source and phase frequency detector of the fractional-N PLL are divided into multiple branches. A variable-delay frequency divider clock controller is used to reduce phase noise, avoid noise folding problems, and reduce reliance on calibration mechanisms.

Benefits of technology

Without increasing circuit area and power consumption, the overall phase noise of fractional-N PLLs is significantly reduced, improving overall performance while maintaining noise-dependent performance.

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Abstract

A fractional-N phase-locked loop (PLL) and its charge pump control method are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a frequency divider clock controller. The first current source provides a first current. The first PFD generates a first detection signal based on a first frequency divider clock to control the first current source, wherein the first frequency divider clock is generated based on an oscillation clock with an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal based on a second frequency divider clock to control the second current source. The frequency divider controller controls the second frequency divider clock based on a variable delay relative to the first frequency divider clock, wherein the variable delay is an integer multiple of the oscillation period. Using this method, phase noise can be reduced.
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