Multiplying digital-to-analog converters with presampling and related pipelined analog-to-digital converters

Abstract

A multiplying digital-to-analog converter (MDAC) includes an operational amplifier, a sample capacitor circuit, a pre-sample capacitor circuit, and a switching circuit. During a sample period, the switching circuit connects a predefined voltage, a plurality of reference voltages to the pre-sample capacitor circuit, disconnects the pre-sample capacitor from an input port of the operational amplifier, disconnects the pre-sample capacitor circuit from the sample capacitor circuit, disconnects an output port of the operational amplifier from the sample capacitor circuit, and connects a voltage input of the MDAC to the sample capacitor circuit. During a conversion period, the switching circuit connects the pre-sample capacitor circuit to the sample capacitor circuit, disconnects the predefined voltage from the pre-sample capacitor circuit, disconnects the plurality of reference voltages from the pre-sample capacitor circuit, connects the pre-sample capacitor circuit to an input of the operational amplifier, connects an output of the operational amplifier to the sample capacitor circuit, and disconnects the voltage input from the sample capacitor circuit.

Description

Technical Field

[0001] This invention relates to the conversion between analog and digital signals, and more specifically, to a multiplying digital-to-analog converter (MDAC) with presampling and an associated pipelined analog-to-digital converter (ADC). Background Technology

[0002] Analog-to-digital converters (ADCs) are used in a variety of electronic systems. Such systems require cost-effective ADCs that can efficiently convert analog input signals into digital output signals over a wide frequency range and signal amplitude, while minimizing noise and distortion.

[0003] An analog-to-digital converter (ADC) typically converts an analog signal into a digital signal by sampling it at predetermined sampling intervals and generating a sequence of binary numbers via a quantizer. This binary sequence is the digital representation of the sampled analog signal. Some common types of ADCs include flash ADCs, pipelined ADCs, and successive approximation register (SAR) ADCs. Among these different types, pipelined ADCs are particularly popular in applications requiring high resolution. Typical pipelined ADCs use switched-capacitor circuitry to add or remove charge and active circuitry such as operational amplifiers to implement multiplication. They are highly susceptible to component mismatches (such as capacitor mismatches) and circuit defects (such as limited amplifier gain). Furthermore, typical pipelined ADCs may employ high-gain and high-speed operational amplifiers, resulting in high power consumption and the need for background calibration. Therefore, there is a need for an innovative, low-power pipelined ADC that does not require background calibration. Summary of the Invention

[0004] One of the objectives of this invention is to provide a pre-sampled multiplication digital-to-analog converter (MDAC) and an associated pipelined analog-to-digital converter (ADC).

[0005] According to a first aspect of the present invention, an exemplary multiplication digital-to-analog converter (MDAC) is disclosed. The exemplary MDAC includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switching circuit. The operational amplifier has an input port and an output port. The switching circuit controls the interconnection between the operational amplifier, the sampling capacitor circuit, and the pre-sampling capacitor circuit. During the sampling period of the MDAC, the switching circuit is configured to connect a predefined voltage to the pre-sampling capacitor circuit, connect multiple reference voltages to the pre-sampling capacitor circuit, disconnect the pre-sampling capacitor circuit from the input port of the operational amplifier, disconnect the pre-sampling capacitor circuit and the sampling capacitor circuit, disconnect the output port of the operational amplifier from the sampling capacitor circuit, and connect the voltage input of the MDAC to the sampling capacitor circuit. During the conversion period of the MDAC, the switching circuit connects the pre-sampling capacitor circuit to the sampling capacitor circuit, wherein the connection configuration between the pre-sampling capacitor circuit and the sampling capacitor circuit depends on the quantization result of the voltage input, further disconnects the predefined voltage from the pre-sampling capacitor circuit, disconnects the multiple reference voltages from the pre-sampling capacitor circuit, connects the pre-sampling capacitor circuit to the input terminal of the operational amplifier, connects the output terminal of the operational amplifier to the sampling capacitor circuit, and disconnects the voltage input from the sampling capacitor circuit.

[0006] Specifically, connecting a predefined voltage to the pre-sampling capacitor circuit means providing the predefined voltage to the pre-sampling capacitor circuit; connecting multiple reference voltages to the pre-sampling capacitor circuit means providing multiple reference voltages to the pre-sampling capacitor circuit; connecting the voltage input of the MDAC to the sampling capacitor circuit means providing the voltage input of the MDAC to the sampling capacitor circuit; disconnecting the predefined voltage from the pre-sampling capacitor circuit means not providing the predefined voltage to the pre-sampling capacitor circuit; disconnecting multiple reference voltages from the pre-sampling capacitor circuit means not providing multiple reference voltages to the pre-sampling capacitor circuit; and disconnecting the voltage input from the sampling capacitor circuit means not providing the voltage input to the sampling capacitor circuit.

[0007] According to a second aspect of the invention, an exemplary pipelined analog-to-digital converter (ADC) is disclosed. The exemplary pipelined ADC includes multiple stages and combinational circuitry. These stages are arranged to generate multiple digital outputs, respectively. The combinational circuitry is arranged to combine the multiple digital outputs. At least one of the multiple stages includes a quantization circuit and a multiplicative digital-to-analog converter (MDAC). The quantization circuitry is arranged to generate a quantized result of a voltage input to the at least one of the multiple stages, wherein the digital output of the at least one of the multiple stages depends on the quantized result of the voltage input. The MDAC includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switching circuit. The operational amplifier has an input port and an output port. The switching circuitry is used to control the interconnections between the operational amplifier, the sampling capacitor circuit, and the pre-sampling capacitor circuit. During the sampling period of the MDAC, the switching circuit is configured to connect a predefined voltage to the pre-sampling capacitor circuit, connect multiple reference voltages to the pre-sampling capacitor circuit, disconnect the pre-sampling capacitor circuit from the input port of the operational amplifier, disconnect the pre-sampling capacitor circuit and the sampling capacitor circuit, disconnect the output port of the operational amplifier from the sampling capacitor circuit, and connect the voltage input of the MDAC to the sampling capacitor circuit; and during the conversion period of the MDAC, the switching circuit is configured to connect the pre-sampling capacitor circuit to the sampling capacitor circuit, wherein the connection configuration between the pre-sampling capacitor circuit and the sampling capacitor circuit depends on the quantization result of the voltage input, further disconnect the predefined voltage from the pre-sampling capacitor circuit, disconnect the multiple reference voltages from the pre-sampling capacitor circuit, connect the pre-sampling capacitor circuit to the input port of the operational amplifier, connect the output port of the operational amplifier to the sampling capacitor circuit, and disconnect the voltage input from the sampling capacitor circuit.

[0008] According to a third aspect of the present invention, an MDAC is provided, comprising: an operational amplifier; a sampling capacitor circuit; and a pre-sampling capacitor circuit; wherein, during a sampling period of the MDAC, the pre-sampling capacitor circuit samples and holds a plurality of pre-sampling reference voltages, and the sampling capacitor circuit samples a voltage input of the MDAC; wherein, during a conversion period of the MDAC, the pre-sampling capacitor circuit is coupled to the sampling capacitor circuit, and the operational amplifier sets a voltage output at its output port according to the voltage input and one of the plurality of pre-sampling reference voltages; the connection configuration between the pre-sampling capacitor circuit and the sampling capacitor circuit depends on a quantization result of the voltage input, and the voltage output is obtained from a voltage combination based on the voltage input and one of the plurality of pre-sampling reference voltages.

[0009] According to a fourth aspect of the present invention, a pipelined analog-to-digital converter (ADC) is provided, comprising a plurality of stages connected in a pipelined manner and arranged to generate a plurality of digital outputs respectively; and a combination circuit for combining the plurality of digital outputs; wherein at least one of the plurality of stages includes: a quantization circuit and the aforementioned MDAC.

[0010] The multiplication digital-to-analog converter (MDAC) and pipelined ADC provided in this invention can reduce the power consumed by the operational amplifier.

[0011] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a pre-sampled multiplicative digital-to-analog converter (MDAC) according to an embodiment of the present invention.

[0013] Figure 2 This is a circuit diagram of a pre-sampled MDAC according to an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram illustrating the principle of the proposed MDAC design with presampling according to an embodiment of the present invention.

[0015] Figure 4 To show Figure 2 The transmission curve of the MDAC is shown in the figure.

[0016] Figure 5 It is shown Figure 2 The diagram shows the equivalent circuit of the MDAC operating during the sampling period.

[0017] Figure 6 It is shown Figure 2 The diagram shows the equivalent circuit of an MDAC operating under the condition (Vip-Vin) > Vref / 4 during the conversion cycle.

[0018] Figure 7 It is shown Figure 2 The diagram shows the equivalent circuit of an MDAC operating under the condition -Vref / 4≦(Vip-Vin)≦Vref / 4 during the conversion cycle, where ≦ indicates less than or equal to.

[0019] Figure 8 It is shown Figure 2 The diagram shown is an equivalent circuit diagram of an MDAC operating under the condition (Vip-Vin) < -Vref / 4 during the conversion cycle.

[0020] Figure 9 This is a schematic diagram illustrating common-mode suppression implemented by a proposed MDAC with presampling according to an embodiment of the present invention.

[0021] Figure 10 This is a schematic diagram illustrating a differential amplifier without a tail current source according to an embodiment of the present invention.

[0022] Figure 11 This is a circuit diagram of an MDAC with presampling and a CLS-assisted operational amplifier according to an embodiment of the present invention.

[0023] Figure 12 It is shown by Figure 11 The diagram illustrates the operation of the DAC-subtract-gain function performed by the MDAC, which includes a sampling period, a first stage of the conversion period, and a second stage of the conversion period, wherein the second stage includes a reset (RST) operation.

[0024] Figure 13 It is shown in Figure 11 The diagram shows the voltage levels of the amplifier output and the MDAC output during the MDAC's conversion cycle.

[0025] Figure 14 It is shown in Figure 11 The operation shown is the equivalent circuit diagram of the MDAC in the first stage of the conversion cycle.

[0026] Figure 15 It is shown in Figure 11 The operation shown is the equivalent circuit diagram of the MDAC at the beginning of the second stage of the conversion cycle.

[0027] Figure 16 It is shown Figure 11 The diagram shows the equivalent circuit of the MDAC during the remaining period of the second stage of the conversion cycle.

[0028] Figure 17 This is a schematic diagram illustrating a pipelined ADC according to an embodiment of the present invention.

[0029] Figure 18 This is a circuit diagram illustrating another MDAC with presampling according to an embodiment of the present invention.

[0030] Figure 19 This is a circuit diagram of a pre-sampled MDAC that uses common-mode voltage as a predefined voltage according to an embodiment of the present invention.

[0031] Figure 20 This is a circuit diagram of a pre-sampled MDAC using different switch arrangements according to an embodiment of the present invention. Detailed Implementation

[0032] Certain terms used in the following description and claims refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to components. This application is not intended to distinguish between components with different names but identical functions. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". Furthermore, the term "coupled" is intended to indicate an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection can be a direct electrical connection or an indirect electrical connection via other devices and connections.

[0033] Figure 1 This is a block diagram illustrating a multiplying digital-to-analog converter (MDAC) with presampling according to an embodiment of the present invention. The MDAC 100 includes an operational amplifier 102, a switching circuit 104, and a plurality of capacitor circuits including a presampling capacitor circuit 106 and a sampling capacitor circuit 108. The operational amplifier 102 has an input port 112 and an output port 114. For example, the input port 112 may include a non-inverting input node (+) and an inverting input node (-), and the output port 114 may include a non-inverting output node (+) and an inverting output node (-). Since the MDAC 100 is a switched capacitor circuit, the switching circuit 104 is arranged to control the interconnection between the operational amplifier 102, the sampling capacitor circuit 108, and the presampling capacitor circuit 106.

[0034] The operation of the DAC-subtract-gain function performed by the MDAC 100 can be divided into a sampling period and a conversion period after the sampling period. During the sampling period of the MDAC 100, the switching circuit 104 is configured to connect a predefined voltage Vpd to the pre-sampling capacitor circuit 106, connect multiple reference voltages (e.g., Vrefn, Vcm, and Vrefp, where Vrefp > Vcm > Vrefn and Vcm = Vrefp + Vrefn = 0V) to the pre-sampling capacitor circuit 106, disconnect the pre-sampling capacitor circuit 106 from the input port 112 of the operational amplifier 102, disconnect the pre-sampling capacitor circuit 106 from the sampling capacitor circuit 108, disconnect the output port 114 of the operational amplifier 102 from the sampling capacitor circuit 108, and connect the voltage input V_IN of the MDAC 100 to the sampling capacitor circuit 108. For example, the voltage input V_IN can be a differential input, which includes a positive signal Vip and a negative signal Vin (i.e., V_IN = Vip - Vin).

[0035] During the conversion cycle of the MDAC100, the switching circuit 104 connects the presampling capacitor circuit 106 to the sampling capacitor circuit 108, wherein the connection configuration between the presampling capacitor circuit 106 and the sampling capacitor circuit 108 depends on the quantization result of the voltage input V_IN. The switching circuit 104 also disconnects a predefined voltage Vpd from the presampling capacitor circuit 106, disconnects a reference voltage (e.g., Vrefn, Vcm, and Vrefp) from the presampling capacitor circuit 106, connects the presampling capacitor circuit 106 to the input port 112 of the operational amplifier 102, connects the output port 114 of the operational amplifier 102 to the sampling capacitor circuit 108, and disconnects the sampling capacitor circuit 108 from the voltage input V_IN. Using the presampling capacitor circuit 106 can relax the power requirements of the operational amplifier and the reference buffer.

[0036] Figure 2 This is a circuit diagram of a pre-sampled MDAC according to an embodiment of the present invention. Figure 1 The MDAC 100 shown can be... Figure 2The MDAC 200 implementation is shown. The MDAC 200 includes an operational amplifier OPAMP, multiple presampling capacitors Cps1, Cps0, Cps-1, C'ps1, C'ps0, C'ps-1, multiple sampling capacitors Csam, C'sam, and multiple switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW'1, SW'2, SW'3, SW'4, SW'5, SW'6, SW'7, SW'8, SW'9, SW'10, SW'11. Figure 1 The operational amplifier 102 shown can be used Figure 2 The operational amplifier OPAMP shown is used to implement this, where the operational amplifier OPAMP is a differential amplifier with input ports including a non-inverting input node (+) and an inverting input node (-), and output ports including an inverting output node (-) and a non-inverting output node (+). Figure 1 The pre-sampling capacitor circuit 106 shown can be used Figure 2 The presampling capacitors Cps1, Cps0, Cps-1, C'ps1, C'ps0, and C'ps-1 shown are used to implement this. Figure 1 The sampling capacitor circuit 108 shown can be used Figure 2 The sampling capacitors Csam and C'sam shown are used to implement this. Figure 1 The switch circuit 104 shown can be used Figure 2 This is achieved using the switches SW1-SW11 and SW'1-SW'11 shown.

[0037] Presampling capacitors Cpsl, Cps0, Cps-1, C'psl, C'ps0, and C'ps-1 are used to presample Vref, 0V, and -Vref, where Vrefp - Vrefn = Vref, Vrefn - Vrefp = -Vref, and Vcm = 0V. Sampling capacitors Csam and C'sam are used to sample the voltage input (Vip-Vin), which is a differential input including the positive signal Vip and the negative signal Vin. The principle of the proposed MDAC design with presampling is to combine the voltage difference held by capacitors to achieve reference voltage subtraction and input voltage amplification. Figure 3This is a schematic diagram illustrating the principle of the proposed MDAC design with presampling according to an embodiment of the present invention. It is assumed that a voltage difference ΔV1 is maintained between the top and bottom plates of capacitor C1, and another voltage difference ΔV2 is maintained between the top and bottom plates of capacitor C2. When capacitors C1 and C2 are connected in series, the voltage across the series-connected capacitors C1 and C2 is equal to ΔV1 + ΔV2. For MDAC200, the voltage output V_OUT serves as the MDAC output and is determined by ΔV1 = 2*(Vip - Vin) and ΔV2 = Dout * Vref, i.e., V_OUT = 2*(Vip - Vin) + Dout * Vref. The voltage 2*(Vip - Vin) is obtained through the sampling capacitor. The voltage Dout * Vref is achieved through the selection of the presampling capacitor. Figure 4 It is shown Figure 2 The diagram shows a schematic of the transfer curve for the MDAC 200. If (Vip-Vin) > Vref / 4, then Dout = -1 and V_OUT = 2*(Vip-Vin) + Vref. If -Vref / 4 ≦ (Vip-Vin) ≦ Vref / 4, then Dout = 0 and V_OUT = 2*(Vip-Vin). When (Vip-Vin) < -Vref / 4, Dout = +1 and V_OUT = 2*(Vip-Vin) - Vref. Further details of the proposed MDAC200 with presampling are described below.

[0038] As described above, the operation of the DAC subtract-gain function performed by the MDAC 200 is divided into a sampling period and a conversion period following the sampling period. For example, the sampling period is enabled by a first clock, and the conversion period is enabled by a second clock, where the first and second clocks are non-overlapping clocks, and the on / off state of the switch can be controlled by the first and second clocks. One node of switch SW1 is coupled to a predefined voltage (e.g., the bias voltage Vbias of the operational amplifier OPAMP), while the other node is coupled to a plate of each of the pre-sampling capacitors Cps1, Cps0, and Cps-1. In this embodiment, Vpd = Vbias. One node of switch SW'1 is coupled to a predefined voltage (e.g., the bias voltage Vbias of the operational amplifier OPAMP), and the other node is coupled to a plate of each of the pre-sampling capacitors C'ps1, C'ps0, and C'ps-1. Switch SW5 has one node coupled to the non-inverting input node (+) of operational amplifier OPAMP, and another node coupled to one plate of each of presampling capacitors Cps1, Cps0, and Cps-1. Switch SW'5 has one node coupled to the inverting input node (-) of operational amplifier OPAMP, and another node coupled to one plate of each of presampling capacitors C'ps1, C'ps0, and C'ps-1. Switch SW9 has one node coupled to the inverting output node (-) of operational amplifier OPAMP, and another node coupled to one plate of sampling capacitor Csam. Switch SW'9 has one node coupled to the non-inverting output node (+) of operational amplifier OPAMP, and another node coupled to one plate of sampling capacitor C'sam.

[0039] One node of switch SW2 is coupled to the reference voltage Vrefp, and the other node is coupled to the other plate of pre-sampling capacitor Cps1. One node of switch SW'2 is coupled to the reference voltage Vrefn, and the other node is coupled to the other plate of pre-sampling capacitor C'ps1. One node of switch SW3 is coupled to the reference voltage Vcm, and the other node is coupled to the other plate of pre-sampling capacitor Cps0. One node of switch SW'3 is coupled to the reference voltage Vcm, and the other node is coupled to the other plate of pre-sampling capacitor C'ps0. One node of switch SW4 is coupled to the reference voltage Vrefn, and the other node is coupled to the other plate of pre-sampling capacitor Cps-1. One node of switch SW'4 is coupled to the reference voltage Vrefp, and the other node is coupled to the other plate of pre-sampling capacitor C'ps-1. When a pair of pre-sampling capacitors Cps1 and C'ps1 are selected to provide the pre-sampling reference voltage Vref based on the quantization result of the voltage input, the pre-sampling capacitor pairs Cps0 and C'ps0, and Cps-1 and C'ps-1 are not selected.

[0040] One node of switch SW6 is coupled to the other plate of pre-sampling capacitor Cps1, and the other node of switch SW6 is coupled to the other plate of sampling capacitor Csam. One node of switch SW7 is coupled to the other plate of pre-sampling capacitor Cps0, and the other node is coupled to the other plate of sampling capacitor Csam. One node of switch SW8 is coupled to the other plate of pre-sampling capacitor Cps-1, and the other node of switch SW8 is coupled to the other plate of sampling capacitor Csam. One node of switch SW'6 is coupled to the other plate of pre-sampling capacitor C'ps1, and the other node is coupled to the other plate of sampling capacitor C'sam. One node of switch SW'7 is coupled to the other plate of pre-sampling capacitor C'ps0, and the other node is coupled to the other plate of sampling capacitor C'sam. One node of switch SW'8 is coupled to the other plate of pre-sampling capacitor C'ps-1, and the other node is coupled to the other plate of sampling capacitor C'sam.

[0041] Switch SW10 has one node coupled to the other plate of the sampling capacitor Csam and another node coupled to the negative signal Vin of the differential voltage input. Switch SW11 has one node coupled to one plate of the sampling capacitor Csam and the other node coupled to the positive signal Vip of the differential voltage input. Switch SW'10 has one node coupled to the other plate of the sampling capacitor C'sam and the other node coupled to the positive signal Vip of the differential voltage input. Switch SW'11 has one node coupled to one plate of the sampling capacitor C'sam and the other node coupled to the negative signal Vin of the differential voltage input.

[0042] During the sampling period, each of switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, and SW'11 is turned on, and each of switches SW5, SW6, SW7, SW8, SW9, SW'5, SW'6, SW'7, SW'8, and SW'9 is turned off. Figure 5 This is an equivalent circuit diagram of the MDAC200 operating during the sampling period. For a period of time, the voltage difference (Vrefp - Vbias) is maintained between the two plates of the pre-sampling capacitor Cps1. For a period of time, the voltage difference (Vcm - Vbias) is maintained between the two plates of the pre-sampling capacitor Cps0. For a period of time, the voltage difference (Vrefn - Vbias) is maintained between the two plates of the pre-sampling capacitor Cps-1. For a period of time, the voltage difference (Vrefn - Vbias) is maintained between the two plates of the pre-sampling capacitor C'ps1. For a period of time, the voltage difference (Vcm - Vbias) is maintained between the two plates of the pre-sampling capacitor C'ps0. For a period of time, the voltage difference (Vrefp - Vbias) is maintained between the two plates of the pre-sampling capacitor C'ps-1. For a period of time, the voltage difference (Vin - Vip) is maintained between the two plates of the sampling capacitor Csam. The voltage difference (Vip - Vin) is maintained between the two plates of the sampling capacitor C'sam.

[0043] During the conversion cycle, each of switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, and SW'11 is open, and each of switches SW5, SW9, SW'5, and SW'9 is closed. Each of switches SW6, SW7, SW8, SW'6, SW'7, and SW'8 is selectively closed in response to the quantization result of the voltage input (Vip-Vin). When presampling capacitor pairs Cps1 and C'ps1 are selected to provide the presampling reference voltage Vref (i.e., Vrefp-Vrefn) based on the quantization result of the voltage input (Vip-Vin), presampling capacitor pairs Cps0 and C'ps0, as well as presampling capacitor pairs Cps-1 and C'ps-1, are not selected. When the presampling capacitor pairs Cps0 and C'ps0 are selected to provide a presampling reference voltage of 0V (i.e., Vcm-Vcm) based on the quantization result of the voltage input (Vip-Vin), the sampling capacitor pairs Cps1 and C'ps1, as well as the presampling capacitor pairs Cps-1 and C'ps-1, are not selected. When the presampling capacitor pairs Cps-1 and C'ps-1 are selected to provide a presampling reference voltage of -Vref (i.e., Vrefn-Vrefp) based on the quantization result of the voltage input (Vip-Vin), the presampling capacitor pairs Cps0 and C'ps0, as well as the presampling capacitor pairs Cps1 and C'ps1, are not selected.

[0044] For example, when (Vip-Vin) is greater than Vref / 4, the quantization result of the voltage input (Vip-Vin) can produce a 2-digit output "11". The decision circuit can refer to the quantization result to switch on switches SW8 and SW'8 and switch off switches SW6, SW6', SW7 and SW'7. Figure 6 This is the equivalent circuit diagram of the MDAC200 during the conversion cycle under the condition that (Vip-Vin) > Vref / 4. Figure 6As shown, presampling capacitor Cps-1 and sampling capacitor Csam are connected in series, and presampling capacitor C'ps-1 and sampling capacitor C'sam are also connected in series. One plate of presampling capacitor Cps-1 is connected to the virtual ground (floating ground) of operational amplifier OPAMP, and the other plate of presampling capacitor C'ps-1 is connected to the virtual ground (floating ground) of operational amplifier OPAMP. The voltage difference between the inverting output node (-) and the non-inverting input node (+) of operational amplifier OPAMP is equal to (Vip - Vin) + (Vrefn - Vbias). The voltage difference between the non-inverting output node (+) and the inverting input node (-) of operational amplifier OPAMP is equal to (Vin - Vip) + (Vrefp - Vbias). Therefore, the voltage output V_OUT can be expressed as follows:

[0045] V_OUT=(Vip-Vin)+(Vrefn-Vbias)-[(Vin-Vip)+(Vrefp-Vbias)]

[0046] =2*(Vip-Vin)+(Vrefn-Vrefp)

[0047] =2*(Vip-Vin)-Vref

[0048] For example, when (Vip-Vin) is not greater than Vref / 4 and not less than -Vref / 4, the quantization result of the voltage input (Vip-Vin) can produce a 2-bit digital output "01". The decision circuit can refer to the quantization result to turn on switches SW7 and SW'7 and turn off switches SW6, SW6', SW8 and SW'8. Figure 7 This is an equivalent circuit diagram showing the MDAC200 operating under the condition -Vref / 4≦(Vip-Vin)≦Vref / 4 during the conversion cycle. (Example) Figure 7 As shown, the presampling capacitor Cps0 is connected in series with the sampling capacitor Csam, and the presampling capacitor C'ps0 is connected in series with the sampling capacitor C'sam. One plate of the presampling capacitor Cps0 is connected to the virtual ground (floating ground) of the operational amplifier OPAMP, and the other plate of the presampling capacitor C'ps0 is connected to the virtual ground (floating ground) of the operational amplifier OPAMP. The voltage difference between the inverting output node (-) and the non-inverting input node (+) of the operational amplifier OPAMP is equal to (Vip - Vin) + (Vcm - Vbias). The voltage difference between the non-inverting output node (+) and the inverting input node (-) of the operational amplifier OPAMP is equal to (Vin - Vip) + (Vcm - Vbias). Therefore, the voltage output V_OUT can be expressed as follows:

[0049] V_OUT=(Vip-Vin)+(Vcm-Vbias)-[(Vin-Vip)+(Vcm-Vbias)]

[0050] =2*(Vip-Vin)

[0051] For example, when (Vip-Vin) is less than -Vref / 4, the quantization result of the voltage input (Vip-Vin) can produce a 2-digit digital output "00". The decision circuit can refer to the quantization result to turn on switches SW6 and SW'6 and turn off switches SW7, SW7', SW8 and SW'8. Figure 8 This is an equivalent circuit diagram of the MDAC200 operating under the condition (Vip-Vin) < -Vref / 4 during the conversion cycle. (Example) Figure 8 As shown, the presampling capacitor Cps1 is connected in series with the sampling capacitor Csam, and the presampling capacitor C'ps1 is connected in series with the sampling capacitor C'sam. One plate of the presampling capacitor Cps1 is connected to the virtual ground (floating ground) of the operational amplifier OPAMP, and the other plate of the presampling capacitor C'ps1 is connected to the virtual ground (floating ground) of the operational amplifier OPAMP. The voltage difference between the inverting output node (-) and the non-inverting input node (+) of the operational amplifier OPAMP is equal to (Vip - Vin) + (Vrefp - Vbias). The voltage difference between the non-inverting output node (+) and the inverting input node (-) of the operational amplifier OPAMP is equal to (Vin - Vip) + (Vrefn - Vbias). Therefore, the voltage output V_OUT can be expressed as follows:

[0052] V_OUT=(Vip-Vin)+(Vrefp-Vbias)-[(Vin-Vip)+(Vrefn-Vbias)]

[0053] =2*(Vip-Vin)+(Vrefp-Vrefn)

[0054] =2*(Vip-Vin)+Vref

[0055] Because one plate of the selected pre-sampled capacitor receiving Vbias is floating during the sampling period, the operational amplifier (OPAMP) does not need to consume power to drive any capacitive load during the switching period, thus the OPAMP has relaxed power requirements. Furthermore, from Figure 6-8As can be seen, the voltage output V_OUT is derived by combining the voltage across the selected pre-sampling capacitor and the voltage across the sampling capacitor. Therefore, the operational amplifier OPAMP has a feedback factor (β) equal to 1. Compared to an operational amplifier with β < 1, the operational amplifier OPAMP can have a wider bandwidth or lower power consumption. Furthermore, since there is no charge flow between the selected pre-charge capacitors Cps1 / Cps0 / Cps-1 / C'ps1 / C'ps0 / C'ps-1 and the sampling capacitors Csam / C'sam during the conversion cycle, there is no voltage change on one plate of the selected pre-charge capacitors Cps1 / Cps0 / Cps-1 / C'ps1 / C'ps0 / C'ps-1 that receive the reference voltage Vrefp / Vcm / Vrefn provided by the external reference buffer. Since the reference buffer does not consume additional power to maintain the reference voltage Vrefp / Vcm / Vrefn during the conversion cycle, the power requirements of the reference buffer are relaxed.

[0056] As described above, the voltage output V_OUT is derived by combining the voltage across the selected pre-sampling capacitor (also known as the voltage across the pre-sampling capacitor) with the voltage across the sampling capacitor (also known as the voltage across the sampling capacitor), where one plate of the selected pre-charge capacitor receives a reference voltage provided by an external reference buffer. The output common-mode voltage is not determined by the input common-mode voltage. Therefore, the proposed MDAC200 with pre-sampling can suppress input common-mode offset. Figure 9 This is a schematic diagram of common-mode rejection implemented by the proposed MDAC200 with pre-sampling according to an embodiment of the present invention. Assume that the positive signal Vip of the differential voltage input has a common-mode offset (e.g., 10mV), and the negative signal Vin of the differential voltage input also has a common-mode offset (e.g., 10mV). During the sampling period, a fixed common-mode voltage appears across the pre-sampling capacitor. During the conversion period, the pre-sampling capacitor and the sampling capacitor are connected in series, and the voltage across the series-connected pre-sampling capacitor and the sampling capacitor is equal to the sum of the voltages across the pre-sampling capacitor and the sampling capacitor. Therefore, the output common-mode voltage is determined by the fixed common-mode voltage provided by the pre-sampling capacitor, and is independent of the input common-mode offset (e.g., 10mV).

[0057] Traditional differential amplifiers can provide a tail current source as an effective technique to address common-mode offset issues. However, conventional differential amplifiers with tail current sources typically sacrifice speed to address these issues. Since the proposed MDAC200 with presampling suppresses input common-mode offset, the operational amplifier OPAMP can be implemented using a differential amplifier without a tail current source, such as... Figure 10As shown. For example, an operational amplifier (OPAMP) can be a telescopic differential amplifier without a tail current source. Since the OPAMP does not use a tail current source, the output current is no longer limited by the tail current source. In this way, the OPAMP can operate at higher speeds to adjust the output current according to the differential amplifier input (e.g., by...). Figure 10 The telescopic differential amplifier shown receives {OP} in1 ,OP ip1} and {OP in0 ,OP ip0}), set the differential amplifier output ( Figure 10 The OP generated by the scaling differential amplifier shown out Furthermore, since the proposed MDAC200 with presampling can suppress input common-mode offset, the common-mode feedback circuit can be omitted from the operational amplifier OPAMP.

[0058] Compared to conventional MDACs without presampling, the proposed MDAC200 with presampling selects one of -Vref, 0V, and Vref through presampling capacitor selection. It achieves 2X voltage amplification by sampling the voltage input only at the sampling capacitor, achieving the same kT / C noise performance as using a smaller sampling capacitor. It utilizes an operational amplifier with β=1, exhibits lower finite gain error and lower power consumption, and can use an operational amplifier without a tail current source. It also relaxes the power requirements of the reference buffers used to provide the reference voltages Vrefp, Vcm, and Vrefn. Furthermore, since the voltage output V_OUT is obtained by combining the voltage across the selected presampling capacitor with the voltage across the sampling capacitor, the proposed MDAC200 with presampling does not require background calibration.

[0059] Compared to multi-stage operational amplifiers, single-stage operational amplifiers offer lower power consumption and smaller output swing. When the operational amplifier OPAMP is implemented using a single-stage operational amplifier, the MDAC 200 with presampling benefits from the low power consumption of the operational amplifier OPAMP. As mentioned above, the proposed MDAC 200 with presampling can suppress input common-mode offset, and the operational amplifier OPAMP can be implemented using a differential amplifier without a tail current source. The operational amplifier OPAMP used in the proposed MDAC 200 with presampling can be a single-stage differential amplifier without a tail current source. By eliminating the tail current source that affects the output swing, the single-stage differential amplifier without a tail current source can provide the required output swing of the proposed MDAC 200 with presampling.

[0060] In some embodiments of the invention, a correlated-level-shifting (CLS) auxiliary operational amplifier can be used in an MDAC with presampling to address the output swing problem encountered by a single-stage operational amplifier. It should be noted that the use of a CLS auxiliary operational amplifier with or without tail current is optional in an MDAC with presampling. In fact, any MDAC design using the proposed presampling technique falls within the scope of this invention.

[0061] Figure 11 This is a circuit diagram of an MDAC with presampling and a CLS auxiliary operational amplifier according to an embodiment of the present invention. Figure 1 The MDAC 100 shown can be... Figure 11 The MDAC 1100 implementation is shown. In this embodiment, the operational amplifier (OPAMP) can be implemented as a single-stage differential amplifier with a tail current source or a single-stage differential amplifier without a tail current source. The main difference between the MDAC 200 and 1100 is that the MDAC 1100 also includes multiple CLS capacitors C. CLS C' CLS And multiple switches SW12, SW'12, SW13. CLS capacitor C CLS One plate of the capacitor is coupled to one plate of the sampling capacitor Csam. CLS capacitor C' CLS One plate of the capacitor is coupled to one plate of the sampling capacitor C'sam. Switch SW13 is a reset switch, and one node of switch SW13 is coupled to capacitor CLS. CLS The other plate and the other node are coupled to the CLS capacitor C' CLS The other pole. One node of switch SW12 is coupled to the inverting output node (-) of operational amplifier OPAMP, while the other node is coupled to a node of switch SW13. One node of switch SW'12 is coupled to the non-inverting output node (+) of operational amplifier OPAMP, and the other node is coupled to another node of switch SW13.

[0062] During the sampling period, each of switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, and SW'11 is turned on, and each of switches SW5, SW6, SW7, SW8, SW9, SW12, SW13, SW'5, SW'6, SW'7, SW'8, SW'9, and SW'12 is turned off. During the switching period, each of switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, and SW'11 is turned off, and each of switches SW5, SW'5, SW9, and SW'9 is turned on. Each of switches SW6, SW7, SW8, SW'6, SW'7, and SW'8 is selectively turned on in response to the quantization result of the voltage input (Vip-Vin). Since the MDAC200 and 1100 control the aforementioned switches in the same way during the sampling and conversion periods, they will not be described in detail here for the sake of simplicity.

[0063] Unlike the MDAC 200, which has an amplifier output that directly serves as the MDAC output (i.e., V_OUT), the MDAC 1100 does not use the amplifier output OP_OUT as the MDAC output (i.e., V_OUT). Specifically, the conversion cycle is divided into a first stage Amp1 and a second stage Amp2 following the first stage Amp1. Furthermore, the second stage Amp2 includes the start period during which a reset (RST) operation occurs to quickly reset the amplifier output OP_OUT. Figure 12 This is a schematic diagram illustrating the operation of the DAC gain reduction function performed by the MDAC1100, including the sampling period, the first stage Amp1 of the conversion period, and the second stage Amp2 of the conversion period, wherein the second stage Amp2 includes a reset (RST) operation.

[0064] refer to Figure 11 and combined Figure 13 , Figure 13 This is a schematic diagram showing the voltage level of the amplifier output OP_OUT and the voltage level of the MDAC output (i.e., V_OUT) during the conversion cycle of the MDAC 1100. During the first stage Amp1 of the conversion cycle, each of switches SW9 and SW'9 is turned on, and each of switches SW12, SW'12, and SW13 is turned off. Figure 14 This is an equivalent circuit diagram showing the MDAC 1100 operating during the first stage (Amp1) of the conversion cycle. Since the MDAC output is coupled to the amplifier output via switches SW9 and SW'9, the voltage level at the amplifier output OP_OUT is essentially the same as the voltage level at the MDAC output (V_OUT), as shown below. Figure 13 As shown.

[0065] At the beginning of the second phase Amp2 of the conversion cycle, each of switches SW9 and SW'9 is disconnected, and each of switches SW12, SW'12, and SW13 is turned on. Figure 15 This is an equivalent circuit diagram of the MDAC1100 operating at the beginning of the second phase, Amp2, of the conversion cycle. (See diagram for example.) Figure 13 As shown, the voltage level output by the MDAC (i.e., V_OUT) is controlled by the CLS capacitor C'. CLS and C' CLS The voltage level of the amplifier output OP_OUT is maintained, while the voltage level is reset to the common-mode voltage (e.g., 0V).

[0066] During the remaining period of the second phase Amp2 of the conversion cycle, each of switches SW9, SW'9, and SW13 is disconnected, and each of switches SW12 and SW'12 is turned on. Figure 16 This is an equivalent circuit diagram showing the MDAC1100 operating during the remaining period of the second phase, Amp2, of the conversion cycle. (See diagram for example.) Figure 13 As shown, the operational amplifier OPAMP continuously adjusts the amplifier output OP_OUT, so that the voltage level of the MDAC output (i.e., V_OUT) is further adjusted by the voltage level of the amplifier output OP_OUT through capacitive coupling. From Figure 13 As can be seen, the amplification operation of the operational amplifier OPAMP is divided into two stages, Amp1 and Amp2. After the operational amplifier output OP_OUT is reset, the output swing required for the operational amplifier OPAMP operating in the second stage, Amp2, is reduced. In this way, by using a CLS-assisted single-stage amplifier with a smaller output swing, a larger MDAC output (i.e., V_OUT) can be successfully obtained. Furthermore, with the help of CLS capacitors and two-step amplification, the finite gain error of the operational amplifier OPAMP (i.e., the CLS-assisted single-stage amplifier) ​​can be significantly reduced.

[0067] The proposed pre-sampled MDAC (or the proposed pre-sampled MDAC and CLS auxiliary operational amplifier) ​​can be used by an analog-to-digital converter (ADC), such as a pipelined ADC or a time-interleaved ADC using a pipelined ADC. Figure 17This is a schematic diagram of a pipelined ADC according to an embodiment of the present invention. The pipelined ADC 1700 includes multiple stages 1702_1-1702_N and a combination circuit 1704. Stages 1702_1-1702_N are connected in a pipeline manner and arranged to produce multiple digital outputs D_1-D_N. The combination circuit 1704 is used to combine the digital outputs D_1-D_N to produce a final digital output. Stage 1702_N is a terminal ADC. For example, the terminal ADC can be implemented by a SAR ADC. In this embodiment, each stage in stages 1702_1-1702_(N-1) can employ the proposed MDAC with presampling (or the proposed MDAC with presampling and CLS auxiliary operational amplifier). Taking stage 1702_1 as an example, it includes a quantization circuit (QTZ) 1712, a decision circuit 1714, and an MDAC 1716. Quantization circuit 1712 generates the quantization result of the voltage input of stage 1702_1, where the digital output D_1 of stage 1702_1 depends on the quantization result of the voltage input of stage 1702_1. MDAC 1716 can be implemented by MDAC 200 / 1100. Determination circuit 1714 is configured to select one of the pre-sampling capacitors Cps1, Cps0, Cps-1 that will be connected in series with one sampling capacitor Csam during the conversion cycle, and further select one of the pre-sampling capacitors C'ps1, C'ps0, C'ps-1 that will be connected in series with another sampling capacitor C'sam during the conversion cycle. For example, determination circuit 1714 references the quantization result of the voltage input (e.g., digital output D_1) to determine the voltage input that will be quantized with 2*(V ip -V in ) combination of D out *V ref If (V ip -V in )<-V ref / 4, then D out =+1; if -V ref / 4≦(V ip -V in )≦V ref / 4, then D out =0, if (V ip -V in )>V ref / 4, then D out =-1.

[0068] Regarding the pipelined ADC 1700, a stage of the MDAC implemented by the MDAC 200 / 1100 has a 1.5-bit / stage structure. However, this is for illustrative purposes only and is not intended to limit the invention. With appropriate modifications to the MDAC200 / 1100, a stage of the modified MDAC may have a 2.5-bit / stage structure or a 3.5-bit / stage structure. Figure 18 This is a circuit diagram illustrating another MDAC with presampling according to an embodiment of the present invention. Regarding the pipelined ADC1700, a stage of the MDAC implemented by MDAC 1800 has a 2.5-bit / stage structure. The main difference between MDAC 200 and 1800 is that MDAC 1800 includes four sampling capacitors Csam1, Csam2, C'sam1, C'sam2 and additional switches SW14 and SW'14. Each of switches SW10, SW11, SW14, SW'10, SW'11, SW'14 is turned on during the sampling period and turned off during the conversion period. Since those skilled in the art can readily understand the details and benefits of the presampling technique employed in MDAC 1800 after reading the above paragraphs regarding MDAC 200, further description is omitted here for brevity.

[0069] exist Figure 2 , 11 and Figure 18 In the above embodiment shown, the predefined voltage V pd The bias voltage V of the operational amplifier OPAMP bias Settings. However, these are for illustrative purposes only and are not intended to limit the invention. Alternatively, modifications may be made. Figure 2 , 11 The embodiments shown in 18 use a predefined voltage V with different voltage settings such as common-mode voltage (e.g., 0V). pd . Figure 19 This is a circuit diagram of a pre-sampled MDAC that utilizes common-mode voltage as a predefined voltage according to an embodiment of the present invention. The main difference between MDAC 200 and 1900 is that one node of switch SW1 is arranged to receive the reference voltage V. CM One node of switch SW'1 is arranged to receive the reference voltage V. CM The reference voltage V CM This is the common-mode voltage (e.g., 0V).

[0070] exist Figure 2 , Figure 11 and Figure 18In the above embodiment shown, the arrangement of switches SW1, SW'1, SW5, and SW'5 controls, during the sampling period, that one plate of each of the pre-sampling capacitors Cps1, Cps0, Cps-1, C'ps1, C'ps0, and C'ps-1 is connected to a predefined voltage (e.g., V). pd =V bias And disconnected from the input port of the operational amplifier OPAMP, during the conversion cycle, controlling one plate of each of the presampling capacitors Cps1, Cps0, Cps-1, C'ps1, C'ps0, and C'ps-1 to be connected to a predefined voltage (e.g., V). pd =V bias Disconnect and connect to the input port of the operational amplifier (OPAMP). However, these are for illustrative purposes only and do not imply limitation of the invention. Alternatively, Figure 2 , 11 The embodiment shown in 18 can be modified with different switching arrangements that achieve the same purpose, namely, being arranged to connect one plate of each of the presampling capacitors Cps1, Cps0, Cps-1, C'ps1, C'ps0, and C'ps-1 to a predefined voltage (e.g., V) during the sampling period. pd =V bias or V pd =V cm ) and disconnect from the input port of the operational amplifier OPAMP, and during the conversion cycle, make one plate of the presampling capacitors Cps1, Cps0, Cps-1, C'ps1, C'ps0, and C'ps-1 parallel to a predefined voltage (e.g., V). pd =V bias or V pd =V cm Disconnect and connect to the input port of the operational amplifier (OPAMP).

[0071] Figure 20 This is a circuit diagram of a pre-sampled MDAC using different switch arrangements according to an embodiment of the present invention. The main difference between MDAC 200 and 2000 is that switch SW1 is replaced by switch group SG1, which includes multiple switches; switch SW'1 is replaced by switch group SG'1, which includes multiple switches; switch SW5 is replaced by switch group SG5, which includes multiple switches; and switch SW'5 is replaced by switch group SG'5, which includes multiple switches.

[0072] The switch group SG1 has one switch, another switch, and yet another switch, the first switch being coupled to a predefined voltage V. pd (For example, V) pd =V bias or V pd =V cmThe first node of the switch is coupled to a second node of a plate of a pre-sampling capacitor Cps1. The second switch has a first node coupled to a predefined voltage Vpd (e.g., Vpd = Vbias or Vpd = Vcm) and a second node coupled to a plate of a pre-sampling capacitor Cps0. The third switch has a first node coupled to a predefined voltage Vpd (e.g., Vpd = Vbias or Vpd = Vcm) and a second node coupled to a plate of a pre-sampling capacitor Cps-1.

[0073] The switch group SG'1 has a switch, another switch, and yet another switch. The first switch has a first node coupled to a predefined voltage Vpd (e.g., Vpd = Vbias or Vpd = Vcm) and a second node coupled to a plate of a presampled capacitor C'ps1. The second switch has a first node coupled to a predefined voltage Vpd (e.g., Vpd = Vbias or Vpd = Vcm) and a second node coupled to a plate of a presampled capacitor C'ps0. The yet another switch has a first node coupled to a predefined voltage Vpd (e.g., Vpd = Vbias or Vpd = Vcm) and a second node coupled to a plate of a presampled capacitor C'ps-1.

[0074] The switch group SG5 has one switch, another switch, and yet another switch. The first switch has a first node coupled to the non-inverting input node of the operational amplifier OPAMP and a second node coupled to a plate of the pre-sampling capacitor Cps1. The other switch has a first node coupled to the non-inverting input node of the operational amplifier OPAMP and a second node coupled to a plate of the pre-sampling capacitor Cps0. The yet another switch has a first node coupled to the non-inverting input node of the operational amplifier OPAMP and a second node coupled to a plate of the pre-sampling capacitor Cps-1.

[0075] The switch group SG'5 has one switch, another switch, and yet another switch. The first switch has a first node coupled to the inverting input node of the operational amplifier OPAMP and a second node coupled to a plate of the presampling capacitor C'ps1. The second switch has a first node coupled to the inverting input node of the operational amplifier OPAMP and a second node coupled to a plate of the presampling capacitor C'ps0. The yet another switch has a first node coupled to the inverting input node of the operational amplifier OPAMP and a second node coupled to a plate of the presampling capacitor C'ps-1.

[0076] During the sampling period of the MDAC 2000, all switches in switch groups SG1 and SG'1 are turned on, and all switches in switch groups SG5 and SG'5 are turned off. During the conversion period of the MDAC 2000, all switches in switch groups SG1 and SG'1 are turned off, while all switches in switch groups SG5 and SG'5 are turned on.

[0077] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A multiplying digital-to-analog converter (MDAC) comprising: include: An operational amplifier with input and output ports; Sampling capacitor circuit; Pre-sampling capacitor circuit; as well as A switching circuit is used to control the interconnection between the operational amplifier, the sampling capacitor circuit, and the pre-sampling capacitor circuit; During the sampling period of the MDAC, the switching circuit is configured to connect a predefined voltage to the pre-sampling capacitor circuit, connect multiple reference voltages to the pre-sampling capacitor circuit, disconnect the pre-sampling capacitor from the input port of the operational amplifier, disconnect the pre-sampling capacitor circuit and the sampling capacitor circuit, disconnect the output port of the operational amplifier from the sampling capacitor circuit, and connect the voltage input of the MDAC to the sampling capacitor circuit; and During the conversion cycle of the MDAC, the switching circuit is used to connect the pre-sampling capacitor circuit to the sampling capacitor circuit, wherein the connection configuration between the pre-sampling capacitor circuit and the sampling capacitor circuit depends on the quantization result of the voltage input, further disconnecting the predefined voltage from the pre-sampling capacitor circuit, disconnecting the plurality of reference voltages from the pre-sampling capacitor circuit, connecting the pre-sampling capacitor circuit to the input terminal of the operational amplifier, connecting the output terminal of the operational amplifier to the sampling capacitor circuit, and disconnecting the voltage input from the sampling capacitor circuit; The plurality of reference voltages includes a first reference voltage, a second reference voltage, and a third reference voltage; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor, wherein the first plates of the first, second, and third pre-sampling capacitors are coupled to each other, and the first plates of the fourth, fifth, and sixth pre-sampling capacitors are coupled to each other; and the switching circuit includes: A first switch has a first node coupled to the first reference voltage and a second node coupled to the second plate of the first pre-sampling capacitor, wherein the first switch is turned on during the sampling period and turned off during the conversion period; The second switch has a first node coupled to the second reference voltage and a second node coupled to the second plate of the second pre-sampling capacitor, wherein the second switch is turned on during the sampling period and turned off during the conversion period; A third switch has a first node coupled to the third reference voltage and a second node coupled to the second plate of the third pre-sampling capacitor, wherein the third switch is turned on during the sampling period and turned off during the conversion period; A fourth switch has a first node coupled to the third reference voltage and a second node coupled to the second plate of the fourth pre-sampling capacitor, wherein the fourth switch is turned on during the sampling period and turned off during the switching period; A fifth switch having a first node coupled to the second reference voltage and a second node coupled to the second plate of the fifth pre-sampling capacitor, wherein the fifth switch is turned on during the sampling period and turned off during the switching period; and A sixth switch has a first node coupled to the first reference voltage and a second node coupled to the second plate of the sixth pre-sampling capacitor, wherein the sixth switch is turned on during the sampling period and turned off during the conversion period.

2. The MDAC of claim 1, wherein, The switching circuit also includes: A seventh switch has a first node coupled to the predefined voltage and a second node coupled to a first plate of each of the first, second, and third presampled capacitors, wherein the seventh switch is turned on during the sampling period and turned off during the switching period; and The eighth switch has a first node coupled to the predefined voltage and a second node coupled to a first plate of each of the fourth, fifth, and sixth presampled capacitors, wherein the eighth switch is turned on during the sampling period and turned off during the conversion period.

3. The MDAC of claim 1, wherein, The switching circuit also includes: A first switch group includes a first switch, another switch, and yet another switch; the first switch has a first node coupled to the predefined voltage and a second node coupled to the first plate of the first pre-sampling capacitor; the other switch has a first node coupled to the predefined voltage and a second node coupled to the first plate of the second pre-sampling capacitor; and the yet another switch has a first node coupled to the predefined voltage and a second node coupled to the first plate of the third pre-sampling capacitor; and The second switch group has one switch, another switch, and yet another switch; the first switch has a first node coupled to the predefined voltage and a second node coupled to the first plate of the fourth pre-sampling capacitor; the other switch has a first node coupled to the predefined voltage and a second node coupled to the first plate of the fifth pre-sampling capacitor; and the yet another switch has a first node coupled to the predefined voltage and a second node coupled to the first plate of the sixth pre-sampling capacitor. In this configuration, all switches in the first switch group and the second switch group are turned on during the sampling period and turned off during the conversion period.

4. The MDAC of claim 1, wherein, The operational amplifier's input ports include a non-inverting input node and an inverting input node; the switching circuit further includes: A seventh switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to a first plate of each of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor; wherein the seventh switch is open during the sampling period and closed during the conversion period; The eighth switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to the first plate of each of the fourth, fifth and sixth presampling capacitors, wherein the eighth switch is open during the sampling period and closed during the conversion period.

5. The MDAC of claim 1, wherein, The operational amplifier's input ports include a non-inverting input node and an inverting input node; the switching circuit further includes: A first switch group includes a switch, another switch, and yet another switch; the first switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to the first plate of the first pre-sampling capacitor; the other switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to the first plate of the second pre-sampling capacitor; the yet another switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to the first plate of the third pre-sampling capacitor; and The second switch group has one switch, another switch, and yet another switch; the first switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to the first plate of the fourth pre-sampling capacitor; the other switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to the first plate of the fifth pre-sampling capacitor; and the yet another switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to the first plate of the sixth pre-sampling capacitor. In this configuration, all switches in the first switch group and the second switch group are disconnected during the sampling period and turned on during the conversion period.

6. The MDAC of claim 1, wherein, The sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; The switching circuit also includes: A seventh switch has a first node coupled to a second plate of the first pre-sampling capacitor and a second node coupled to a plate of the first sampling capacitor, wherein the seventh switch is open during the sampling period and is selectively turned on during the conversion period in response to the quantization result of the voltage input; An eighth switch has a first node coupled to a second plate of the second pre-sampling capacitor and a second node coupled to the first plate of the sampling capacitor, wherein the eighth switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period; A ninth switch having a first node coupled to a second plate of the third pre-sampling capacitor and a second node coupled to a plate of the first sampling capacitor, wherein the ninth switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period; A tenth switch has a first node coupled to a second plate of the fourth pre-sampling capacitor and a second node coupled to a plate of the second sampling capacitor, wherein the tenth switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period; The eleventh switch has a first node coupled to the second plate of the fifth pre-sampling capacitor and a second node coupled to the first plate of the second sampling capacitor, wherein the eleventh switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period; A twelfth switch has a first node coupled to a second plate of the sixth pre-sampling capacitor and a second node coupled to one plate of the second sampling capacitor, wherein the twelfth switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period.

7. The MDAC of claim 1, wherein, The operational amplifier's output ports include a non-inverting output node and an inverting output node; The sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; The switching circuit also includes: A seventh switch having a first node coupled to the inverting output node of the operational amplifier and a second node coupled to a plate of the first sampling capacitor, wherein the seventh switch is open during the sampling period and closed during the conversion period; as well as An eighth switch has a first node coupled to the non-inverting output node of the operational amplifier and a second node coupled to a plate of the second sampling capacitor, wherein the eighth switch is open during the sampling period and closed during the conversion period.

8. The MDAC of claim 1, wherein, The voltage input is a differential input that includes both positive and negative signals; The sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor, and the switching circuit further includes: A seventh switch having a first node coupled to the negative signal and a second node coupled to a first plate of the first sampling capacitor, wherein the seventh switch is turned on during the sampling period and turned off during the conversion period; An eighth switch has a first node coupled to the positive signal and a second node coupled to the second plate of the first sampling capacitor, wherein the eighth switch is turned on during the sampling period and turned off during the conversion period; A ninth switch having a first node coupled to the positive signal and a second node coupled to the first plate of the second sampling capacitor, wherein the ninth switch is turned on during the sampling period and turned off during the conversion period; and A tenth switch has a first node coupled to the negative signal and a second node coupled to the second plate of the second sampling capacitor, wherein the tenth switch is turned on during the sampling period and turned off during the conversion period.

9. The MDAC of claim 1, wherein, The operational amplifier is a single-stage differential amplifier without a tail current source.

10. The MDAC of claim 1, wherein, Further includes: First relevant level shifter CLS capacitor; as well as Second CLS capacitor; The operational amplifier's output port includes a non-inverting output node and an inverting output node; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; one plate of the first sampling capacitor is coupled to the first plate of the first CLS capacitor; one plate of the second sampling capacitor is coupled to the first plate of the second CLS capacitor; and the switching circuit further includes: A seventh switch having a first node coupled to one plate of the first sampling capacitor and a second node coupled to the inverting output node of the operational amplifier, wherein the seventh switch is turned on during a first phase of the conversion cycle and turned off during a second phase of the conversion cycle; An eighth switch has a first node coupled to one plate of the second sampling capacitor and a second node coupled to the non-inverting output node of the operational amplifier, wherein the eighth switch is turned on during a first phase of the conversion cycle and turned off during a second phase of the conversion cycle; A ninth switch having a first node coupled to the second plate of the first CLS capacitor and a second node coupled to the second plate of the second CLS capacitor, wherein the ninth switch is turned on at the beginning of the second phase and turned off during the remainder of the second phase of the switching cycle; A tenth switch, having a first node coupled to the inverting output node of the operational amplifier and a second node coupled to the first node of the third switch, wherein the tenth switch is open during a first phase of the conversion cycle and closed during a second phase of the conversion cycle; and The eleventh switch has a first node coupled to the non-inverting output node of the operational amplifier and a second node coupled to the second node of the third switch, wherein the eleventh switch is open during the first phase of the conversion cycle and closed during the second phase of the conversion cycle.

11. The MDAC of claim 10, wherein, During the second phase of the conversion cycle, the voltage difference between one plate of the first sampling capacitor and one plate of the second sampling capacitor serves as the MDAC output.

12. The MDAC of claim 1, wherein, The predefined voltage is the bias voltage of the operational amplifier.

13. The MDAC of claim 1, wherein, The predefined voltage is one of the plurality of reference voltages.

14. A multiplying digital-to-analog converter (MDAC) comprising: include: Operational amplifier; Sampling capacitor circuit; Pre-sampling capacitor circuit; as well as A switching circuit is used to control the interconnection between the operational amplifier, the sampling capacitor circuit, and the pre-sampling capacitor circuit; During the sampling period of the MDAC, the switching circuit is configured to allow the pre-sampling capacitor circuit to sample and hold multiple pre-sampling reference voltages, and to allow the sampling capacitor circuit to sample the voltage input of the MDAC; During the conversion cycle of the MDAC, the switching circuit is used to connect the pre-sampling capacitor circuit to the sampling capacitor circuit, and to allow the operational amplifier to set the voltage output at the output port of the operational amplifier according to the voltage input and one of the plurality of pre-sampling reference voltages. The connection configuration between the pre-sampling capacitor circuit and the sampling capacitor circuit depends on the quantization result of the voltage input, and the voltage output is obtained from a voltage combination based on the voltage input and one of the plurality of pre-sampling reference voltages.

15. The MDAC of claim 14, wherein, The operational amplifier has a feedback factor of 1 and there is no charge flow between the pre-sampling capacitor circuit and the sampling capacitor circuit.

16. The MDAC of claim 14, wherein, There is no voltage change at one plate of the presampled capacitor circuit that receives a reference voltage from the reference buffer.

17. The MDAC of claim 14, wherein, The presampling capacitor circuit includes a first presampling capacitor, a second presampling capacitor, a third presampling capacitor, a fourth presampling capacitor, a fifth presampling capacitor, and a sixth presampling capacitor; The switching circuit includes: A first switch has a first node coupled to a predefined voltage and a second node coupled to a plate of each of the first, second, and third presampled capacitors, wherein the first switch is turned on during the sampling period and turned off during the switching period; and The second switch has a first node coupled to the predefined voltage and a second node coupled to a plate of each of the fourth, fifth and sixth presampled capacitors, wherein the second switch is turned on during the sampling period and turned off during the switching period; Alternatively, the switching circuit includes: A first switch group includes a first switch, another switch, and yet another switch; the first switch has a first node coupled to the predefined voltage and a second node coupled to a plate of the first pre-sampling capacitor; the other switch has a first node coupled to the predefined voltage and a second node coupled to a plate of the second pre-sampling capacitor; and the yet another switch has a first node coupled to the predefined voltage and a second node coupled to a plate of the third pre-sampling capacitor; and The second switch group has one switch, another switch, and yet another switch; the first switch has a first node coupled to the predefined voltage and a second node coupled to a plate of the fourth pre-sampling capacitor; the other switch has a first node coupled to the predefined voltage and a second node coupled to a plate of the fifth pre-sampling capacitor; and the yet another switch has a first node coupled to the predefined voltage and a second node coupled to a plate of the sixth pre-sampling capacitor. In this configuration, all switches in the first switch group and the second switch group are turned on during the sampling period and turned off during the conversion period.

18. The MDAC of claim 14, wherein, The operational amplifier's input ports include a non-inverting input node and an inverting input node; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor; The switching circuit includes: A first switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to a plate of each of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor; wherein the first switch is open during the sampling period and closed during the conversion period; The second switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to a plate of each of the fourth, fifth, and sixth presampling capacitors, wherein the second switch is open during the sampling period and closed during the conversion period; Alternatively, the switching circuit includes: A first switch group includes a switch, another switch, and yet another switch; the first switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to a plate of the first pre-sampling capacitor; the other switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to a plate of the second pre-sampling capacitor; the yet another switch has a first node coupled to the non-inverting input node of the operational amplifier and a second node coupled to a plate of the third pre-sampling capacitor; and The second switch group has one switch, another switch, and yet another switch; the first switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to a plate of the fourth presampling capacitor; the other switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to a plate of the fifth presampling capacitor; and the yet another switch has a first node coupled to the inverting input node of the operational amplifier and a second node coupled to a plate of the sixth presampling capacitor. In this configuration, all switches in the first switch group and the second switch group are disconnected during the sampling period and turned on during the conversion period.

19. The MDAC of claim 14, wherein, The presampling capacitor circuit includes a first presampling capacitor, a second presampling capacitor, a third presampling capacitor, a fourth presampling capacitor, a fifth presampling capacitor, and a sixth presampling capacitor, wherein the first plates of the first presampling capacitor, the second presampling capacitor, and the third presampling capacitor are coupled to each other, and the first plates of the fourth presampling capacitor, the fifth presampling capacitor, and the sixth presampling capacitor are coupled to each other. The switching circuit includes: A first switch has a first node coupled to a first reference voltage and a second node coupled to a second plate of the first pre-sampling capacitor, wherein the first switch is turned on during the sampling period and turned off during the conversion period; The second switch has a first node coupled to a second reference voltage and a second node coupled to a second plate of the second pre-sampling capacitor, wherein the second switch is turned on during the sampling period and turned off during the conversion period; A third switch has a first node coupled to a third reference voltage and a second node coupled to a second plate of the third pre-sampling capacitor, wherein the third switch is turned on during the sampling period and turned off during the switching period; A fourth switch has a first node coupled to the third reference voltage and a second node coupled to the second plate of the fourth pre-sampling capacitor, wherein the fourth switch is turned on during the sampling period and turned off during the conversion period; A fifth switch having a first node coupled to the second reference voltage and a second node coupled to the second plate of the fifth pre-sampling capacitor, wherein the fifth switch is turned on during the sampling period and turned off during the switching period; and A sixth switch has a first node coupled to the first reference voltage and a second node coupled to the second plate of the sixth pre-sampling capacitor, wherein the sixth switch is turned on during the sampling period and turned off during the conversion period.

20. The MDAC of claim 14, wherein, The sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor, wherein the first plates of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor are coupled to each other, and the first plates of the fourth pre-sampling capacitor, the fifth pre-sampling capacitor, and the sixth pre-sampling capacitor are coupled to each other; The switching circuit includes: A first switch has a first node coupled to a second plate of the first pre-sampling capacitor and a second node coupled to a plate of the first sampling capacitor, wherein the first switch is open during the sampling period and is selectively turned on during the conversion period in response to the quantization result of the voltage input; The second switch has a first node coupled to a second plate of the second pre-sampling capacitor and a second node coupled to the first plate of the sampling capacitor, wherein the second switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period. A third switch has a first node coupled to a second plate of the third pre-sampling capacitor and a second node coupled to a plate of the first sampling capacitor, wherein the third switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period. A fourth switch has a first node coupled to a second plate of the fourth pre-sampling capacitor and a second node coupled to a plate of the second sampling capacitor, wherein the fourth switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period; A fifth switch has a first node coupled to a second plate of the fifth pre-sampling capacitor and a second node coupled to a first plate of the second sampling capacitor, wherein the fifth switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period; A sixth switch having a first node coupled to a second plate of the sixth pre-sampling capacitor and a second node coupled to one plate of the second sampling capacitor, wherein the sixth switch is open during the sampling period and is selectively turned on in response to the quantization result of the voltage input during the conversion period.

21. The MDAC according to claim 14, characterized in that, The operational amplifier's output ports include a non-inverting output node and an inverting output node; The sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; The switching circuit includes: A first switch having a first node coupled to the inverting output node of the operational amplifier and a second node coupled to a plate of the first sampling capacitor, wherein the first switch is open during the sampling period and closed during the conversion period; as well as The second switch has a first node coupled to the non-inverting output node of the operational amplifier and a second node coupled to a plate of the second sampling capacitor, wherein the second switch is open during the sampling period and closed during the conversion period.

22. The MDAC according to claim 14, characterized in that, The voltage input is a differential input that includes both positive and negative signals; The sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor, and the switching circuit includes: A first switch has a first node coupled to the negative signal and a second node coupled to a first plate of the first sampling capacitor, wherein the first switch is turned on during the sampling period and turned off during the conversion period; The second switch has a first node coupled to the positive signal and a second node coupled to the second plate of the first sampling capacitor, wherein the second switch is turned on during the sampling period and turned off during the conversion period; A third switch has a first node coupled to the positive signal and a second node coupled to the first plate of the second sampling capacitor, wherein the third switch is turned on during the sampling period and turned off during the switching period; and A fourth switch has a first node coupled to the negative signal and a second node coupled to the second plate of the second sampling capacitor, wherein the fourth switch is turned on during the sampling period and turned off during the conversion period.

23. The MDAC of claim 14, wherein, Further includes: First relevant level shifter CLS capacitor; as well as Second CLS capacitor; The operational amplifier's output port includes a non-inverting output node and an inverting output node; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; one plate of the first sampling capacitor is coupled to the first plate of the first CLS capacitor; one plate of the second sampling capacitor is coupled to the first plate of the second CLS capacitor; and the switching circuit includes: A first switch has a first node coupled to one plate of the first sampling capacitor and a second node coupled to the inverting output node of the operational amplifier, wherein the first switch is turned on during a first phase of the conversion cycle and turned off during a second phase of the conversion cycle. The second switch has a first node coupled to one plate of the second sampling capacitor and a second node coupled to the non-inverting output node of the operational amplifier, wherein the second switch is turned on during a first phase of the conversion cycle and turned off during a second phase of the conversion cycle; A third switch has a first node coupled to the second plate of the first CLS capacitor and a second node coupled to the second plate of the second CLS capacitor, wherein the third switch is turned on at the beginning of the second phase and turned off during the remainder of the second phase of the switching cycle. A fourth switch having a first node coupled to the inverting output node of the operational amplifier and a second node coupled to the first node of the third switch, wherein the fourth switch is open during a first phase of the conversion cycle and closed during a second phase of the conversion cycle; and A fifth switch having a first node coupled to the non-inverting output node of the operational amplifier and a second node coupled to the second node of the third switch, wherein the fifth switch is open during a first phase of the conversion cycle and closed during a second phase of the conversion cycle.

24. The MDAC of claim 23, wherein, During the second phase of the conversion cycle, the voltage difference between one plate of the first sampling capacitor and one plate of the second sampling capacitor serves as the MDAC output.

25. A pipelined analog-to-digital converter (ADC) comprising: include: Multiple stages are connected in a pipeline manner and arranged to produce multiple digital outputs respectively; as well as a combination circuit for combining the plurality of digital outputs; wherein at least one of the plurality of stages comprises a quantization circuit and a multiplying digital-to-analog converter (MDAC) according to any one of claims 1 to 13 or a MDAC according to any one of claims 14 to 24; wherein the quantization circuit is configured to generate a quantization result of a voltage input of at least one of the plurality of stages, wherein the digital output of at least one of the plurality of stages depends on the quantization result of the voltage input.

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