Data Conversion Device and High-Definition Multimedia Interface Receiver Device

Abstract

A data conversion device and a high-definition multimedia interface receiving device. The data conversion device includes a storage circuit and a frequency adjustment circuit. The storage circuit is used to store pixel data in the high-definition multimedia interface signal according to a first clock and output image data according to a second clock. The frequency adjustment circuit is used to adjust the second clock according to a control signal in the high-definition multimedia interface signal and the second clock, and transmit the adjusted second clock to the storage circuit.

Description

Technical Field

[0001] The present invention relates to a data conversion device, and particularly to a data conversion device for converting a high-definition multimedia interface (HDMI) signal operating in a fixed clock domain to a pixel clock domain. Background Art

[0002] According to the definition of the high-definition multimedia interface (HDMI) standard, after the HDMI signal sent by the HDMI transmitting device is received by the HDMI receiving device, it will be converted from the transmission clock domain of the HDMI transmitting device to the reception clock domain of the HDMI receiving device and then sent to the playback device. In order to prevent the HDMI receiving device from receiving too much data and causing an overflow situation, or outputting too fast and causing an underflow situation, how to adjust the reception clock of the HDMI receiving device has become one of the problems that the field is eager to solve. Summary of the Invention

[0003] The present invention discloses a data conversion device, which includes a storage circuit and a frequency adjustment circuit. The storage circuit is used to store pixel data in a high-definition multimedia interface (HDMI) signal according to a first clock, and output image data according to a second clock. The frequency adjustment circuit is used to adjust the second clock according to a control signal in the HDMI signal and the second clock, and transmit the adjusted second clock to the storage circuit.

[0004] The present invention also discloses an HDMI receiving device, which includes a decoding device and a data conversion device. The decoding device is used to receive an HDMI signal to generate a first control signal and pixel data operating in a clock domain of a first clock. The data conversion device is used to receive the first clock, the first control signal, and the pixel data, and generate a second control signal and image data operating in a clock domain of a second clock, wherein the data conversion device adjusts the second clock according to the first control signal and the second clock.

[0005] Compared with the prior art, the data conversion and HDMI receiving devices of the present application can adjust the pixel clock in real time, and efficiently output image data according to the pixel clock, so as to avoid the situation of overflow or underflow in the output and reception of the HDMI receiving device. Brief Description of the Drawings

[0006] Figure 1 It is a schematic diagram of a high-definition multimedia interface (HDMI) receiving device in some embodiments of the present invention.

[0007] Figure 2 In some embodiments of the present invention, it is a schematic diagram of a data conversion device in an HDMI receiving device.

[0008] Symbol Explanation

[0009] 10: HDMI receiving device

[0010] PHY: Physical layer device

[0011] 100: Decoding device

[0012] S1: HDMI signal

[0013] S2: Video signal

[0014] 200: Data conversion device

[0015] 220: Storage circuit

[0016] 240: Frequency adjustment circuit

[0017] 245: Data calculator

[0018] 246: Write index unit

[0019] 247: Read index unit

[0020] 248: Error generator

[0021] 250: Frequency setter

[0022] 255: Phase-locked loop

[0023] 260: Format generation circuit

[0024] CLK1: FRL clock

[0025] CLK2: Pixel clock

[0026] D1: Pixel data

[0027] D2: Video data

[0028] C1: Control signal

[0029] C2: Control signal

[0030] V1: Data valid signal

[0031] WV: Write value

[0032] RV: Read value

[0033] WL: Water level value

[0034] N: Clock control signal

[0035] RCLK: Reference Clock

[0036] HSYNC1: Horizontal Sync Signal

[0037] VSYNC1: Vertical Sync Signal

[0038] RC: Data Compression Ratio Signal

[0039] HSYNC2: Horizontal Sync Signal

[0040] VSYNC2: Vertical Sync Signal

[0041] DE: Enable Signal Detailed Implementation Manner

[0042] Figure 1 It is a schematic diagram of the HDMI receiving device 10. The HDMI receiving device 10 is used to receive the HDMI signal S1 transmitted from an HDMI transmitting device (not shown) and convert the HDMI signal S1 into an image signal S2 for output. The HDMI signal S1 includes a fixed rate link (FRL) clock CLK1, pixel data D1, and a control signal C1, and the image signal S2 includes a pixel clock CLK2, image data D2, and a control signal C2. In some embodiments, the pixel data D1 and the image data D2 are RGB data.

[0043] The HDMI receiving device 10 includes a physical layer device PHY, a decoding device 100, and a data conversion device 200. The physical layer device PHY is used to receive the HDMI signal S1 and obtain the FRL clock CLK1 through a clock recovery circuit in the physical layer device PHY. The physical layer device PHY transmits the FRL clock CLK1 and the HDMI signal S1 to the decoding device 100. The decoding device 100 decodes the HDMI signal S1 into a control signal C1, a data valid signal V1, and pixel data D1.

[0044] The data conversion device 200 receives the FRL clock CLK1, the control signal C1, the data valid signal V1, and the pixel data D1, and outputs a pixel clock CLK2, image data D2, and a control signal C2. Among them, the image data D2 and the control signal C2 belong to the clock domain of the pixel clock CLK2. The data conversion device 200 is used to store the pixel data D1 according to the FRL clock CLK1 and output the image data D2 according to the pixel clock CLK2. The data conversion device 200 is used to adjust the pixel clock CLK2 so that the image data D2 and the control signal C2 can be output according to different pixel clocks CLK2 at different times.

[0045] In some embodiments, the data conversion device 200 has a first in first out (FIFO) register for storing the received pixel data D1 and outputting the pixel data D1 in the FIFO register in sequence as image data D2 according to the pixel clock CLK2.

[0046] However, the storage space of the FIFO register is ultimately limited. In some prior arts, the HDMI receiving device cannot efficiently adjust the pixel clock, such that when the rate at which the HDMI receiving device outputs image data is lower than the rate at which it stores pixel data, the FIFO register overflows because there is more pixel data stored than image data output. Or when the rate at which the HDMI receiving device outputs image data is higher than the rate at which it stores pixel data, the FIFO register underflows because there is more image data output than pixel data stored.

[0047] Compared with the prior art, the data conversion device 200 and the HDMI receiving device 10 provided by the present invention have the function of being able to more effectively adjust the pixel clock CLK2 to avoid the above-mentioned overflow or underflow situations. The details are described as follows.

[0048] Refer to Figure 2 。 Figure 2 FIG. is a schematic diagram of a data conversion device 200 according to some embodiments of the present invention. The data conversion device 200 includes a storage circuit 220, a frequency adjustment circuit 240, and a format generation circuit 260.

[0049] In some embodiments, the storage circuit 220 includes a FIFO register. The storage circuit 220 stores the pixel data D1 according to the FRL clock CLK1, the data compression ratio signal RC and the data valid signal V1 in the control signal C1. In some embodiments, when the data valid signal V1 corresponds to the first bit time, it means that the storage circuit 220 receives valid pixel data D1, and at this time the storage circuit 220 stores the received pixel data D1. In contrast, when the data valid signal V1 corresponds to the second bit time (different from the first bit time), it means that the storage circuit 220 receives invalid pixel data D1, such as a gap character, and at this time the storage circuit 220 does not perform a storage operation.

[0050] The storage circuit 220 outputs image data D2 according to the pixel clock CLK2. In other words, the output image data D2 belongs to the clock domain of the pixel clock CLK2. The frequency adjustment circuit 240 is used to generate the pixel clock CLK2 and adjust the pixel clock CLK2 in real time. Specifically, the frequency adjustment circuit 240 adjusts the pixel clock CLK2 according to the accumulated quantity of the pixel data D1 stored in the storage circuit 220 and the accumulated quantity of the output image data D2. The format generation circuit 260 generates a control signal C2 according to the pixel clock CLK2 and the control signal C1, and transmits the control signal C2 to the storage circuit 220, so that the storage circuit 220 outputs the image data D2 according to the control signal C2 (and generated according to the pixel clock CLK2).

[0051] In some embodiments, the frequency adjustment circuit 240 includes a data calculator 245, a frequency setter 250, and a phase-locked loop 255. The data calculator 245 generates a water level value WL according to the control signal C1, the data valid signal V1, the FRL clock CLK1, and the pixel clock CLK2, where the water level value WL represents the difference between the accumulated quantity of the pixel data D1 stored in the storage circuit 220 and the accumulated quantity of the output image data D2. The frequency setter 250 generates a clock control signal N according to the water level value WL. The phase-locked loop 255 generates the pixel clock CLK2 according to the clock control signal N and the reference clock RCLK. For example, the clock control signal N is the division ratio of the phase-locked loop 255.

[0052] In some embodiments, the data calculator 245 includes a write index unit 246, a read index unit 247, and an error generator 248. In some embodiments, the write index unit 246 and the read index unit 247 are index registers, which are used to indicate the addresses in the storage circuit 220. For example, the write index unit 246 and the read index unit 247 can be implemented by a program counter, which can also be called an address register. The write index unit 246 is used to indicate a write value WV according to the control signal C1, the data valid signal V1, and the FRL clock CLK1, where the write value WV represents the address where the latest stored pixel data D1 is stored in the storage circuit 220, and the read index unit 247 is used to indicate a read value RV according to the pixel clock CLK2, where the read value RV represents the address where the latest output image data D2 was originally stored in the storage circuit 220. The error generator 248 generates the water level value WL according to the write value WV and the read value RV. The above write index unit 246 and read index unit 247 are only for illustrative purposes, and various different write index units 246 and read index units 247 are within the consideration and scope of the present invention. For example, the write index unit 246 and the read index unit 247 can be implemented by an accumulator.

[0053] In some embodiments, the storage circuit 220 stores the pixel data D1 according to the data compression ratio signal RC, the data valid signal V1, and the FRL clock CLK1 in the control signal C1, while the write index unit 246 determines the number of restored pixel data D1 received by the storage circuit 220 according to the data compression ratio signal RC, the data valid signal V1, and the FRL clock CLK1. For example, in one cycle of the FRL clock CLK1, the data volume may be 3 Bytes (bytes) in size. When the data compression ratio signal RC indicates that the FRL clock signal CLK1 cycle being received contains 6 times the data volume, and the data valid signal V1 indicates that the 3 Bytes of data received in this cycle is valid, it means that after the pixel data D1 is restored (decompressed) in this cycle, it contains 6 times the data volume of 3 Bytes. Therefore, the storage circuit 220 needs to store a data volume of 18 Bytes (6 * 3 Bytes * 1), so that the write index unit 246 will indicate that the address currently used in the storage circuit 220 is pushed forward by 18 Bytes, where the data valid signal V1 corresponding to 1 represents that the data received in this cycle is valid. This address is the write value WV. For example, when the data valid signal V1 corresponds to 0, it means that the data received in this cycle is invalid.

[0054] In contrast, since all the data stored in the storage circuit 220 is valid, the read index unit 247 only needs to determine how much image data D2 is output by the storage circuit 220 according to the pixel clock CLK2, and indicate the address of the currently latest output image data D2 in the storage circuit 220. This address is the read value RV.

[0055] Since the storage circuit 220 stores the pixel data D1 sequentially (it may include a FIFO register as described above), the difference between the cumulative quantity of the stored pixel data D1 and the cumulative quantity of the output image data D2 can be obtained from the difference in the addresses of the storage circuit 220. Specifically, the error generator 248 reads the write value WV and the read value RV, and subtracts the read value RV from the write value WV as the water level value WL. Since the write value WV is updated in real time with the pixel data D1, the data compression ratio signal RC, the data valid signal V1, and the FRL clock CLK1, and the read value RV is updated in real time with the pixel clock CLK2, the water level value WL can accurately simulate the data volume stored but not output in the storage circuit 220.

[0056] When the water level value WL is greater than the preset upper limit value, the frequency setter 250 generates a clock control signal N, causing the phase-locked loop 255 to increase the frequency of the pixel clock CLK2 according to the clock control signal N. For example, by increasing the clock control signal N, the output speed of the storage circuit 220 is thereby increased. When the water level value WL is less than the preset lower limit value, the frequency setter 250 generates a clock control signal N, causing the phase-locked loop 255 to decrease the frequency of the pixel clock CLK2 according to the clock control signal N. For example, by decreasing the clock control signal N, the output speed of the storage circuit 220 is thereby decreased. In other words, the frequency adjustment circuit 240 is used to adjust the pixel clock CLK2 according to the difference between the accumulated quantity of the stored pixel data D1 and the accumulated quantity of the output image data D2, so that the pixel data D1 in the storage circuit 220 that has not been output as the image data D2 occupies the storage space in the storage circuit 220 between the preset upper limit value and the preset lower limit value. In some embodiments, the preset upper limit value corresponds to the water level of approximately 70% of the storage space in the storage circuit 220 (i.e., there is an allowable value of approximately 30% from the occurrence of the overflow situation). In some embodiments, the preset lower limit value corresponds to the water level of approximately 30% of the storage space in the storage circuit 220 (i.e., there is an allowable value of approximately 30% from the occurrence of the underflow situation).

[0057] In some embodiments, the control signal C1 further includes a horizontal synchronization signal HSYNC1 and a vertical synchronization signal VSYNC1. The horizontal synchronization signal HSYNC1 is used to indicate the start point of each scan line in a frame under the clock domain of the FRL clock CLK1, and the vertical synchronization signal VSYNC1 is used to indicate the first scan line of each frame under the clock domain of the FRL clock CLK1. The control signal C2 includes an enable signal DE, a horizontal synchronization signal HSYNC2, and a vertical synchronization signal VSYNC2, where the horizontal synchronization signal HSYNC2 and the vertical synchronization signal VSYNC2 respectively indicate the start point of each scan line in a frame and the first scan line of each frame under the clock domain of the pixel clock CLK2. The format generation circuit 260 converts the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1 from the clock domain of the FRL clock signal CLK1 to the clock domain of the pixel clock signal CLK2 for output as the horizontal synchronization signal HSYNC2 and the vertical synchronization signal VSYNC2. Specifically, the format generation circuit 260 can obtain the data volume of a frame based on the number of periods of the FRL clock CLK1 between each horizontal synchronization signal HSYNC1 and the number of vertical synchronization signals VSYNC1, and then convert the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1 operating in the clock domain of the FRL clock CLK1 into the horizontal synchronization signal HSYNC2 and the vertical synchronization signal VSYNC2 operating in the clock domain of the pixel clock CLK2 for output, and generate the enable signal DE to the storage circuit 220 according to the pixel clock CLK2, the horizontal synchronization signal HSYNC2, and the vertical synchronization signal VSYNC2. In some embodiments, the format generation circuit 260 includes a counter for calculating the number of times the generated horizontal synchronization signal HSYNC2 and vertical synchronization signal VSYNC2 are generated. When the vertical synchronization signal VSYNC2 indicates the start of scanning of the first scan line in a frame, the enable signal DE is generated at the start of each scan line indicated by the horizontal synchronization signal HSYNC2. In other words, the data of each scan line stored in the storage circuit 220 corresponds to an enable signal DE. Therefore, after receiving the enable signal DE, the storage circuit 220 can output the image data D2 of the corresponding scan line according to the pixel clock CLK2.

Claims

1. A data conversion device, comprising: A storage circuit for storing a pixel data in a high-definition multimedia interface signal according to a first clock, and outputting an image data according to a second clock; and A frequency adjustment circuit for adjusting the second clock according to a control signal in the high-definition multimedia interface signal and the second clock, and transmitting the adjusted second clock to the storage circuit, wherein the frequency adjustment circuit comprises: A data calculator for outputting a water level value according to the first clock, the control signal and the second clock; and A phase-locked loop for outputting the second clock according to the water level value, wherein the water level value represents a difference between an accumulated quantity of the pixel data stored in the storage circuit and an accumulated quantity of the image data output.

2. The data conversion device according to claim 1, wherein the frequency adjustment circuit further comprises: A frequency setter for generating a clock control signal to the phase-locked loop according to the water level value, wherein the phase-locked loop outputs the second clock according to the clock control signal and a reference clock.

3. The data conversion device according to claim 1, further comprising: A format generation circuit for generating an enable signal to the storage circuit according to the second clock and the control signal, wherein the storage circuit further outputs the image data according to the enable signal and the second clock.

4. A high-definition multimedia interface receiving device, comprising: A decoding device for receiving a high-definition multimedia interface signal to generate a first control signal and a pixel data operating in a clock domain of a first clock; and A data conversion device for receiving the first clock, the first control signal and the pixel data, and generating a second control signal and an image data operating in a clock domain of a second clock, wherein the data conversion device adjusts the second clock according to the first control signal and the second clock, wherein the data conversion device comprises: A frequency adjustment circuit for adjusting the second clock according to a data compression ratio signal in the first control signal and the second clock; and A storage circuit for storing the pixel data, and for outputting the image data according to the second clock, wherein the frequency adjustment circuit comprises: A data calculator for generating a water level value according to the data compression ratio signal and the second clock; A frequency setter for generating a clock control signal according to the water level value; and A phase-locked loop for adjusting the second clock according to the clock control signal and a reference clock, wherein the water level value represents a difference between an accumulated quantity of the pixel data stored in the storage circuit and an accumulated quantity of the image data output.

5. The high-definition multimedia interface receiving device according to claim 4, wherein the data conversion device further comprises: A format generation circuit for converting the first control signal into the second control signal according to the second clock.

6. The high-definition multimedia interface receiving device according to claim 4, wherein the data calculator comprises: A write index unit for indicating a write value according to the data compression ratio signal; A read index unit for indicating a read value according to the second clock signal; and An error generator for generating the water level value, where the water level value is equal to the write value minus the read value.

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