Prediction of wafer flatness

Abstract

Aspects of the present disclosure provide methods for determining wafer flatness and for manufacturing semiconductor devices. The method includes: storing a first wafer expansion of a first wafer collected during a lithography process along a first direction parallel to a working surface of the first wafer. The lithography process is used to pattern a structure on the working surface of the first wafer. Prior to a manufacturing step with a wafer flatness requirement, a wafer flatness of the first wafer is determined using a flatness prediction model configured to predict wafer flatness and based on the first wafer expansion collected during the lithography process. In an example, a layer having a thickness based on the determined wafer flatness of the first wafer is deposited on a back side of the first wafer.

Description

Technical Field

[0001] Embodiments described herein relate generally to semiconductor memory devices and the fabrication of semiconductor memory devices. Background Art

[0002] A semiconductor device may be formed by various manufacturing steps performed on a wafer. The manufacturing steps may affect the flatness (e.g., bow) of the wafer. Certain manufacturing steps, such as wafer-level bonding of a first wafer and a second wafer, may have a flatness requirement for the flatness of the wafers. However, the first wafer and / or the second wafer may have a relatively large bow, making wafer-level bonding challenging. The bow of the wafer needs to be measured and then reduced to meet the flatness requirement. Summary of the invention

[0003] Various aspects of the present disclosure provide a method for determining wafer flatness. The method may include storing a first wafer expansion of a first wafer collected along a first direction parallel to a working surface of the first wafer during a lithography process for patterning a structure on the working surface of the first wafer. Prior to a manufacturing step with a wafer flatness requirement, a flatness prediction model configured to predict wafer flatness may be used to determine wafer flatness of the first wafer based on the first wafer expansion collected during the lithography process.

[0004] In an embodiment, the method includes depositing a layer on the back side of the first wafer having a thickness based on the determined wafer flatness of the first wafer.

[0005] In an embodiment, the method further comprises measuring a second wafer expansion along a second direction parallel to the working surface of the first wafer, wherein the first direction may be perpendicular to the second direction. The method further comprises determining wafer flatness of the first wafer based on the first wafer expansion and the second wafer expansion using a flatness prediction model.

[0006] In an embodiment, the method further comprises, after the lithography process and before the determining step, modifying the first wafer by forming a structure on a working surface of the first wafer using a plurality of manufacturing steps. Wafer flatness of the first wafer may be determined using a flatness prediction model and based on first wafer expansion and a waiting time between two manufacturing steps of the plurality of manufacturing steps.

[0007] In an embodiment, wafer flatness is indicated by a bow of the first wafer, the flatness prediction model is a bow prediction model that predicts the bow of the first wafer, and the method includes determining the bow of the first wafer based on the first wafer expansion using the bow prediction model.

[0008] In an embodiment, the flatness prediction model is based on a machine learning algorithm, and the method further comprises measuring a wafer expansion of the second wafer along a direction parallel to the working surface of the second wafer during a lithography process for patterning a structure on the working surface of the second wafer. Before performing a manufacturing step with a wafer flatness requirement on the second wafer, the wafer flatness of the second wafer may be determined using the flatness prediction model and based on the wafer expansion of the second wafer. The method comprises measuring an actual wafer flatness of the second wafer, and updating the flatness prediction model based on the measured wafer flatness of the second wafer and the determined wafer flatness of the second wafer.

[0009] In an embodiment, the lithography process is a lithography process that is performed closest in time to a manufacturing step having a wafer flatness requirement.

[0010] In an embodiment, a wafer flatness of a first wafer is determined using a flatness prediction model and based on a process temperature or a process time of one of a plurality of manufacturing steps. The flatness prediction model may depend on first wafer expansion, a waiting time, and one of a process temperature and a process time of one of a plurality of manufacturing steps.

[0011] In an example, a manufacturing step with wafer planarity requirements is performed after forming the contact structures and the wordline contacts.

[0012] In an example, the structure includes a contact structure and a word line contact, and a photolithography process patterns the contact structure and the word line contact.

[0013] Aspects of the present disclosure provide a method for a semiconductor device. The method may include obtaining a first wafer expansion of a first wafer, the first wafer expansion being collected along a first direction parallel to a working surface of the first wafer during a lithography process for patterning a structure of a semiconductor device on a working surface of the first wafer. Prior to a bonding step with a wafer flatness requirement, a wafer flatness of the first wafer may be determined based on the first wafer expansion using a flatness prediction model configured to predict wafer flatness. The method also includes depositing a layer having a thickness determined based on the determined wafer flatness of the first wafer on a back side of the first wafer, and bonding the first wafer face-to-face with a second wafer.

[0014] In an embodiment, after depositing the layer, a wafer flatness of the first wafer meets a wafer flatness requirement.

[0015] In an embodiment, the method further comprises measuring a second wafer expansion along a second direction parallel to the working surface of the first wafer. The first direction may be perpendicular to the second direction. The wafer flatness of the first wafer may be determined using a flatness prediction model and based on the first wafer expansion and the second wafer expansion.

[0016] In an embodiment, the method further comprises, after the lithography process and before the determining step, modifying the first wafer by forming a structure on a working surface of the first wafer using a plurality of manufacturing steps. Wafer flatness of the first wafer may be determined using a flatness prediction model configured to predict wafer flatness and based on first wafer expansion and a wait time between two manufacturing steps of the plurality of manufacturing steps.

[0017] In an embodiment, the wafer flatness is indicated by a bow of the first wafer and the flatness prediction model is a bow prediction model. The bow of the first wafer may be determined based on the first wafer expansion using a bow prediction model that predicts the bow of the first wafer.

[0018] In an embodiment, the flatness prediction model is based on a machine learning algorithm. The method also includes measuring a wafer expansion of the third wafer along a direction parallel to the working surface of the third wafer during a lithography process for patterning a structure on the working surface of the third wafer. Before performing a bonding step with a wafer flatness requirement on the third wafer, the flatness prediction model can be used to determine the wafer flatness of the third wafer. The method includes measuring the actual wafer flatness of the third wafer, and updating the flatness prediction model based on the measured wafer flatness of the third wafer and the determined wafer flatness of the third wafer.

[0019] In an embodiment, the method includes depositing a layer on the back side of the third wafer having a thickness based on the determined wafer flatness of the third wafer.

[0020] In an example, the method includes determining wafer flatness of a first wafer using a flatness prediction model and based on a process temperature or a process time of one of a plurality of manufacturing steps. The flatness prediction model may depend on first wafer expansion, a waiting time, and one of a process temperature and a process time of one of a plurality of manufacturing steps.

[0021] In an example, the semiconductor device is a semiconductor memory device including a 3D NAND array, the first wafer includes a plurality of 3D NAND arrays, and the second wafer includes a peripheral circuit for controlling the 3D NAND arrays.

[0022] In an example, a bonding step with wafer flatness requirements is performed after forming the contact structures and the wordline contacts.

[0023] In an example, the structure includes a contact structure and a word line contact, and a photolithography process patterns the contact structure and the word line contact.

[0024] In an example, the structure of the semiconductor device includes a channel structure of a 3D NAND array. Based on the first wafer expansion, a wafer flatness of the first wafer can be determined using a flatness prediction model before fabricating wordline contacts of the semiconductor device and after forming the channel structure of the 3D NAND array.

[0025] In an example, the lithography process is a lithography process that is performed closest in time to a manufacturing step having a wafer flatness requirement.

[0026] Aspects of the present disclosure provide a computing device. The computing device may include a processing circuit configured to store wafer expansion of a wafer collected along a first direction parallel to a working surface of the wafer during a lithography process for patterning a structure on the working surface of the wafer. Prior to a manufacturing step with a wafer flatness requirement, the processing circuit may determine wafer flatness of the wafer based on the wafer expansion collected during the lithography process using a flatness prediction model configured to predict wafer flatness.

[0027] Aspects of the present disclosure provide a non-transitory computer-readable storage medium storing a program, the program executable by one or more processors to perform: storing wafer expansion of a wafer collected along a first direction parallel to a working surface of the wafer during a photolithography process for forming a structure on the working surface of the wafer. Prior to a manufacturing step with a wafer flatness requirement, the program executable by the one or more processors may: determine wafer flatness of the wafer based on the wafer expansion collected during the photolithography process using a flatness prediction model configured to predict wafer flatness. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0029] Figure 1A-1B Examples of different types of stresses in accordance with aspects of the present disclosure are shown.

[0030] Figure 2 The variation in wafer flatness across a wafer according to an embodiment of the present disclosure is shown.

[0031] Figure 3 The relationship between the bow of a wafer and the radius of curvature of the wafer according to an embodiment of the present disclosure is shown.

[0032] Figures 4A-4C The relationship between wafer bow and wafer expansion according to an embodiment of the present disclosure is shown.

[0033] Figure 5 A cross-sectional view of a semiconductor device during a manufacturing process is shown in accordance with some embodiments.

[0034] Figure 6 A flowchart outlining a process for forming a semiconductor device according to some embodiments of the present disclosure is shown.

[0035] Figure 7 A flow chart outlining a process for determining wafer flatness according to some embodiments of the present disclosure is shown.

[0036] Figure 8-13 A cross-sectional view of a semiconductor device during a manufacturing process is shown in accordance with some embodiments.

[0037] Figures 14A-14D An exemplary relationship between wafer expansion of a wafer measured at a first time and a corresponding wafer flatness of the wafer measured at a second time is shown in accordance with an embodiment of the present disclosure.

[0038] Figures 15A-15B An exemplary relationship between wafer expansion of a wafer measured at a first time and wafer flatness of the wafer measured at a second time based on a queue time according to an embodiment of the present disclosure is shown.

[0039] Fig. 15C The relationship between wafer flatness and queue time according to an embodiment of the present disclosure is shown.

[0040] Fig.15D An exemplary relationship between wafer expansion of a wafer measured at a first time and wafer flatness of the wafer measured at a second time based on a queue time according to an embodiment of the present disclosure is shown.

[0041] Fig.16 An exemplary comparison of actual measured bends and predicted bends according to an embodiment of the present disclosure is shown.

[0042] Fig.17 An exemplary linear relationship of actual measured bending to predicted bending according to an embodiment of the present disclosure is shown.

[0043] Fig.18 A computer system (1800) suitable for implementing certain embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0044] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first and second features are directly contacted and formed, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0045] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0046] Semiconductor circuit components may be formed on a wafer during a manufacturing process. The manufacturing process may include various manufacturing steps (or stages). Various aspects of the present disclosure provide techniques for determining wafer flatness of a wafer using a flatness prediction model. At least one wafer expansion of a wafer may be stored. For example, during a photolithography process for patterning a structure on a working surface of a wafer during a manufacturing process, at least one wafer expansion may be collected. Before performing a manufacturing step with a wafer flatness requirement, the wafer flatness of the wafer may be determined using a flatness prediction model and based on at least one wafer expansion, the flatness prediction model predicting wafer flatness based at least on the wafer expansion. Since the technique for determining wafer flatness does not require the use of a flatness measurement station to perform actual flatness measurement of the wafer, the manufacturing process is not interrupted and productivity may be improved. For example, one or more measurement results collected for a photolithography process may also be reused to determine wafer flatness. In other embodiments, measurement results may be collected outside of a photolithography process.

[0047] For example, as manufacturing steps are performed on the wafer, the flatness of the wafer may change. In an example, based on at least one expansion at an earlier stage of the manufacturing process, such as when a lithography process is performed, a flatness prediction model can be used to determine the flatness of the wafer at a later stage of the manufacturing process. Since multiple manufacturing steps can be performed on the wafer between the earlier stage and the later stage, additional parameters can be included in the flatness prediction model for more accurate prediction. For example, the flatness prediction model also determines the flatness of the wafer based on the waiting time that the wafer waits to be processed between two manufacturing steps in the multiple manufacturing steps. In an example, the flatness prediction model also determines the flatness of the wafer based on the process parameters (e.g., process temperature, process time) of one of the multiple manufacturing steps.

[0048] In an example, the flatness prediction model is a bend prediction model that predicts the bend of the wafer based on at least one wafer expansion. The flatness prediction model can be based on a machine learning algorithm and can be updated based on the actual measured wafer flatness of the wafer and the predicted wafer flatness. Since the wafer flatness of most wafers does not need to be measured, the number of flatness measurement stations is significantly reduced, making the technology cost-effective.

[0049] A layer having a thickness based on a predicted wafer flatness of the wafer may be deposited on the back side of the wafer. Subsequently, the wafer may be bonded face-to-face with another wafer. In an example, the wafer includes a plurality of memory cell arrays, and the other wafer includes peripheral circuitry for controlling the memory cell arrays. The wafer may be manufactured to optimize the density and performance of the memory cell arrays without affecting manufacturing constraints due to the peripheral circuitry; and the other wafer may be manufactured to optimize the performance of the peripheral circuitry without affecting manufacturing constraints due to the memory cell arrays.

[0050] Wafer flatness (or flatness) of a wafer (e.g., a semiconductor wafer) may indicate whether the wafer is flat. Wafer flatness may affect device manufacturing processes, including, for example, etching, bonding, lithography, and deposition, and thus affect product yield. The flatness of a wafer may deviate due to various manufacturing steps (e.g., deposition and / or etching) used in forming semiconductor devices on the wafer.

[0051] Typically, layer (or film) deposition on a wafer may cause stress and bending (or bowing) of the wafer. Figure 1A-1B An example of wafer bending according to an embodiment of the present disclosure is shown. Figure 1A , wafer 320 includes a layer (eg, a thin film) 323 formed over a substrate 325. The deposition of layer 323 may induce stress, so that a middle region of wafer 320 may move upward relative to reference plane 350, while an edge of wafer 320 may bend (or bend) downward. Figure 1B , wafer 330 includes a layer (eg, a thin film) 333 formed over a substrate 335. The deposition of layer 333 may cause Figure 1A The wafer 330 may bend (or bend) upward relative to the reference plane 350, and thus the middle region of the wafer 330 may move downward relative to the reference plane 350, while the edge of the wafer 330 may bend (or bend) upward. This upward or downward bending or bending of the wafer may be characterized using parameters such as wafer bow (or bend) of the wafer, as described below.

[0052] Figure 2 The variation of wafer flatness across a wafer 300 according to an embodiment of the present disclosure is shown. The wafer 300 may include a front surface 311 on the front side and a back surface 312 on the back side. In an example, semiconductor device(s) may be fabricated over the front surface (or working surface) 311 on the front side.

[0053] The flatness of wafer 300 can be described using any suitable parameters relative to a reference plane (e.g., reference plane 302) and measured using any suitable method. The reference plane can be selected in any suitable different ways depending on how the flatness is characterized. The reference plane can be selected to include three points at specified locations, for example, on front surface 311, on intermediate surface 301 between front surface 311 and rear surface 312, on a least squares fit to intermediate surface 301, on rear surface 312, on a least squares fit to rear surface 312, and so on. In an example, the reference plane can be a plane of a sample holder of a metrology tool or a processing tool, such as reference plane 303.

[0054] refer to Figure 2 In various examples, wafer flatness can be described using wafer bow (or bowing) of wafer 300. For example, wafer bowing of wafer 300 can be described as the distance between point B and reference plane 302. Point B can be located at the mid-thickness of wafer 300 (along the Z direction perpendicular to reference plane 302) and at the center of the wafer (in the XY plane parallel to reference plane 302). In an example, reference plane 302 is a least squares fit to mid-surface 301. Although a specific distance is used to indicate wafer bowing, wafer bowing can be indicated by any other distance, such as Figure 2 The distance B1 in.

[0055] Wafer bending symbols can be used to indicate things like Figure 1A-1B Different types of stress are shown in Figure 2. In the example, negative bending indicates Figure 1A , while positive bending corresponds to Figure 1B The stress in .

[0056] As described above, any suitable parameter including wafer bow may be used to characterize or define wafer flatness. For simplicity, the following description uses wafer bow of a wafer to represent wafer flatness. However, the methods and embodiments in the present disclosure are applicable to other scenarios where other parameters such as warpage are used to describe wafer flatness. When other parameters are used to describe wafer flatness, the description of the methods and embodiments in the present disclosure may be appropriately modified.

[0057] Generally, wafer flatness, such as wafer bow, may be measured using any suitable method, such as a non-contact measurement method / device, including a non-contact electrical method with capacitance measurement, a non-contact optical method, etc. Optical methods may include optical interferometry, optical critical dimension (OCD) measurement, etc. In some examples, the optical method uses a patterned wafer geometry (PWG) metrology tool.

[0058] As described above, the curvature of the wafer affects the device manufacturing process and product yield, so when a semiconductor device is formed on a wafer, the curvature can be measured at one or more steps or stages. In some examples, forming a semiconductor device may include wafer-level bonding, such as bonding two wafers (e.g., a first wafer and a second wafer) face to face, wherein the front side of the first wafer is bonded to the front side of the second wafer. Portions of the semiconductor device including, for example, transistors may be fabricated on the front side of the first wafer and the front side of the second wafer, respectively. The two wafers should be flat (e.g., the flatness (e.g., curvature) of the two wafers meets the requirements) so that the bonding structures of the two wafers are aligned with each other.

[0059] In an example, a first wafer (e.g., an array wafer including a three-dimensional (3D) NAND array) and a second wafer (e.g., a peripheral wafer including peripheral circuits for controlling the 3D NAND array) are manufactured separately and then bonded face to face to form a semiconductor device (e.g., a semiconductor memory device). Typically, the array wafer may have a relatively large curvature due to manufacturing steps, such as deposition and / or etching. Therefore, before the array wafer and the peripheral wafer are bonded together, the curvature of the array wafer may need to be compensated (or reduced) by any suitable curvature compensation method or flattening method. In an example, a combination of one or more layers (referred to as a compensation layer) is formed on the back side of the array wafer to flatten the array wafer. The properties of the layer including layer thickness, (multiple) materials, and / or the like can be determined based on the curvature (e.g., amplitude and sign) of the array wafer before the layer is formed. In an example, tensile stress is required on the back side of the array wafer, so a silicon nitride layer can be deposited on the back side of the array wafer.

[0060] In order to reduce the wafer bow by the compensation method, the wafer bow is determined before the compensation method is performed. Various methods can be used to determine the wafer bow. In an example, the wafer bow can be determined by measuring the curvature radius of the wafer using any suitable measuring device capable of measuring the curvature radius. Figure 3 The relationship between the curvature of the wafer 320 and the radius of curvature R1 of the wafer 320 according to an embodiment of the present disclosure is shown. The curvature K is the inverse of the radius of curvature R1 of the wafer 320 (e.g., K=1 / R1). The wafer radius is represented as R0. The curvature of the wafer 320 may depend on the curvature K and the wafer radius R0. Therefore, if the curvature K or the radius of curvature (1 / K) is known, the curvature of the wafer 320 may be determined. In the example, the curvature of the wafer 320 is approximately proportional to the curvature K.

[0061] If the bow of each array wafer to be bonded is measured before bow compensation (or reduction) is performed by backside deposition of a compensation layer, a large number of bow measurement devices may be required as the number of wafers to be measured increases, thereby increasing manufacturing costs. In addition, performing bow measurement on each wafer interrupts the manufacturing process, increases manufacturing time, and thus reduces productivity. Therefore, methods that avoid the need for such measurements, such as by predicting wafer bow without measuring actual bow and / or without interrupting the manufacturing process for each wafer, can reduce manufacturing time, improve productivity, and reduce manufacturing costs.

[0062] Wafer flatness, such as indicated by wafer bow (also referred to as out-of-plane deformation), may be correlated to wafer expansion in the XY plane (also referred to as in-plane deformation). Figures 4A-4C An exemplary relationship between the bow of the wafer 320 and the wafer expansion ΔL in one direction (eg, the X direction, the Y direction, or another direction) within the XY plane is shown.

[0063] Figure 4A A first situation is shown, where wafer 320 includes substrate 325 before forming layer 323. Two structures 401 on wafer 320 are separated by a distance L in one direction (eg, X direction), and the curvature of wafer 320 is indicated as a first curvature.

[0064] Figure 4B A second situation is shown, where wafer 320 includes substrate 325 and layer 323, as shown in FIG. Figure 1A For example, due to stress caused by the deposition of layer 323, the two structures 401 are further apart (greater than L). The bowing of wafer 320 is indicated as a second bow.

[0065] Figure 4CA distance L+ΔL between the two structures 401 along the direction is shown for the second case. The wafer expansion ΔL along the direction can be related to the first bend of the wafer 320 and the second bend of the wafer 320. In an example, the wafer expansion ΔL is approximately proportional to the difference between the second bend and the first bend. As described above, the wafer bend is related to the radius of curvature of the wafer. Therefore, the wafer expansion ΔL can be approximately proportional to the difference between the second radius of curvature of the wafer 320 in the second case and the first radius of curvature of the wafer 320 in the first case. If the first radius of curvature or the first bend is known, or the first bend can be determined to be minimum (e.g., considered to be zero), the second radius of curvature and / or the second bend can be determined based on the wafer expansion ΔL.

[0066] Typically, wafer expansion data (e.g., wafer expansion along a direction within the XY plane) can be measured during a lithography process as part of a manufacturing process, and thus a separate device and / or step is not required to measure wafer bow based on the wafer expansion data. Thus, manufacturing costs can be reduced and productivity can be improved. After obtaining the wafer expansion data, wafer bow can be derived based on the relationship between wafer expansion and wafer bow, such as Figures 4A-4C Wafer expansion data may be collected in the same measurement used to perform lithography or in a separate measurement used to derive wafer bow.

[0067] Wafer flatness (e.g., bow) of a wafer may be required in a manufacturing step or stage with a wafer flatness requirement. Manufacturing steps with such wafer flatness requirements may include, for example, bonding steps (e.g., wafer-level bonding), forming wordline contacts, etc. However, for example, when a lithography process is not performed in a manufacturing step, no wafer expansion data corresponding to the manufacturing step is available. According to aspects of the present disclosure, when a semiconductor device is manufactured using a manufacturing process including a plurality of manufacturing steps, wafer expansion (or wafer expansion data) may be measured at a first time (T1) (e.g., at a first manufacturing step) in the manufacturing process before predicting the flatness (or bow) of the wafer at a second time (T2) (e.g., at the second manufacturing step) in the manufacturing process. The second time may occur later than the first time. In some embodiments, the second time may be equal to the first time. Wafer bow at a later time (e.g., the second time) may be predicted based on the wafer expansion data at the first time. Wafer expansion data may be measured using lithography for the first step.

[0068] In an example, in order for the wafer expansion measured at the first manufacturing step to accurately predict the wafer flatness (or bow) at the second manufacturing step, the first manufacturing step is selected as the manufacturing step that is closest in time to the second manufacturing step. Which manufacturing step is selected as the first manufacturing step for measuring the wafer expansion can be determined based on the device manufacturing process and requirements. For example, the number of manufacturing steps between the second manufacturing step and the first manufacturing step is minimized. In an example, there are no other lithography processes between the first time (e.g., at the first manufacturing step) and the second time (e.g., at the second manufacturing step). In some examples, the structural changes of the semiconductor device caused by the (multiple) manufacturing steps between the first time and the second time are relatively small, for example, the difference in bow between the first bow (e.g., corresponding to the wafer expansion at the first time) and the bow at the second time is less than a threshold value, so as to accurately predict the wafer flatness.

[0069] In general, the flatness of the wafer at time T2 may depend on the flatness of the wafer at time T1 (e.g., wafer bow) and changes in flatness (if any) caused by the manufacturing step(s) performed on the wafer between time T1 and time T2. Time T2 may be greater than time T1 and be a later time than T1.

[0070] According to aspects of the present disclosure, a flatness prediction model may be configured to determine the flatness (e.g., bow) of a wafer at T2 based on the flatness of the wafer at T1. The flatness of the wafer at T1 may be indicated, for example, by the wafer expansion measured at T1. The flatness prediction model may indicate a relationship between a flatness variable F1 (e.g., an output of the flatness prediction model) and one or more input variables (e.g., (multiple) inputs to the flatness prediction model). The flatness variable F1 may indicate the flatness of the wafer at T2. The one or more input variables may include any one or any suitable combination of the following: (i) at least one expansion variable E indicating flatness at T1 (e.g., an X expansion variable E indicating X expansion along the X direction); x , Y expansion variable E indicating Y expansion along the Y direction y ), (ii) at least one waiting time (also called queue time) variable Q associated with the manufacturing step(s) between T1 and T2 time1 To Q timei , (iii) one or more process parameters (e.g., process temperature, process time, process type) of the corresponding manufacturing step(s), and / or the like. The integer i is positive and indicates the number of at least one waiting time included in the flatness prediction model. Each of the at least one waiting time (e.g., Q time1 ) is the waiting time between two manufacturing steps that the wafer waits to be processed.

[0071] Since the change in flatness between T1 and T2 can depend on the (multiple) manufacturing steps performed on the wafer between T1 and T2, each process can affect the flatness at T2. Therefore, by incorporating the impact of process parameters associated with (multiple) manufacturing steps, the flatness prediction model can be made more accurate. One manufacturing step can have a greater impact than another manufacturing step. In an example, process parameters that have a relatively large impact on flatness at T2 are incorporated into the flatness prediction model. Process parameters that have a relatively large impact on flatness at T2 may include expansion data, (multiple) waiting times, and / or the like.

[0072] The one or more input variables may include a plurality of input variables. In an example, the plurality of input variables include at least one expansion variable and at least one wait time variable. The flatness variable F1 may be written as a function f1 of the plurality of input variables as in Formula 1, indicating that the flatness at T2 depends on at least one wafer expansion and at least one wait time at T1.

[0073] Fl = f1(E x , E y , Q time1 , ... Q timei ,.) Formula 1

[0074] In an example, the plurality of input variables include at least one expansion variable, at least one queue time variable, and one or more process parameters. The flatness variable F1 can be written as a function f2 of the plurality of input variables as in Formula 2, where the integer J is positive and indicates the number of manufacturing steps to be considered in the flatness prediction model. empj and Tj may represent the temperature and processing duration of the j-th process.

[0075] Fl = f2(E x , E y , Q time1 , ..., Q timei ,T emp1 ,T1,..., T empj , T j ) Formula 2

[0076] In an example, the flatness variable F1 can be written as a function f3 of multiple input variables as in Formula 3, where at least one queue time is constrained to a smaller range. For example, the total range available for one of the at least one queue time variables is 3-12 hours. Using Formula 3, a sub-range (e.g., 4 to 5 hours) of the total range (e.g., 3-12 hours) is selected.

[0077] Fl = f3(E x, E y , Q time1 In the first range, ..., Q timei In the i-th range, ...) Formula 3

[0078] In an example, the plurality of input variables include a plurality of expansion variables, such as an X expansion variable and a Y expansion variable. The flatness variable F1 can be written as a function f4 of the plurality of input variables as in Formula 4.

[0079] Fl = f4(E x , E y ) Formula 4

[0080] In an example, one or more input variables include an expansion variable (eg, E x or E y ). The flatness variable F1 can be written as a function f5 of the expansion variable as in Formula 5.

[0081] Fl = f5(E x ) Formula 5

[0082] Typically, time T2 may be greater than time T1 and be a later time than T1. Formulas 1-5 may be used to determine the flatness at T2 based on the corresponding expansion data collected at T1. In an example, time T2 is time T1, and Formula 4 or Formula 5 may be used to determine the flatness at T1 based on the corresponding expansion data collected at T1.

[0083] In various examples, for a flatness prediction model including one or more input variables, such as shown in Formulas 1-5, the flatness prediction model may determine flatness based on (multiple) inputs to a subset or a complete set of the one or more input variables. x 、E y , Q time1 ,...,Q time The flatness may be determined using the flatness prediction model in Formula 1 based on one or more (multiple) inputs of . In an example, the flatness may be determined based on X-dilation and using the flatness prediction model in Formula 1.

[0084] According to aspects of the present disclosure, a method for determining wafer flatness (e.g., bow of a wafer) of, for example, a first wafer is described. At least one wafer expansion (or expansion data) (e.g., X expansion and / or Y expansion) of the first wafer collected during a lithography process for patterning structures on a working surface of the first wafer can be stored. During the lithography process, the at least one wafer expansion can be measured along one or more directions parallel to the working surface of the first wafer. For example, the one or more directions are in the range of 0 to 100 degrees. Figure 2Prior to performing a manufacturing step with a wafer flatness requirement, wafer flatness of a first wafer may be determined based on at least one wafer expansion using a flatness prediction model such as that described above that predicts wafer flatness using equations 1-5.

[0085] In an example, after the lithography process and before the flatness is determined using the flatness prediction model, the first wafer may be modified using a plurality of manufacturing steps including forming a structure. A flatness prediction model may be used, such as shown in Formulas 1-3, to calculate the flatness based on at least one wafer expansion and a waiting time between two of the plurality of processes (e.g., Q time1 ) to determine wafer flatness.

[0086] Any suitable machine learning algorithm can be used to update (e.g., optimize) the flatness prediction model, for example, to determine the flatness of the wafer with higher accuracy. For example, in addition to using the flatness prediction model to predict flatness (referred to as virtual measurement), the actual flatness of a subset of wafers to be predicted (e.g., 10%) is directly measured, and the flatness of the actual measured wafer subset is thus obtained. The flatness prediction model can be updated using a machine learning algorithm based on the flatness of the actual measured wafer subset and the predicted flatness of the wafer subset. For example, the flatness prediction model can be continuously updated when the actual flatness of additional wafers and the predicted flatness of additional wafers are available.

[0087] Advantages of the flatness prediction method include a significant reduction in actual flatness measurements, for example, a 90% reduction in the number of wafers whose flatness is measured, and thus a significant reduction in the number of measurement devices used to measure the actual flatness, and higher productivity as the measurement time used in the flatness measurement is reduced. Therefore, a flatness prediction method including a combination of virtual measurement of multiple wafers and selective measurement of a small subset (e.g., 80-90%) of the multiple wafers may be suitable for mass production.

[0088] Before describing the flatness prediction method in detail, the following describes a semiconductor device (eg, Figure 5 A semiconductor device is manufactured on a wafer based on the wafer flatness determined using the flatness prediction method.

[0089] Figure 5 A cross-sectional view of a semiconductor device according to some embodiments of the present disclosure, such as a semiconductor memory device 100, is shown. The semiconductor memory device 100 can be formed using wafer-level bonding of a first wafer 501 and a second wafer 502. Wafer-level bonding results in face-to-face bonding of two dies. In an example, the semiconductor memory device 100 includes two dies bonded face-to-face.

[0090] Specifically, in Figure 5 In the example of , the semiconductor device 100 (or semiconductor memory device 100) includes an array die 102 and a CMOS die 101 bonded face to face. Note that in some embodiments, the semiconductor memory device may include multiple array dies and CMOS dies. Multiple array dies and CMOS dies may be stacked and bonded together. The CMOS die is coupled to the multiple array dies, respectively, and the corresponding array dies may be driven in a similar manner.

[0091] The semiconductor device 100 can be any suitable device. In some examples, the semiconductor device 100 includes a first wafer 501 and a second wafer 502 bonded face to face. The array die 102 is arranged on the first wafer 501 together with other array dies, and the CMOS die 101 including, for example, peripheral circuits is arranged on the second wafer 502 together with other CMOS dies. The first wafer 501 and the second wafer 502 are bonded together, so that the array die on the first wafer 501 is bonded to the corresponding CMOS die on the second wafer 502. In some examples, the semiconductor device 100 is a semiconductor chip in which at least the array die 102 is bonded to the CMOS die 101. In an example, semiconductor chips are cut from the bonded wafers (e.g., the first wafer 501 and the second wafer 502). In another example, the semiconductor device 100 is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0092] The array die 102 includes one or more semiconductor portions 105 and insulating portions 106 between the semiconductor portions 105. A memory cell array may be formed in the semiconductor portion 105, and the insulating portion may isolate the semiconductor portion 105 and provide space for a contact structure 170. The CMOS die 101 includes a substrate 104 and peripheral circuits formed on the substrate 104. For simplicity, a major surface (of a die or wafer) is referred to as an XY plane, and a direction perpendicular to the major surface is referred to as a Z direction.

[0093] In addition, Figure 5 In the example of FIG. 1 , the connection structure 121 and the pad structures 122 - 123 are formed on the back side of one of the two dies, such as the array die 102 . Figure 5 In the example of FIG. 1 , the pad structures 122 - 123 are above the insulating portion 106 , and each of the pad structures 122 - 123 can be conductively connected to one or more contact structures 170 . Figure 5In some examples, the connection structure 121 is above the semiconductor portion 105 and is conductively connected to the semiconductor portion 105. In some examples, the semiconductor portion 105 is coupled to an array common source (ACS) of a memory cell array, and the connection structure 121 is disposed above the (multiple) semiconductor portions 105 of the memory cell array block. In some examples, the connection structure 121 is formed of a metal layer having a relatively low resistivity, and when the connection structure 121 covers a relatively large portion of the semiconductor portion 105, the connection structure 121 can connect the ACS of the memory cell array block with extremely small parasitic resistance. The connection structure 121 may include a portion of a pad structure configured as an ACS to receive an ACS signal from an external source. The pad structures 122-123 and the connection structure 121 are made of a suitable (multiple) metal material (e.g., aluminum, etc.), which can facilitate the attachment of bonding wires. In some examples, the pad structures 122-123 include a titanium layer 126 and an aluminum layer 128, and the connection structure 121 includes a titanium silicide layer 127 and an aluminum layer 128.

[0094] For ease of illustration, some components of the semiconductor memory device 100 , such as a passivation structure, are not shown.

[0095] The array die 102 initially includes a substrate and a semiconductor portion 105, and an insulating portion 106 is formed on the substrate. The substrate is removed before forming the pad structures 122-123 and the connecting structure 121.

[0096] Figure 6 A flowchart outlining a process 200A for forming a first semiconductor device (eg, semiconductor memory device 100) according to some embodiments of the present disclosure is shown, and Figure 8-13 A cross-sectional view of a semiconductor memory device 100 during a process according to some embodiments is shown. The process 200A may include predicting wafer flatness using a flatness prediction model such as described above. The process 200A starts at S201A and proceeds to S210A.

[0097] At S210A, at least one wafer expansion of a first wafer collected during a lithography process for a first semiconductor device (e.g., semiconductor memory device 100) may be stored. As described below in step S214A, at least one wafer expansion of the first wafer collected during the lithography process may be used to predict wafer flatness (or bow) at another manufacturing step (e.g., a second manufacturing step or at a second time T2) having a wafer flatness requirement. For a manufacturing process having multiple lithography processes, the lithography process for measuring wafer expansion may be determined based on the device manufacturing process and the requirements. In an example, in order to accurately predict wafer flatness at a second manufacturing step or at a second time (e.g., T2), a lithography process is selected as the lithography process that is closest in time to the second manufacturing step, and thus there are no other lithography processes between the lithography process and the second manufacturing step.

[0098] In an example, at least one wafer expansion of the first wafer is measured during a lithography process. The lithography process may include alignment, exposure, inspection, and / or the like. In an example, the lithography process includes metrology after exposing and developing the photoresist. The at least one wafer expansion of the first wafer may be measured before or after exposure, such as during alignment. In an example, the at least one wafer expansion of the first wafer is measured during metrology.

[0099] Figure 8 A cross-sectional view of a semiconductor memory device 100 at a photolithography process (eg, before forming vertical memory cell strings) is shown. The semiconductor memory device 100 includes an array die 102. In some embodiments, the array die 102 is fabricated on a first wafer 501 along with other array dies.

[0100] The array die 102 includes a substrate 103. On the substrate 103, one or more semiconductor portions 105 and insulating portions 106 are formed. The insulating portion 106 is formed of an insulating material, such as silicon oxide, etc., which can isolate the semiconductor portion 105. In an example, a memory cell array will be formed in the semiconductor portion 105, and a contact structure will be formed in the insulating portion 106.

[0101] Substrate 103 may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and / or a silicon on insulator (SOI) substrate. Substrate 103 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. Group IV semiconductors may include Si, Ge, or SiGe. Substrate 103 may be a bulk wafer or an epitaxial layer. In some examples, the substrate is formed of a plurality of layers. For example, substrate 103 includes a plurality of layers, such as a bulk portion 111, a silicon oxide layer 112, and a silicon nitride layer 113, such as Figure 8 shown.

[0102] In some examples, semiconductor portion 105 is formed on substrate 103, and a block of 3D NAND memory cell strings will be formed in semiconductor portion 105. Semiconductor portion 105 is conductively coupled to the array common source of the memory cell strings. In some examples, the memory cell array will be formed as an array of vertical memory cell strings in core region 115. In addition to core region 115, array die 102 also includes step region 116 and insulating region 117. Step region 116 is used to facilitate forming connections to, for example, the gates of memory cells in the vertical memory cell string, the gates of the select transistors, etc. The gates of the memory cells of the vertical memory cell string correspond to the word lines of the NAND memory architecture. Insulating region 117 is used to form insulating portion 106.

[0103] Layer stack 190 includes alternately stacked gate layers 195 and insulating layers 194. Gate layers 195 and insulating layers 194 are configured to form vertically stacked transistors. In some examples, the transistor stack includes a memory cell and a selection transistor, such as one or more bottom selection transistors, one or more top selection transistors, etc. In some examples, the transistor stack may include one or more dummy selection transistors. Gate layer 195 corresponds to the gate of the transistor. Gate layer 195 is made of a gate stack material, such as a high dielectric constant (high k) gate insulator layer, a metal gate (MG) electrode, etc. Insulating layer 194 is made of an insulating material (e.g., silicon nitride, silicon dioxide, etc.).

[0104] exist Figure 8 In some examples, a common source layer 189 is formed and is conductively connected to the source of the vertical memory cell string. The common source layer 189 may include one or more layers. In some examples, the common source layer 189 includes a silicon material such as intrinsic polysilicon, doped polysilicon (such as N-type doped silicon, P-type doped silicon, etc.), etc. In some examples, the common source layer 189 may include a metal silicide to improve conductivity.

[0105] According to some aspects of the present disclosure, in some examples, semiconductor portion 105 and common source layer 189 are conductively coupled, so semiconductor portion 105 can be configured as an array common source for vertical memory cell strings formed in semiconductor portion 105 .

[0106] The first portion of the first semiconductor device may be disposed on the front side of the first wafer, for example, above the working surface. In some embodiments, the first semiconductor device is a semiconductor memory device 100, and the first wafer is a first wafer 501. In an example, reference Figure 8, a first portion of a first semiconductor device (eg, semiconductor memory device 100) includes a semiconductor portion 105 formed over a substrate 103, a common source layer 189, and a layer stack 190. Figure 8 The semiconductor memory device 100 shown performs a photolithography process. For clarity, a mask layer over the first wafer 501 used in the photolithography process is not shown.

[0107] At least one wafer expansion of the first wafer 501 may be measured during the lithography process, and the time when the lithography process is performed is referred to as a first time (e.g., T1). The at least one wafer expansion of the first wafer 501 may include one or more wafer expansions along one or more corresponding directions in the XY plane (e.g., parallel to the working surface of the first wafer), such as an X wafer expansion along the X direction and / or a Y wafer expansion along the Y direction. In an example, the X direction is perpendicular to the Y direction.

[0108] At S212A, after the photolithography process, (multiple) manufacturing steps may be performed on the first semiconductor device. In an example, a second portion (eg, Fig. 9 In an example, certain structures and / or materials are removed from the first semiconductor device.

[0109] In the example, refer to Fig. 9 , (multiple) manufacturing steps include forming a vertical memory cell string 180. A photolithography process is used in a manufacturing step for patterning a structure on the front side of the first wafer. For example, a pattern of channel holes arranged in an XY plane may be formed after the photolithography process.

[0110] The (multiple) manufacturing steps include forming a vertical memory cell string 180 including a channel structure 181. Since the (multiple) manufacturing steps include (multiple) etchings, multiple depositions of different materials, etc., the first wafer 501 can be queued (multiple times) between etching and multiple depositions and wait for processing. Therefore, the first wafer 501 can experience at least one waiting time in the (multiple) manufacturing steps. The queuing time between two manufacturing steps in the multiple manufacturing steps can be any suitable duration, such as on the order of hours, such as 3-12 hours.

[0111] refer to Fig. 9 In some examples, vertical memory cell strings 180 can be formed in semiconductor portion 105. Semiconductor portion 105 is conductively coupled to an array common source of memory cell strings 180. In some examples, a memory cell array is formed in core region 115 as an array of vertical memory cell strings.

[0112] exist Fig. 9In the example of FIG. 1 , a vertical memory cell string 180 is shown as a representation of a vertical memory cell string array formed in the core region 115 . The vertical memory cell string 180 is formed in a layer stack 190 .

[0113] According to some aspects of the present disclosure, a vertical memory cell string is formed by a channel structure 181 extending vertically (Z direction) into the layer stack 190. The channel structures 181 can be arranged separately from each other in the XY plane. In some embodiments, the channel structure 181 is arranged in an array between gate line cutting structures (not shown). The gate line cutting structure is used to facilitate the replacement of the sacrificial layer with the gate layer 195 in the post-gate process. The array of the channel structure 181 may have any suitable array shape, such as a matrix array shape along the X direction and the Y direction, a zigzag array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. In some embodiments, each channel structure has a circular shape in the XY plane and a columnar shape in the XZ plane and the YZ plane. In some embodiments, the number and arrangement of the channel structure between the gate line cutting structures are not limited.

[0114] In some embodiments, the channel structure 181 has a columnar shape extending in the Z direction perpendicular to the direction of the main surface of the substrate 103. In an embodiment, the channel structure 181 is formed of a material having a circular shape in the XY plane and extending in the Z direction. For example, the channel structure 181 includes functional layers such as a blocking insulating layer 182 (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) 183, a tunneling insulating layer 184 (e.g., silicon oxide), a semiconductor layer 185, and an insulating layer 186, which have a circular shape in the XY plane and extend in the Z direction. In an example, the blocking insulating layer 182 (e.g., silicon oxide) is formed on the side wall of the hole for the channel structure 181 (which enters the layer stack 190), and then the charge storage layer (e.g., silicon nitride) 183, the tunneling insulating layer 184, the semiconductor layer 185, and the insulating layer 186 are stacked in sequence from the side wall. Semiconductor layer 185 may be any suitable semiconductor material, such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be undoped or may include p-type or n-type dopants. In some examples, the semiconductor material is an undoped intrinsic silicon material. However, due to defects, in some examples, the intrinsic silicon material may have a 10 10 cm -3 The insulating layer 186 is formed of an insulating material such as silicon oxide and / or silicon nitride, and / or may be formed as an air gap.

[0115] According to some aspects of the present disclosure, channel structure 181 and layer stack 190 together form memory cell string 180. For example, semiconductor layer 185 corresponds to the channel portion of a transistor in memory cell string 180, and gate layer 195 corresponds to the gate of a transistor in memory cell string 180. Typically, a transistor has a gate that controls the channel and has a drain and a source on each side of the channel. For simplicity, in Fig. 9 In the example, Figure 3 The bottom side of the channel of a transistor is called the drain, while Fig. 9 The upper side of the channel of a transistor in is called the source. The drain and source can be switched under certain drive configurations. Fig. 9 In the example of FIG. 1 , semiconductor layer 185 corresponds to a connection channel of the transistor. For a particular transistor, Fig. 9 In the example of , the drain of a particular transistor is connected to the source of a lower transistor below the particular transistor, and the source of the particular transistor is connected to the drain of an upper transistor above the particular transistor. Thus, the transistors in the memory cell string 180 are connected in series. "Up" and "down" are specifically for Fig. 9 used, wherein the array die 102 is arranged upside down.

[0116] The memory cell string 180 includes memory cell transistors (or referred to as memory cells). Based on carrier capture in a portion of the charge storage layer 183 corresponding to the floating gate of the memory cell transistor, the memory cell transistor may have different threshold voltages. For example, when a large number of holes are captured (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is lower than a predefined value, so the memory cell transistor is in an unprogrammed state (also referred to as an erased state) corresponding to logic "1". When holes are discharged from the floating gate, the threshold voltage of the memory cell transistor is higher than a predefined value, so the memory cell transistor is in a programmed state corresponding to logic "0" in some examples.

[0117] The memory cell string 180 includes one or more top select transistors configured to couple / decouple memory cells in the memory cell string 180 with a bit line, and includes one or more bottom select transistors configured to couple / decouple memory cells in the memory cell string 180 with an ACS.

[0118] The top selection transistor is controlled by a top selection gate (TSG). For example, when the TSG voltage (the voltage applied to the TSG) is greater than the threshold voltage of the top selection transistor, the top selection transistor in the memory cell string 180 is turned on and the memory cells in the memory cell string 180 are coupled to the bit line (for example, the drain of the memory cell string is coupled to the bit line); and when the TSG voltage (the voltage applied to the TSG) is less than the threshold voltage of the top selection transistor, the top selection transistor is turned off and the memory cells in the memory cell string 180 are decoupled from the bit line (for example, the drain of the memory cell string is decoupled from the bit line).

[0119] Similarly, the bottom selection transistor is controlled by a bottom selection gate (BSG). For example, when the BSG voltage (the voltage applied to the BSG) is greater than the threshold voltage of the bottom selection transistor in the memory cell string 180, the bottom selection transistor is turned on and the memory cells in the memory cell string 180 are coupled to the ACS (for example, the source of the memory cell string in the memory cell string 180 is coupled to the ACS); and when the BSG voltage (the voltage applied to the BSG) is less than the threshold voltage of the bottom selection transistor, the bottom selection transistor is turned off and the memory cells are decoupled from the ACS (for example, the source of the memory cell string in the memory cell string 180 is decoupled from the ACS).

[0120] like Fig. 9 As shown, the upper portion of the semiconductor layer 185 in the channel hole corresponds to the source side of the vertical memory cell string 180, and the upper portion is labeled 185 (S). Fig. 9 In the example of FIG. 1 , common source layer 189 is formed to be conductively connected to the source of vertical memory cell string 180. Common source layer 189 is similarly conductively connected to the sources of other vertical memory cell strings (not shown) in semiconductor portion 105, and thus forms an array common source (ACS).

[0121] exist Fig. 9 In the example of the embodiment of the present invention, in the channel structure 181, the semiconductor layer 185 extends vertically downward from the source side of the channel structure 181 and forms a bottom portion corresponding to the drain side of the vertical memory cell string 180. The bottom portion of the semiconductor layer 185 is marked as 185 (D). Note that the drain side and the source side are named for convenience of description. The drain side and the source side may function differently from the name.

[0122] At S214A, wafer flatness of the first wafer after the (plurality) manufacturing steps may be determined (or predicted) based on the flatness prediction model.

[0123] The wafer flatness of the first wafer 501 at a second time (eg, T2) can be predicted. Fig. 9The second time may be after (multiple) manufacturing steps, for example, after forming the vertical memory cell string 180 and the gate layer 195. In an example, the second portion includes the vertical memory cell string 180 and the gate layer 195. Fig.11 In an example, the second time is also before forming the contact structure 170 and the word line connection structure (also referred to as word line contact) 150. The second time may also be before forming the bonding structures 174 and 164.

[0124] Typically, the flatness prediction model is configured to determine the wafer flatness of the first wafer based on one or more of: (i) at least one expansion indicative of flatness at a first time (e.g., T1) (e.g., at a photolithography process), (ii) at least one waiting time between the first time (e.g., T1) and a second time (e.g., T2), (iii) one or more process parameters (e.g., process temperature, process time) of corresponding (multiple) manufacturing steps, and / or the like, such as described in Formulas 1-5.

[0125] Thus, the input to the flatness prediction model may include one or more of: (i) at least one expansion, (ii) at least one waiting time between the first time and the second time, (iii) one or more process parameters of the corresponding (multiple) manufacturing steps, and / or the like. The output of the flatness prediction model may indicate wafer flatness, such as bow, of the first wafer (e.g., first wafer 501).

[0126] In an example, wafer flatness is indicated by a bow of the first wafer, and the flatness prediction model is a bow prediction model that predicts the bow of the first wafer based on input(s) similar to or the same as the input(s) of the flatness prediction model described above. The bow of the first wafer may be determined based on the bow prediction model.

[0127] In an example, the flatness prediction model is based on a machine learning algorithm and is updated based on the measured wafer flatness and predicted wafer flatness of the third wafer. During a lithography process for patterning a structure on the front side of the third wafer, at least one wafer expansion of the third wafer may be measured. In an example, at least one wafer expansion of the third wafer is measured at a third time. For example, before performing a manufacturing step with a wafer flatness requirement, the wafer flatness of the third wafer may be determined using a flatness prediction model. The flatness prediction model may be configured to determine the wafer flatness of the third wafer based on at least one wafer expansion of the third wafer. In an example, the wafer flatness of the third wafer at a fourth time is predicted. In addition, before a manufacturing step with a wafer flatness requirement for the third wafer, for example, at a fourth time, the actual wafer flatness of the third wafer may be measured. Typically, the flatness of the third wafer has minimal or no change between the actual measurement and the determination using the flatness prediction model. The flatness prediction model may be updated based on the measured wafer flatness of the third wafer and the predicted wafer flatness of the third wafer.

[0128] The updated flatness prediction model can be used by other wafers for which flatness is to be predicted. In an example, the fourth time is later than the third time. In an example, the fourth time is the third time.

[0129] In an example, the third wafer is different from the first wafer, and at T2, no actual measurement is performed on the first wafer to determine the flatness of the first wafer. The updated flatness prediction model can be used to predict the flatness of the first wafer at T2.

[0130] In an example, the third wafer is the first wafer and the above description may be adjusted. The measurement of at least one wafer expansion of the third wafer and the determination of the flatness of the third wafer using the flatness prediction model may be omitted.

[0131] At S216A, a layer having a thickness based on the determined wafer flatness of the first wafer may be deposited on the back side of the first wafer. In an example, the thickness is determined to adjust the wafer flatness so as to meet the wafer flatness requirement. In an example, after depositing the layer, the wafer flatness of the first wafer meets the wafer flatness requirement. In the example described in S216A, the thickness of the layer is adjusted to meet the wafer flatness requirement. In general, one or more properties of the layer, such as the thickness, the material composition of the layer, the position of the layer, the process for forming the layer, and / or the like, may be used to meet the wafer flatness requirement.

[0132] As above reference Figure 1A-1BAs described above, generally, the predicted flatness or bow of a first wafer such as the first wafer 501 may indicate the nature of the stress (e.g., tensile stress or compressive stress) of the first wafer 501. In order to reduce the bow of the first wafer 501, the thickness of the layer may be determined based on the magnitude of the predicted bow. The material may be determined based on the nature of the stress (e.g., tensile stress or compressive stress) indicated by the predicted flatness and the location where the layer will be deposited (e.g., the back side of the first wafer). In an example, a material that produces tensile stress will be deposited on the back side of the first wafer, so a material such as silicon nitride, polysilicon, tungsten, etc. may be used. In an example, the layer may include silicon nitride. Reference Fig.10 , which layer may be a silicon nitride layer 199 on the back side of the first wafer 501 .

[0133] At S218A, the wafer flatness of the first wafer after the layer is deposited may be measured, for example, by optical critical dimension (OCD) measurement. In an example, S218A is omitted and the wafer flatness of the first wafer after the layer is deposited is not measured. If the measured wafer flatness (e.g., the measured bow) meets the wafer flatness requirement, the process 200A proceeds to S220A. Otherwise, the process 200A may proceed to S299 and terminate or return to S216A.

[0134] At S220A, the first wafer and the second wafer are bonded face to face. Fig.11 A cross-sectional view of the semiconductor memory device 100 is shown after the first wafer 501 is face-to-face bonded to the second wafer 502. The semiconductor memory device 100 includes an array die 102 and a CMOS die 101 that are face-to-face bonded.

[0135] In some embodiments, the array die 102 is manufactured on the first wafer 501 together with other array dies, and the CMOS die 101 is manufactured on the second wafer 502 together with other CMOS dies. In some examples, the first wafer 501 and the second wafer 502 are manufactured separately. A first bonding structure is formed on the front side of the first wafer 501. Similarly, peripheral circuits are formed on the second wafer 502 using a process operating on the front side of the second wafer 502, and a second bonding structure is formed on the front side of the second wafer 502.

[0136] In some embodiments, the first wafer 501 and the second wafer 502 may be bonded face-to-face using a wafer-to-wafer bonding technique. A first bonding structure on the first wafer 501 is bonded to a corresponding second bonding structure on the second wafer 502, so that the array die on the first wafer 501 is bonded to the CMOS die on the second wafer 502, respectively. In general, any suitable steps performed on the first wafer 501 may be performed on the second wafer to predict the wafer flatness (or wafer bow) of the second wafer at a later manufacturing step with a flatness requirement, and then compensate for the wafer bow. For example, steps S210A, S214A, S216A, and S218A are suitable for storing at least one wafer expansion measured in a lithography process, using the at least one wafer expansion to predict the wafer flatness of the second wafer in a later manufacturing step, depositing a layer over the second wafer to meet the flatness requirement, wherein one or more attributes (e.g., the thickness of the layer) may be determined based on the predicted wafer flatness. Optionally, the wafer flatness after the deposition of the layer may be measured.

[0137] Furthermore, a contact structure may be formed in the insulating portion 106. The CMOS die 101 includes a substrate 104, and includes peripheral circuits formed on the substrate 104. The substrate 104 may be similar or identical to the substrate 103, and thus a detailed description may be omitted for the sake of brevity.

[0138] exist Fig.11 In the example of FIG. 1 , a memory cell array is formed on a substrate 103 of an array die 102, and a peripheral circuit is formed on a substrate 104 of a CMOS die 101. The array die 102 and the CMOS die 101 are disposed face to face (the surface on which the circuit is disposed is referred to as the front side, and the opposite surface is referred to as the back side), and are bonded together.

[0139] exist Fig.11 In the example of FIG. 1 , an interconnect structure such as a via 162 , a metal wire 163 , a bonding structure 164 , etc. may be formed to electrically couple the bottom portion 185 (D) of the semiconductor layer to the bit line (BL).

[0140] In addition, Fig.11 In the example of , the step region 116 includes a step formed to facilitate a word line connection to the gate of a transistor (e.g., a memory cell, (multiple) top selection transistors, (multiple) bottom selection transistors, etc.). For example, the word line connection structure 150 includes a word line contact plug 151, a via structure 152, and a metal wire 153 that are conductively coupled together. The word line connection structure 150 can electrically couple WL to the gate terminal of the transistor in the memory cell string 180.

[0141] exist Fig.11In the example of FIG. 1 , the contact structure 170 is formed in the insulating region 117. In some embodiments, the contact structure 170 can be formed simultaneously with the word line connection structure 150 by processing on the front side of the array die 102. Therefore, in some examples, the contact structure 170 has a similar structure to the word line connection structure 150. Specifically, the contact structure 170 may include a contact plug 171, a via structure 172, and a metal line 173 that are conductively coupled together.

[0142] In some examples, a mask including a pattern for contact plug 171 and word line contact plug 151 may be used. The mask is used to form contact holes for contact plug 171 and word line contact plug 151. An etching process may be used to form the contact holes. In an example, etching of the contact hole for word line contact plug 151 may stop on gate layer 195, and etching of the contact hole for contact plug 171 may stop in oxide layer 112. In addition, the contact hole may be filled with a suitable liner layer (e.g., titanium / titanium nitride) and a metal layer (e.g., tungsten) to form contact plugs, such as contact plug 171 and word line contact plug 151. Further back-end of line (BEOL) processes are used to form various connection structures, such as via structures, metal lines, bonding structures, etc.

[0143] In addition, Fig.11 In the example of FIG. 1 , bonding structures are formed on the front side of array die 102 and CMOS die 101, respectively. For example, bonding structures 174 and 164 are formed on the front side of array die 102, and bonding structures 131 and 134 are formed on the front side of CMOS die 101.

[0144] exist Fig.11 In the example, a first wafer 501 including an array die 102 is arranged face to face (the circuit side is the front side, and the substrate side is the back side) and bonded together with a second wafer 502 including a CMOS die 101. Therefore, the array die 102 and the CMOS die 101 are arranged face to face and bonded together. The corresponding bonding structures on the first wafer 501 and the second wafer 502 are aligned and bonded together, and a bonding interface that conductively couples appropriate components on the two wafers is formed. For example, the bonding structure 164 is bonded to the bonding structure 131 to couple the drain side of the memory cell string 180 to the bit line (BL). In another example, the bonding structure 174 is bonded to the bonding structure 134 to couple the contact structure 170 on the array die 102 to the I / O circuit on the CMOS die 101.

[0145] refer to Fig.11In the example, the first wafer is the first wafer 501, and the second wafer is the second wafer 502 (e.g., a peripheral wafer or a CMOS wafer). In the example, after S216A, a contact structure 170, a word line connection structure 150, and bonding structures 174 and 164 are formed on the first wafer, wherein the flatness (e.g., curvature) of the first wafer 501 meets the wafer flatness requirement. The bonding structures (e.g., 164, 174) of the first semiconductor device (e.g., semiconductor memory device 100) on the first wafer (e.g., first wafer 501) can be bonded to corresponding bonding structures (e.g., 131, 134) of the peripheral wafer including the peripheral circuit for controlling the 3D NAND array.

[0146] In various examples, such as in the manufacture of 3D NAND memory devices, the curvature of an array wafer including (multiple) 3D NAND arrays and without curvature compensation using layer 199 is significantly greater than the curvature of a peripheral wafer to be bonded to the array wafer. Therefore, before the bonding step, the curvature of the array wafer (e.g., first wafer 501) is measured or predicted, and then the curvature is reduced by layer 199. In an example, the curvature of the peripheral wafer is not measured or predicted, and it does not need to be reduced because the curvature of the peripheral wafer is relatively small. In an example, the curvature of the peripheral wafer can be measured and / or predicted. The curvature of the peripheral wafer can be reduced similarly to that described in reference S216A.

[0147] In S222A, a substrate of the first wafer may be removed from the back side of the first wafer. The removal of the first substrate exposes the semiconductor portion and the contact structure 170 on the first die or the back side of the first wafer.

[0148] In some examples, after the wafer-to-wafer bonding process, the first wafer 501 having the array die is bonded to the second wafer 502 having the CMOS die. Then, the first substrate is thinned from the back side of the first wafer 501. In an example, a chemical mechanical polishing (CMP) process or a grinding process is used to remove most of the bulk portion 111 of the first wafer 501. In addition, the remaining bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113 can be removed from the back side of the first wafer 501 using an appropriate etching process.

[0149] In some examples, step S222A may be adjusted as follows: The bonded first wafer 501 and second wafer 502 may be singulated into a plurality of bonded array dies 102 and CMOS dies 101. Subsequently, the substrate of the array die 102 (eg, the first die) may be removed from the back side of the array die 102.

[0150] Fig.12FIG. 5 shows a cross-sectional view of the semiconductor memory device 100 after the first substrate 103 is removed from the array die 102 or the first wafer 501. Fig.12 In the example of FIG. 5 , the bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113 are removed from the back side of the array die 102 or the first wafer 501. The removal of the bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113 can expose the end of the contact structure 170 protruding from the insulating portion 106 (as shown by 175). The removal of the bulk portion 111, the silicon oxide layer 112, and the silicon nitride layer 113 can also expose the semiconductor portion 105.

[0151] At S224A, a pad structure and a connection structure for the first semiconductor device may be formed at the back side of the first die on the first wafer. In some embodiments, the pad structure includes a first pad structure conductively connected to the contact structure 170 . The connection structure is conductively connected to the semiconductor portion 150 .

[0152] In some embodiments, the pad structure and the connection structure are mainly formed of aluminum (Al). In some embodiments, (multiple) interface layers can be formed between aluminum and semiconductor portion 105. In some examples, a metal silicide film can be used as (multiple) interface layers. In an example, the metal silicide film can be used to achieve ohmic contact between aluminum and semiconductor portion 105. In another example, the metal silicide film is used to form a local interconnect to semiconductor portion 105. In another example, the metal silicide film is used as a diffusion barrier to prevent aluminum from diffusing into semiconductor portion 105.

[0153] In some examples, titanium is deposited on the entire back side of a first wafer bonded face-to-face with a second wafer and then heated in a nitrogen atmosphere. Titanium can react with exposed silicon surfaces (e.g., semiconductor portion 105) to form titanium silicide. Portions of titanium (e.g., above the insulating portion, above the end of contact structure 170, etc.) are not reacted to form silicide.

[0154] Then, metal film(s) may be formed on the surface of the back side of the first wafer. Fig.13 1 shows a cross-sectional view of the semiconductor memory device 100 after deposition of metal film(s). Fig.13 In the example of , the metal film 120 is deposited on the back side of the first wafer. Due to the protrusion of the end of the contact structure 170, the metal film 120 may have an uneven surface. In some embodiments, the metal film 120 includes a titanium layer 126 and an aluminum layer 128. In an embodiment, the titanium layer 126 on the semiconductor portion 105 may react with the silicon surface to form titanium silicide 127. For example, the titanium layer 126 is deposited and heated in a nitrogen atmosphere. Then the aluminum layer 128 is deposited.

[0155] The metal film 120 may be patterned to form a pad structure and a connection structure. Figure 5 FIG. 1 is a cross-sectional view of the semiconductor memory device 100 after the metal film 120 is patterned into the pad structures 122-123 and the connection structure 121. Figure 5 In the example of FIG, pad structures 122-123 are respectively connected to contact structure 170 and are disposed above insulating portion 106; connection structure 121 is connected to semiconductor portion 105. In some embodiments, according to a mask, a photolithography process is used to define patterns of pad structures 122-123 and connection structure 121 in a photoresist layer, and then an etching process is used to transfer the patterns to metal film 120, thereby forming pad structures 122-123 and connection structure 121.

[0156] The process 200A is described using a semiconductor memory device, such as semiconductor memory device 100, as an example, and forming a semiconductor memory device such as semiconductor memory device 100. Figure 5 The specific structure shown. Process 200A, which includes predicting the flatness of a wafer using a flatness prediction model, can be appropriately adapted to form other types of semiconductor devices or the same type of semiconductor devices with different and / or additional structures. One or more steps in process 200A can be modified or omitted. For example, S212A can be omitted, so that the flatness of the wafer at T1 can be predicted based on at least one wafer expansion measured at T1 using a flatness prediction model. Process 200A can be performed in any suitable order. Additional (multiple) steps can be added. The wafer manufacturing process can continue with further processes, such as passivation, testing, cutting, etc.

[0157] Figure 7 A flow chart outlining a process 200B for determining wafer flatness according to some embodiments of the present disclosure is shown. Figure 6 The portion of process 200A shown in FIG. Figure 7 An example of process 200B in FIG. Process 200B starts at S201B and proceeds to S210B.

[0158] At S210B, at least one wafer expansion of the first wafer is stored. The at least one wafer expansion of the first wafer may be collected or measured during a photolithography process for a first semiconductor device (e.g., semiconductor memory device 100). As described above with reference to S210A, the at least one wafer expansion of the first wafer may be measured during a photolithography process for the first semiconductor device. The first portion of the first semiconductor device may be disposed on a front side of the first wafer, e.g., above a working surface. In S210A, reference may be made to the front side of the first wafer. Figure 6 and 8An example of S210B is described. In some embodiments, the first semiconductor device is the semiconductor memory apparatus 100. The first wafer is the first wafer 501. In some embodiments, the first semiconductor device includes a circuit other than a NAND array(s).

[0159] During the lithography process, at least one wafer expansion of the first wafer may be measured, and the time when the lithography process is performed is referred to as a first time (e.g., T1). The at least one wafer expansion of the first wafer may include one or more wafer expansions along corresponding one or more directions in an XY plane (e.g., parallel to a working surface of the first wafer), such as an X wafer expansion along an X direction and / or a Y wafer expansion along a Y direction. In an example, the X direction is perpendicular to the Y direction.

[0160] At S212B, after the photolithography process, (multiple) manufacturing steps may be performed on the first semiconductor device. In an example, a second portion (eg, Fig. 9 In an example, certain structures and / or materials are removed from the first semiconductor device.

[0161] Since the manufacturing steps include (multiple) etchings, multiple depositions of different materials, etc., the first wafer may be queued (multiple times) between (multiple) etchings and multiple depositions and wait for processing. Therefore, as described above, the first wafer may experience at least one waiting time in (multiple) manufacturing steps. In S212A, refer to Figure 6 and Fig. 9 An example of S212B is described.

[0162] At S214B, wafer flatness of the first wafer after the (plurality of) manufacturing steps may be determined (or predicted) based on the flatness prediction model.

[0163] The wafer flatness of the first wafer at a second time (eg, T2) may be predicted. The second time may be after (multiple) manufacturing steps, as described in S214A.

[0164] As above reference Figure 6 The flatness prediction model is configured to determine the wafer flatness of the first wafer based on one or more of the following: (i) at least one expansion indicating flatness at a first time (e.g., T1) (such as at a photolithography process), (ii) at least one waiting time between the first time (e.g., T1) and a second time (e.g., T2), (iii) one or more process parameters (e.g., process temperature, process time) of the corresponding (multiple) manufacturing steps, and / or the like, such as described in Formulas 1-5.

[0165] In an example, wafer flatness is indicated by a bow of the first wafer, and the flatness prediction model is a bow prediction model that predicts the bow of the first wafer based on input(s) similar or the same as the input(s) to the flatness prediction model described above. The bow of the first wafer may be determined based on the bow prediction model.

[0166] In an example, the flatness prediction model is based on a machine learning algorithm and is updated based on the measured wafer flatness and the predicted wafer flatness of the third wafer, as described with respect to process 200A.

[0167] In an example, the third wafer is different from the first wafer, and at T2, no actual measurement is performed on the first wafer to determine the flatness of the first wafer. The updated flatness prediction model can be used to predict the flatness of the first wafer at T2.

[0168] In an example, the first wafer is a third wafer and the above description may be adjusted. The measurement of at least one wafer expansion of the third wafer and the determination of the flatness of the third wafer using the flatness prediction model may be omitted. Figure 6 An example of S214B is described in S214A of FIG.

[0169] At S216B, a layer having a thickness based on the determined wafer flatness of the first wafer may be deposited on the back side of the first wafer. In an example, the thickness is determined to adjust the wafer flatness so as to meet the wafer flatness requirement. In an example, after depositing the layer, the wafer flatness of the first wafer meets the wafer flatness requirement. Figure 6 An example of S216B is described in S216A of FIG.

[0170] At S218B, the wafer flatness of the first wafer after the deposition layer may be measured, for example, by OCD measurement. Figure 6 An example of S218B is described in S218A of FIG. If the measured wafer flatness (eg, measured bow) meets the wafer flatness requirement, process 200B proceeds to S299B and terminates. Otherwise, process 200B may proceed to S299B or return to S216B.

[0171] In addition to determining the flatness of the first wafer using the flatness prediction model and updating the flatness prediction model, process 200B may include additional manufacturing steps (multiple steps) to form the first semiconductor device, such as bonding the first wafer face-to-face to another wafer, such as Figure 6The process 200A described above may be described in process 200B. One or more steps in process 200B may be adjusted or omitted. For example, S212B may be omitted, so that the wafer flatness at T1 may be predicted based on at least one wafer expansion measured at T1 and using a flatness prediction model. Process 200B may be performed in any suitable order. Additional step(s) may be added. The wafer manufacturing process may continue with further processes such as passivation, testing, segmentation, etc.

[0172] In an example, the flatness of multiple wafers is required before performing a manufacturing step with a wafer flatness requirement, and layers can be deposited on the wafers to adjust the flatness of the multiple wafers. According to aspects of the present disclosure, processes 200A and 200B can be performed on multiple wafers as follows. A virtual flatness measurement can be performed on each of the multiple wafers, where a flatness prediction model is used to determine the flatness of the corresponding wafer. However, actual flatness measurements are performed only on a subset of the multiple wafers, for example, to update the flatness prediction model. A subset of the multiple wafers is a small set of the multiple wafers, such as 10%. Both the virtual flatness measurement and the actual flatness measurement can be performed before layer deposition. In an example, the results of the virtual flatness measurement and the actual flatness measurement of each wafer indicate the flatness of the wafer at T2, and the results of the virtual flatness measurement are based on the expansion data measured at T1.

[0173] As described above, which manufacturing step is selected as the first manufacturing step for measuring wafer expansion can be determined based on the device manufacturing process and requirements. In an example, a contact structure (e.g., Figure 5 The wafer flatness (or wafer bow) is determined in a manufacturing step after the contact structure 170 in the contact structure 170. Therefore, the first manufacturing step can be used to form the contact structure 170. Therefore, the wafer expansion of the first wafer (e.g., the first wafer 501) in the semiconductor device (e.g., the semiconductor device 100) is measured using a photolithography process, which, for example, patterns the contact holes for the contact plugs 171 in the contact structure 170 and the word line contact plugs 151 in the word line connection structure 150, respectively.

[0174] Figures 14A-14D The relationship between wafer expansion measured at a first time corresponding to a first manufacturing step (or first manufacturing stage) and the corresponding wafer flatness of the wafer measured at a second time corresponding to a second manufacturing step (or second manufacturing stage) according to an embodiment of the present disclosure is shown. The first manufacturing step may be performed before the second manufacturing step.

[0175] exist Fig.14A, the vertical axis corresponds to the X wafer expansion along the X direction measured at a first time, and the horizontal axis corresponds to the first bow (or X bow) of the wafer measured at a second time. The measurement of the first bow of the wafer at the second time is performed on the layer used to reduce the bow (e.g., Fig.10 199). Each data point represents an X wafer expansion and a first bow measurement of a wafer. The raw data (e.g., data points) and the linear fit show a linear relationship between the X wafer expansion and the measured first bow of the wafer. The linear relationship indicates that the X wafer expansion and bow of a wafer corresponding to different manufacturing steps (and at different times) may have a linear relationship. Therefore, the X wafer expansion corresponding to one manufacturing step can be used to predict the wafer bow corresponding to another manufacturing step.

[0176] exist Fig. 14B , the vertical axis corresponds to the Y wafer expansion along the Y direction measured at a first time, and the horizontal axis corresponds to the second bow (or Y bow) of the wafer measured at a second time. Each data point represents a Y wafer expansion and second bow measurement of a wafer. The raw data (e.g., data points) and the linear fit indicate a linear relationship between the Y wafer expansion measured at a first manufacturing step and the second bow of the wafer measured at a second manufacturing step. Similar to the reference Fig.14A As described, the linear relationship indicates that the Y wafer expansion and bow of the wafer corresponding to different manufacturing steps may have a linear relationship. Therefore, the Y wafer expansion corresponding to one manufacturing step can be used to predict the wafer bow corresponding to another manufacturing step.

[0177] exist Fig. 14C , the vertical axis corresponds to the sum of X wafer expansion and Y wafer expansion corresponding to the first manufacturing step, and the horizontal axis corresponds to the sum of the first bow and the second bow of the wafer measured corresponding to the second manufacturing step (or (X+Y) bow). The raw data (e.g., data points) and the linear fit indicate a linear relationship between the sum of X wafer expansion and Y wafer expansion measured at the first manufacturing step and the sum of the first bow and the second bow of the wafer measured corresponding to the second manufacturing step.

[0178] exist Fig.14D , the vertical axis corresponds to the difference between X wafer expansion and Y wafer expansion corresponding to a first manufacturing step, and the horizontal axis corresponds to the difference between the first bow and the second bow of the wafer measured corresponding to a second manufacturing step (or (XY) bow). The raw data (e.g., data points) and the linear fit indicate a linear relationship between the difference between X wafer expansion and Y wafer expansion measured at the first manufacturing step and the difference between the first bow and the second bow of the wafer measured corresponding to the second manufacturing step.

[0179] In conclusion, Figures 14A-14DAn exemplary linear relationship between wafer expansion corresponding to a first manufacturing stage and bow corresponding to a second manufacturing stage is shown. Bow corresponding to the second manufacturing stage can be predicted based on wafer expansion corresponding to the first manufacturing stage.

[0180] On the other hand, despite Figures 14A-14D A linear relationship between wafer expansion corresponding to the first manufacturing stage and bow corresponding to the second manufacturing stage is indicated, but the variation in the raw data from each linear fit is relatively large, indicating that other variable(s) may affect the relationship between wafer expansion corresponding to the first manufacturing stage and bow corresponding to the second manufacturing stage. Such variables may include queue time(s), processing parameters, and / or the like.

[0181] Figures 15A-15D It is shown that according to an embodiment of the present disclosure, the relationship between wafer expansion corresponding to a first manufacturing stage and bow corresponding to a second manufacturing stage may depend on the queue time.

[0182] Fig.15A Corresponds to Fig.14A ,in Fig.15A The horizontal and vertical axes in Fig.14A The horizontal and vertical axes are the same. Fig.14A The original data and linear fit in Fig.15A Draw it using bright circles.

[0183] Described below Fig.15A and Fig.14A In general, the queue time for one wafer can be different from the queue time for another wafer. In the example, the variation in queue time between different wafers is large. An example of a queue time is the queue time between the CMP and the second manufacturing step when the bow is measured (referred to as the CMP queue time). Fig.14A In , the range (e.g., full range) of CMP queue times can be relatively large (e.g., a full range of 9 hours from 3 to 12 hours). Fig.15A , the data points shown as dark circles (ie, a subset of the original data) represent a subset of wafers having CMP queue times that are confined within a sub-range of CMP queue times (eg, a sub-range of 1 hour from 4 to 5 hours).

[0184] Compare Fig.14A and Fig.15A , by reducing the variation of queue times (e.g., CMP queue times), Fig.15A The wafer flatness (e.g. bow) in the Fig.14A , a better correlation (e.g., a larger correlation factor). Fig.15AComparison of the raw data in the bright circles in FIG. 1 with a subset of the raw data in the dark circles in FIG. 2 shows that the flatness of the wafer (e.g., bow of the wafer) at a later manufacturing stage (e.g., a second manufacturing stage) may depend on the queue time in addition to the expansion data (e.g., X expansion, Y expansion, and / or the like). Therefore, a flatness prediction model (e.g., bow prediction model) may be made more accurate by incorporating one or more queue times (e.g., CMP queue times).

[0185] Fig. 15B Corresponds to Fig. 14B ,in Fig. 15B The horizontal and vertical axes in Fig. 14B The horizontal and vertical axes are the same. Fig. 14B The original data and linear fit in Fig. 15B The bright circles are shown in FIG. Fig. 15B and Fig. 14B The difference between Fig.15A and Fig.14A The differences between are as described above, so a detailed description is omitted for the sake of brevity.

[0186] Fig.15D Corresponds to Fig.14D ,in Fig.15D The horizontal and vertical axes in Fig.14D The horizontal and vertical axes are the same. Fig.14D The original data and linear fit in Fig.15D The bright circles are shown in FIG. Fig.15D and Fig.14D The difference between Fig.15A and Fig.14A The differences between are as described above, so a detailed description is omitted for the sake of brevity.

[0187] therefore, Fig.14A and Fig.15A , Fig. 14B and Fig. 15B as well as Fig.14D and Fig.15D The comparison shows that wafer flatness or wafer bow depends on the queue time, so by incorporating (multiple) queue times (eg, CMP queue time), the flatness prediction model (eg, bow prediction model) can be more accurate.

[0188] Fig. 15CThe relationship between wafer flatness (e.g., bow) and queue time (e.g., CMP queue time) according to an embodiment of the present disclosure is shown. As shown here, wafer flatness or wafer bow (e.g., the sum of the first bow and the second bow of the wafer (or (X+Y) bow)) depends on the queue time, so by incorporating (multiple) queue times (e.g., CMP queue time), a flatness prediction model (e.g., bow prediction model) can be more accurate.

[0189] Figures 14A-14D An exemplary linear relationship between wafer expansion corresponding to a first manufacturing stage and bow corresponding to a second manufacturing stage is shown. In general, wafer flatness (e.g., bow) corresponding to the second manufacturing stage can depend on one or more variables, such as wafer expansion corresponding to the first manufacturing stage and (multiple) other variables, such as (multiple) queue times, processing parameters, and / or the like. Wafer flatness (e.g., bow) corresponding to the second manufacturing stage can have a linear or nonlinear relationship with each of the one or more variables. A flatness prediction model (e.g., bow prediction model) can predict flatness (e.g., bow) corresponding to the second manufacturing stage based on the linear or nonlinear relationship between flatness and each of the one or more variables. In an example, for example, with reference to Figures 15A-15D As described, by taking into account (multiple) other variables (e.g., queue time), the parameters characterizing the relationship (e.g., linear relationship) between the flatness (e.g., bow) corresponding to the second manufacturing stage and the wafer expansion corresponding to the first manufacturing stage can be more accurate.

[0190] Fig.16 A comparison of actual measured bow and predicted bow according to an embodiment of the present disclosure is shown. The horizontal axis represents the wafers whose bow is actually measured and predicted. The vertical axis represents the actual measured bow (squares) and the predicted bow (diamonds). Fig.17 The correlation of the actual measured bending and the predicted bending is shown in , where the horizontal axis represents the actual measured bending and the vertical axis represents the predicted bending. Fig.17 The correlation factor R is shown 2 The linear trend of 0.96 indicates that the flatness prediction model (eg, the curvature prediction model) is highly accurate.

[0191] Can be based on (such as Figure 16-17 The flatness prediction model is updated by using the measured wafer flatness and the predicted wafer flatness as shown in FIG. As described above, the flatness prediction model may indicate a relationship between the flatness variable F1 and one or more input variables, such as an X expansion variable Ex, a Y expansion variable Ey, a queue time variable Q associated with (multiple) manufacturing steps between T1 and T2, and a queuing time variable Q2. time1 To Q timei, process parameters of the corresponding (multiple) manufacturing steps (e.g., process temperature, process time, process type), and / or the like. In an example, when more input variables are considered in the flatness prediction model, the flatness prediction model can be made more accurate, such as Figures 15A-15D As shown, in addition to the expansion variables, the queue time is also included. Figures 15A-15D Similar to the method described in , where the queue time is taken into account, the flatness prediction model can further include other input variables. By including another input variable determined to have a relatively large impact, the flatness prediction model can be made more accurate.

[0192] In some examples, a machine learning algorithm is used and optimized by including more input variables in addition to the X-inflation variable Ex, the Y-inflation variable Ey, and the queue time in the flatness prediction model.

[0193] In some examples, a mathematical relationship between the flatness variable F1 and one or more input variables is obtained, such as shown in Formulas 1-5, and then the mathematical relationship can be made more accurate by comparing the measured wafer flatness with the predicted wafer flatness. In an example, a mathematical relationship between the flatness variable F1 and the expansion variables (e.g., X expansion variable Ex and Y expansion variable Ey) is obtained when considering different additional input variables of the corresponding (multiple) manufacturing steps (e.g., queue time variables, process parameters (e.g., process temperature, process time, process type)).

[0194] The above methods can be implemented as computer software using computer readable instructions and physically stored in one or more computer readable media, such as non-transitory computer readable storage media. In an example, the computer software can be embedded in a controller or other circuit for semiconductor manufacturing equipment. In an example, one or more computer readable media can be read by a controller, a computing device, or a computer system for semiconductor manufacturing equipment. For example, Fig.18 A computer system (1800) suitable for implementing certain embodiments of the present disclosure is shown. The computer system (1800) may include a computing device, and the computing device may include processing circuitry configured to determine wafer flatness using one or more of the methods described in the present disclosure.

[0195] Computer software may be encoded using any suitable machine code or computer language, which may be subjected to mechanisms such as assembly, compilation, linking, etc. to create code comprising instructions that may be executed directly by one or more computer central processing units (CPUs), graphics processing units (GPUs), etc., or through interpretation, microcode execution, etc.

[0196] The instructions may be executed on various types of computers or components thereof, including, for example, personal computers, tablet computers, servers, smart phones, gaming devices, IoT devices, etc. In an example, the instructions may be executed in a computing device used in a semiconductor manufacturing process.

[0197] Fig.18 The components for the computer system (1800) shown in the example are exemplary in nature and are not intended to impose any limitation on the scope of use or functionality of computer software implementing embodiments of the present disclosure. Nor should the configuration of components be interpreted as having any dependency or requirement on any one component or combination of components shown in the exemplary embodiment of the computer system (1800).

[0198] The computer system (1800) may include certain human-machine interface input devices. Such human-machine interface input devices may be responsive to input from one or more human users through, for example, tactile input (such as keystrokes, swipes, data glove movements), audio input (such as voice, clapping), visual input (such as gestures), olfactory input (not shown). The human-machine interface devices may also be used to capture certain media that are not necessarily directly related to a person's conscious input, such as audio (such as voice, music, ambient sounds), images (such as scanned images, photographic images obtained from a still image camera), and videos (such as two-dimensional video, three-dimensional video including stereoscopic video).

[0199] The input human-machine interface device may include one or more of the following (only one of each is shown in the figure): keyboard (1801), mouse (1802), trackpad (1803), touch screen (1810), data gloves (not shown), joystick (1805), microphone (1806), scanner (1807), camera (1808).

[0200] The computer system (1800) may also include certain human-computer interface output devices. Such human-computer interface output devices may stimulate one or more human user senses through, for example, tactile output, sound, light, and smell / taste. Such human-computer interface output devices may include tactile output devices (e.g., tactile feedback through a touch screen (1810), a data glove (not shown), or a joystick (1805), but there may also be tactile feedback devices that are not used as input devices), audio output devices (such as: speakers (1809), headphones (not shown)), visual output devices (such as screens (1810), including CRT screens, LCD screens, plasma screens, OLED screens, each with or without touch screen input capabilities, each with or without tactile feedback capabilities - some of which are capable of outputting two-dimensional visual outputs or more than three-dimensional outputs through devices such as stereographic output, virtual reality glasses (not shown), holographic displays, and smoke tanks (not shown)) and printers (not shown).

[0201] The computer system (1800) may also include human-accessible storage devices and their associated media, such as optical media including CD / DVD ROM / RW (1820) with CD / DVD and other media (1821), thumb drives (1822), removable hard drives or solid-state drives (1823), traditional magnetic media such as tapes and floppy disks (not shown), dedicated ROM / ASIC / PLD-based devices such as security dongles (not shown), etc. In an example, the computer system (1800) may include a solid-state device (SSD) drive. The SSD drive may be implemented using 3D NAND semiconductor devices.

[0202] Those skilled in the art should also understand that the term "computer-readable media" used in conjunction with the subject matter disclosed in this disclosure does not include transmission media, carrier waves, or other transient signals.

[0203] The computer system (1800) may also include an interface (1854) to one or more communication networks (1855). The network may be, for example, wireless, wired, optical. The network may also be local, wide area, urban, vehicular and industrial, real-time, delay tolerant, and the like. Examples of networks include: local area networks such as Ethernet, wireless LANs, cellular networks including GSM, 3G, 4G, 5G, LTE, etc., television wired or wireless wide area digital networks including cable, satellite, and terrestrial broadcast television, vehicle and industrial networks including CANBus, and the like. Some networks typically require an external network interface adapter attached to some common data port or peripheral bus (1849) (e.g., a USB port of the computer system (1800)); others are typically integrated into the core of the computer system (1800) by attaching to a system bus as described below (e.g., an Ethernet interface attached to a PC computer system or a cellular network interface attached to a smartphone computer system). Using any of these networks, the computer system (1800) can communicate with other entities. Such communication may be one-way, receive-only (e.g., broadcast television), one-way send-only (e.g., CANbus to certain CANbus devices), or two-way, such as to other computer systems using local or wide area digital networks. Certain protocols and protocol stacks may be used on each of those networks and network interfaces as described above.

[0204] The above-mentioned human interface devices, human-accessible storage devices, and network interfaces may be attached to the core (1840) of the computer system (1800).

[0205] The core (1840) may include one or more central processing units (CPUs) (1841), graphics processing units (GPUs) (1842), dedicated programmable processing units in the form of field programmable gate arrays (FPGAs) (1843), hardware accelerators for certain tasks (1844), graphics adapters (1850), etc. These devices, along with read-only memory (ROM) (1845), random access memory (1846), internal mass storage devices such as internal non-user accessible hard drives, SSDs, etc. (1847), may be connected via a system bus (1848). In some computer systems, the system bus (1848) may be accessible in the form of one or more physical plugs to enable expansion by additional CPUs, GPUs, etc. Peripheral devices may be attached to the core's system bus (1848) directly or via a peripheral bus (1849). In an example, a screen (1810) may be connected to a graphics adapter (1850). The architecture of the peripheral bus includes PCI, USB, etc.

[0206] The CPU (1841), GPU (1842), FPGA (1843), and accelerator (1844) can execute certain instructions, which in combination can constitute the above-mentioned computer code. Computer code including the methods disclosed in the present disclosure can be stored in ROM (1845) or RAM (1846). Transition data can also be stored in RAM (1846), while permanent data can be stored in, for example, an internal mass storage device (1847). Fast storage and retrieval of any of the memory devices can be achieved by using a cache memory, which can be closely associated with one or more CPUs (1841), GPUs (1842), mass storage devices (1847), ROMs (1845), RAMs (1846), etc.

[0207] The computer readable medium may have computer code thereon for performing various computer-implemented operations. The medium and computer code may be those specially designed and constructed for the purposes of the present disclosure, or they may be of a type well known and available to those skilled in the art of computer software.

[0208] As an example and not limitation, a computer system having the architecture (1800), and in particular the core (1840), can provide functionality as a result of (multiple) processors (including CPUs, GPUs, FPGAs, accelerators, etc.) executing software included in one or more tangible computer-readable media. Such computer-readable media can be media associated with a user-accessible mass storage device as described above and a non-transitory specific storage device of the core (1840), such as a core internal mass storage device (1847) or ROM (1845). Software implementing various embodiments of the present disclosure can be stored in such a device and executed by the core (1840). Depending on specific needs, the computer-readable medium may include one or more memory devices or chips. The software can enable the core (1840) and specifically the processors therein (including CPUs, GPUs, FPGAs, etc.) to perform specific processes or specific parts of specific processes described herein, including defining data structures stored in RAM (1846) and modifying such data structures according to processes defined by the software. Additionally or alternatively, a computer system may provide functionality as a result of logic units hardwired or otherwise included in circuits (e.g., accelerators (1844)) that may operate in place of or in conjunction with software to perform a particular process or a particular portion of a particular process described herein. Where appropriate, references to software may include logic units and vice versa. Where appropriate, references to computer-readable media may include circuits (such as integrated circuits (ICs)) storing software for execution, circuits including logic units for execution, or both. The present disclosure includes any suitable combination of hardware and software.

[0209] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for determining wafer flatness, comprising: storing a first wafer expansion of a first wafer, the first wafer expansion of the first wafer collected along a first direction parallel to the working surface of the first wafer during a photolithography process for patterning structures on the working surface of the first wafer; as well as Prior to a manufacturing step having a wafer flatness requirement, wafer flatness of the first wafer is determined using a flatness prediction model configured to predict the wafer flatness and based on the first wafer expansion collected during the lithography process.

2. The method according to claim 1, further comprising: A layer having a thickness based on the determined wafer flatness of the first wafer is deposited on the back side of the first wafer.

3. The method according to claim 1 or 2, wherein: The method further includes: measuring a second wafer expansion along a second direction parallel to the working surface of the first wafer, the first direction being perpendicular to the second direction; and The determining includes determining the wafer flatness of the first wafer based on the first wafer expansion and the second wafer expansion using the flatness prediction model.

4. The method according to claim 1 or 2, wherein: The method further includes: modifying the first wafer by forming the structure on the working surface of the first wafer using a plurality of manufacturing steps after the photolithography process and before the determining step; and The determining includes determining the wafer flatness of the first wafer using the flatness prediction model and based on the first wafer expansion and a waiting time between two manufacturing steps of the plurality of manufacturing steps.

5. The method according to claim 1 or 2, wherein: The wafer flatness is indicated by a bow of the first wafer, The flatness prediction model is a warp prediction model that predicts the warp of the first wafer, and The determining includes determining the bow of the first wafer based on the first wafer expansion using the bow prediction model.

6. The method according to claim 1 or 2, wherein: The flatness prediction model is based on a machine learning algorithm; and The method further comprises: measuring wafer expansion of the second wafer along a direction parallel to the working surface of the second wafer during a lithography process for patterning structures on the working surface of the second wafer; Before performing the manufacturing step with the wafer flatness requirement on the second wafer, determining wafer flatness of the second wafer based on the wafer expansion of the second wafer using the flatness prediction model; and measuring an actual wafer flatness of the second wafer; and The flatness prediction model is updated based on the measured wafer flatness of the second wafer and the determined wafer flatness of the second wafer.

7. The method according to claim 1 or 2, wherein: The photolithography process is a photolithography process that is performed closest in time to a manufacturing step having the wafer flatness requirement.

8. The method according to claim 4, wherein: The determination includes: The wafer flatness of the first wafer is determined using the flatness prediction model and based on a processing temperature or a processing time of one of the multiple manufacturing steps, wherein the flatness prediction model depends on one of the processing temperature and the processing time of one of the multiple manufacturing steps, expansion of the first wafer, and the waiting time.

9. The method according to claim 1 or 2, wherein: The manufacturing steps with the wafer flatness requirement are performed after forming contact structures and wordline contacts.

10. The method according to claim 1 or 2, wherein: The structure includes a contact structure and a word line contact, and the photolithography process patterns the contact structure and the word line contact.

11. A method for manufacturing a semiconductor device, comprising: obtaining a first wafer expansion of a first wafer, the first wafer expansion being collected along a first direction parallel to a working surface of the first wafer during a photolithography process for patterning structures of the semiconductor device on the working surface of the first wafer; Prior to a bonding step having a wafer flatness requirement, determining wafer flatness of the first wafer based on the first wafer expansion using a flatness prediction model configured to predict the wafer flatness, depositing a layer having a thickness determined based on the determined wafer flatness of the first wafer on the back side of the first wafer; and The first wafer is bonded to the second wafer face to face.

12. The method according to claim 11, wherein: After depositing the layer, the wafer flatness of the first wafer meets the wafer flatness requirement.

13. The method according to claim 11 or 12, wherein: The method further comprises measuring a second wafer expansion along a second direction parallel to the working surface of the first wafer, the first direction being perpendicular to the second direction, and The determining includes determining the wafer flatness of the first wafer based on the first wafer expansion and the second wafer expansion using the flatness prediction model.

14. The method according to claim 11 or 12, wherein: The method further comprises: modifying the first wafer by forming the structure on the working surface of the first wafer using a plurality of manufacturing steps after the photolithography process and before the determining step, and The determining includes determining the wafer flatness of the first wafer using the flatness prediction model configured to predict the wafer flatness and based on the first wafer expansion and a waiting time between two manufacturing steps of the plurality of manufacturing steps.

15. The method according to claim 11 or 12, wherein: The wafer flatness is indicated by a bow of the first wafer, The flatness prediction model is a curvature prediction model, and The determining includes using the bow prediction model that predicts the bow of the first wafer and determining the bow of the first wafer based on the first wafer expansion.

16. The method according to claim 11 or 12, wherein: The flatness prediction model is based on a machine learning algorithm; and The method further comprises: measuring wafer expansion of the third wafer along a direction parallel to the working surface of the third wafer during a lithography process for patterning structures on the working surface of the third wafer; Before performing the bonding step with wafer flatness requirement on the third wafer, determining wafer flatness of the third wafer using the flatness prediction model; and measuring an actual wafer flatness of the third wafer; and The flatness prediction model is updated based on the measured wafer flatness of the third wafer and the determined wafer flatness of the third wafer.

17. The method according to claim 16, further comprising: A layer having a thickness based on the determined wafer flatness of the third wafer is deposited on the back side of the third wafer.

18. The method according to claim 14, wherein: The determination includes: The wafer flatness of the first wafer is determined using the flatness prediction model and based on a processing temperature or a processing time of one of the multiple manufacturing steps, wherein the flatness prediction model depends on one of the processing temperature and the processing time of one of the multiple manufacturing steps, expansion of the first wafer, and the waiting time.

19. The method according to claim 11 or 12, wherein: The semiconductor device is a semiconductor memory apparatus including a 3D NAND array, the first wafer includes a plurality of 3D NAND arrays, and the second wafer includes a peripheral circuit for controlling the 3D NAND arrays.

20. The method according to claim 11 or 12, wherein: The bonding step with the wafer flatness requirement is performed after forming the contact structure and the word line contact.

21. The method according to claim 11 or 12, wherein: The structure includes a contact structure and a word line contact, and the photolithography process patterns the contact structure and the word line contact.

22. The method according to claim 11 or 12, wherein: The structure of the semiconductor device includes a channel structure of a 3D NAND array, and The determining further includes determining the wafer flatness of the first wafer based on the first wafer expansion using the flatness prediction model before fabricating word line contacts of the semiconductor device and after forming the channel structure of the 3D NAND array.

23. The method according to claim 11 or 12, wherein: The photolithography process is a photolithography process that is performed closest in time to a manufacturing step having the wafer flatness requirement.

24. A computing device comprising a processing circuit, the processing circuit being configured to: storing wafer expansion of a wafer, the wafer expansion of the wafer being collected along a first direction parallel to a working surface of the wafer during a photolithography process for patterning structures on the working surface of the wafer; and Prior to a manufacturing step having a wafer flatness requirement, wafer flatness of the wafer is determined using a flatness prediction model configured to predict the wafer flatness and based on the wafer expansion collected during the lithography process.

25. A non-transitory computer-readable storage medium storing a program executable by one or more processors to perform: storing wafer expansion of a wafer, the wafer expansion of the wafer being collected along a first direction parallel to the working surface of the wafer during a photolithography process for forming structures on the working surface of the wafer; and Prior to a manufacturing step having a wafer flatness requirement, the wafer flatness of the wafer is determined using a flatness prediction model configured to predict wafer flatness and based on the wafer expansion collected during the lithography process.

Images