Memory interface with adjustable voltage and termination and method of use

Abstract

A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device is coupled between a power rail and a data line, and wherein the pull-down device is coupled between the data line and ground; and a power supply configured to supply a first supply voltage to the power rail during a terminated data transmission mode, in which a receiving memory interface coupled to the data line has an effective on-chip termination, and wherein the power supply is further configured to supply a second supply voltage to the power rail during an unterminated data transmission mode, in which the on-chip termination does not load the data line, the second supply voltage being less than the first supply voltage.

Description

[0001] This application is a divisional application of a patent application with an international application date of September 9, 2016, an international application number of PCT / US2016 / 051134, a national application number of 201680055256.X, and an invention name of “Memory interface with adjustable voltage and termination and method of use”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Nonprovisional Application No. 14 / 863,890, filed on September 24, 2015, the entire contents of which are incorporated herein by reference as if fully set forth below for all applicable purposes. Technical Field

[0004] The present application relates to memory interfaces with processor devices, and more particularly to memory interfaces with adjustable voltages and terminations. Background Art

[0005] Synchronous dynamic random access memory (SDRAM) is a type of memory used in mobile communications and computing devices such as smartphones and tablets. In some embodiments, double data rate SDRAM (DDR SDRAM or DDR) refers to a type of memory and an associated interface for communicating with the memory. In addition, sometimes referred to as mobile DDR Low power DDR (LPDDR or LP for short) is a type of DDR designed to reduce power consumption, where mobile devices are the target application. There are several versions of LPDDR corresponding to various data speeds and power requirements. For example, LPDDR3 (sometimes also denoted as LP3) and LPDDR4 (sometimes also denoted as LP4) are the two latest versions of LPDDR. LPDDR4 is designed to communicate at higher speeds and consume less power than LPDDR3, but at the expense of increased cost and / or complexity.

[0006] The trend in modern mobile devices (such as smartphones) is to focus memory design on greater memory transfer rates while saving power. System on chip (SoC) is often used in mobile devices to save power and / or minimize space requirements. SoC refers to multiple functional modules, such as modems and application processor cores, that are embedded on a single substrate to allow mobile devices to execute complex and power-hungry applications. The single substrate is sometimes called a bare die, so multiple functional blocks are usually implemented on a single bare die.

[0007] The current generation of low power double data rate (LPDDR4) DRAM uses n-type field effect transistors (NFETs) in its interface for both pull-up and pull-down drivers. In addition, an on-chip termination (ODT) device (e.g., a transistor) may be turned on when receiving data to present a desired impedance to the receive line. This is generally referred to as terminated mode. When the pull-up and pull-down transistors are turned on during data transmission, the pull-up and pull-down transistors are tuned to also present a desired impedance (e.g., 50 ohms).

[0008] The power supply voltage (VDDQ) of a conventional LPDDR4 interface is typically about 1.1V. In a terminated high-speed operating mode in which an ODT transistor is active in the receiving node, the pull-up transistor in the transmitting device and the ODT transistor in the receiving device effectively form a voltage divider that divides the power supply voltage for the pull-up transistor in half. When active, the source voltage of the pull-up transistor is VDDQ minus its threshold voltage, so that the source voltage varies between a minimum of 550mV and a maximum of 888mV (an average of approximately 720mV). Due to the voltage divider formed as just discussed, when the pull-up device is active, the receiving device will receive an average voltage of approximately 350mV. When the pull-down device is active, the received voltage is ground, so that the voltage swing at the receiving node for the terminated high-speed mode is approximately 350mV.

[0009] However, the active ODT device in the terminated mode consumes DC power. Therefore, if the bandwidth of the terminated high-speed mode is not required for the current data transmission, the unterminated slow-down mode can be used. In the unterminated mode, the ODT device is turned off. Since the ODT device of the receiving device is turned off in the unterminated mode, almost no DC power is consumed. However, the voltage swing is equal to the supply voltage of the pull-up device (550mV to 888mV as just described). The AC power is proportional to the square of the voltage swing, making the AC power consumption in the unterminated mode approximately four times that of the AC power consumption in the terminated mode.

[0010] Therefore, there is a need in the art for improved unterminated modes for memory interfaces. Summary of the invention

[0011] A memory interface with an adjustable operating voltage is disclosed. In one example, a transmit and receive memory interface has an adjustable power supply and selectable on-chip termination resistors. The memory interface is coupled to a data transmission line and another transmit and receive memory interface, which also has an adjustable power supply and selectable on-chip termination. Either memory interface can be used for transmission or reception and can be used in terminated or unterminated mode. The transmitting memory interface can adjust its voltage depending on whether it is in terminated or unterminated data transmission mode.

[0012] In one embodiment, a memory interface includes a pull-up device and a pull-down device, wherein the pull-up device is coupled between a power rail and a data line, and wherein the pull-down device is coupled between the data line and ground. The memory interface also includes a power supply configured to supply a first supply voltage to the power rail during a terminated data transmission mode, in which a receiving memory interface coupled to the data line has an effective on-chip termination. The power supply is also configured to supply a second supply voltage to the power rail during an unterminated data transmission mode, in which the on-chip termination does not load the data line, and the second supply voltage is less than the first supply voltage.

[0013] In another embodiment, a method includes transmitting a data signal at a transmit data interface in communication with a transmit channel and a receive data interface. The receive data interface has an on-chip termination resistor configured to be turned on for a first data transmission mode and turned off for a second data transmission mode. The method also includes changing from the first data transmission mode to the second data transmission mode, including changing a speed of the transmit data signal, and in response to changing from the first data transmission mode to the second data transmission mode, adjusting an operating voltage of the transmit data interface.

[0014] In yet another embodiment, a memory interface includes means for transmitting a binary one and means for transmitting a binary zero, wherein the means for transmitting a binary one is coupled between a power rail and a data line, and wherein the means for transmitting a binary zero is coupled between the data line and ground. The memory interface also includes means for applying a first supply voltage to the power rail during a terminated data transfer mode in which a receiving memory interface coupled to the data line has effective on-chip termination, and applying a second supply voltage to the power rail during an unterminated data transfer mode in which the on-chip termination does not load the data line. The second supply voltage is less than the first supply voltage.

[0015] In yet another embodiment, a memory interface circuit includes a first transmit and receive data interface in communication with a second transmit and receive data interface through a transmit channel, wherein the second transmit and receive data interface includes a selectable on-chip termination resistor configured to be turned on in a first data transmission mode and turned off in a second data transmission mode. The memory interface circuit also includes a power supply in communication with the first transmit and receive data interface and configured to apply a first voltage level for the first data transmission mode and a second voltage level for the second data transmission mode, wherein the second voltage level is lower than the first voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is an architectural diagram illustrating an example SoC die and corresponding architecture according to an embodiment of the present disclosure.

[0017] Figure 2 An example processing chip is shown that communicates with a memory chip using multiple interfaces according to an embodiment of the present disclosure.

[0018] Figure 3 An example system including an interface circuit at a processing chip in an interface circuit at a memory chip connected through a transmission channel for data according to an embodiment of the present disclosure is shown.

[0019] Figure 4 An example method for changing voltage based on terminated or unterminated transmission mode according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] Embodiments of memory interfaces including adjustable power supplies and on-chip termination components are disclosed herein. In order to reduce AC power consumption in the memory interface, the VDDQ supply voltage as described above is no longer maintained constant across the terminated mode and the unterminated mode. Instead, the power supply that controls the VDDQ rail is configured to reduce the VDDQ supply voltage when the unterminated mode is valid, and to use a higher level (e.g., a conventional 1.1V) when the terminated mode is valid. For example, the power supply may include a linear dropout regulator (LDO) or a switching power supply that is configured to respond to an indication that the unterminated mode is valid by reducing the VDDQ level. As discussed above, the terminated mode (also referred to as the terminated data transmission mode) generally refers to a data transmission mode in which the ODT device (e.g., a transistor) is turned on on the receiving side, while the unterminated mode (also referred to as the unterminated data transmission mode) generally refers to a data transmission mode in which the ODT device is turned off on the receiving side.

[0021] In one aspect of the present disclosure, VDDQ during unterminated mode can be half the level used for VDDQ during terminated mode. For example, if VDDQ is approximately equal to 1.1V during terminated mode, it can be reduced to a level that allows the voltage swing to still be approximately 350mV during unterminated mode. In another implementation, when switching from terminated mode to unterminated mode, VDDQ can drop from 1.1V to approximately 888mV. The scope of the embodiments is not limited to any particular voltage level for VDDQ at the power rail or VSSQ, as other voltage levels or values ​​may be appropriately employed in alternative implementations; the scope of the embodiments is also not limited to any particular value for the voltage swing. In fact, the voltage values ​​provided herein are for illustration only, and it should be understood that various embodiments may use any suitable voltage, whether lower or higher than those example values ​​mentioned in the present disclosure.

[0022] Figure 1 1 is an architectural diagram illustrating an example system-on-chip (SOC) die 100 and corresponding architecture. In one embodiment, the SoC die 100 is used in a smartphone, tablet computer, or other mobile wireless device. Figure 1 As shown, SoC die 100 includes a plurality of functional blocks including a multi-core processor 110 (sometimes referred to as a central processing unit or CPU), a graphics processor 120 , a modem 130 , and memory circuits 140 . Figure 1 1 is a logical layout of SoC die 100 that shows each of regions 110 - 140 for the indicated functions as separate and distinct regions, although the actual physical layout may be more complex, eg, one functional block circuit is interspersed within another functional block circuit.

[0023] In one embodiment, the modem 130 implements baseband processing for any of a number of known wireless technologies or standards, such as Long Term Evolution (LTE). The processors 110-130 refer to areas of the SoC die 100 dedicated to those functional blocks. In each of these areas, there are circuits for specified functions. The memory circuit 140 may refer to an area of ​​the SoC die 100 dedicated to a memory controller and an interface circuit for interfacing with an external memory. For example, the external memory may be housed in a package having an interface for connecting to the memory circuit 140. The memory circuit 140 may be configured to interface with any type of memory, such as DDR SDRAM, DRAM, or flash memory. For purposes of illustration, the present disclosure focuses on DDR SDRAM such as LPDDR3 and LPDDR4, but the scope of the embodiments is not limited to any particular memory technology or standard. At least one of the multi-core processor 110, the graphics processor 120, and the modem 130 communicates with the memory circuit 140. The various components 110-140 may communicate via any form of known connection such as a bus.

[0024] The memory circuit 140 includes a plurality of interfaces for transmitting data to and receiving data from one or more memory chips. Figure 2 And is shown in more detail, Figure 2A plurality of data transmission lines between the SOC and the memory chip are shown. As described above, each memory interface may include a termination component that can be turned on and off and an adjustable power supply configured to change the voltage level as the interface changes from termination to non-termination and vice versa. The scope of the embodiments is not limited to any particular SoC architecture, or even to multi-core systems, and SoC 100 is shown as an example. In fact, various embodiments may be applicable to any type of interface between a processing circuit and a memory circuit.

[0025] Figure 2 According to an embodiment Figure 1 FIG. 2 shows a system 200 in which the SoC 100 communicates with a memory chip 220 . The SoC 100 communicates with the memory chip 220 via a transmission channel 215 .

[0026] The memory chip 220 in this example includes any suitable memory chip for a computing device having SoC 100. Examples include DDR SDRAM chips, static random access memory (SRAM) chips, dynamic random access memory (DRAM) chips, and electrically erasable programmable read-only memory (flash memory) chips, but the scope of the embodiments is not limited to any particular memory chip. During a write operation, the memory chip 220 receives data from the SoC 100 via a transmission channel (data line) 215, and a memory controller at the memory chip 220 then stores the data in a memory cell of the memory chip. During a read operation, the memory chip 220 receives a read request for specific data from the SoC 100, and the memory controller of the memory chip 220 then accesses the data from the various memory cells of the memory chip and transmits these data bits to the SoC 100 via the transmission channel 215.

[0027] Figure 2 The system may include Figure 1 and 3 In one example, Figure 2 The system 200 operates according to one or more DDR standards, wherein the memory chip 220 is a DDR SDRAM chip. The memory chip 220 includes a plurality of interface circuits configured to transmit and receive data through various transmission channels 215. It is contemplated that there are many interface circuits at the memory chip 220, and thus the interface circuits are collectively shown as TX / RX circuits 224. Each interface circuit is described below with respect to Figure 3 The transmission channels 215 are each connected to a 216-bit DAC. Figure 3The transmission channels 320 are the same or similar, including having characteristic impedance.

[0028] Similarly, SoC 100 also has a plurality of interface circuits configured to transmit and receive data through various transmission channels 215. The interface circuits of SOC 100 are collectively shown as TX / RX 212 in this example. Each interface circuit is described below with respect to Figure 3 The invention operates as described, including having an adjustable power supply and a selectable termination impedance. Figure 1 The memory circuit 140 includes a TX / RX circuit 212 .

[0029] Figure 3 is a diagram of an interface circuit of a SoC coupled to an interface circuit of a memory chip according to one embodiment.

[0030] Figure 3 The left side of FIG. 1 is a diagram of an interface circuit 380 implemented on SOC 100 and in this example represents the Figure 2 One of the interface circuits at the TX / RX circuit 212. Figure 3 To the right of FIG. 2 is a diagram of an interface circuit 390 implemented on the memory chip 220, and in this example represents one of the interface circuits at the TX / RX circuit 224. The interface circuits 380, 390 are coupled via a transmission channel 320, which corresponds to Figure 2 One of the transmission channels 215.

[0031] Transmission channel 320 provides a data link between SoC 100 and memory chip 220. Transmission channel 320 can be implemented in any suitable structure, such as a cable, a metal trace on a printed circuit board, a metal wire connecting chips in a package, a via and a metal trace connecting the SoC package to the memory chip package, etc. Figure 3 , the transmission channel 320 is shown as a transmission line to emphasize its general similarity to a transmission line, including having a characteristic impedance and a resistance-capacitance (RC) time constant. In this example embodiment, the impedance introduced by the termination pattern acts to match the impedance of the interface circuit to the characteristic impedance of the transmission channel 320.

[0032] Referring to the interface circuit 380, the pull-up device 310a is shown as an NFET, as are the pull-down device 312a and the on-chip termination device 314a. The power supply 304a provides a voltage source for VDDQ. As further described below, the power supply 304a is configured to be adjustable so that it can provide at least two voltage levels. The control circuit 302a provides a control signal to the power supply 304a to direct the power supply 304a to apply a first voltage level during the termination mode and to apply a second voltage level in the unterminated mode.

[0033] Interface circuit 390 is configured similarly to interface circuit 380. Specifically, in this example, pull-up device 310b, pull-down device 312b, and on-chip termination device 314b are shown as NFET devices. Power supply 304b is an adjustable voltage source that receives a control signal from control circuit 302b. Control circuit 302b provides a control signal to power supply 304b to direct power supply 304b to apply a first voltage level during termination mode and apply a second voltage level in unterminated mode.

[0034] Despite Figure 3 302a and 302b may be in electrical communication so that they can coordinate terminated and unterminated modes. For example, in an example where control circuit 302a determines that it should change from terminated mode to unterminated mode (or vice versa), control circuit 302a may send a control signal to control circuit 302b to inform control circuit 302b of the appropriate terminated or unterminated mode.

[0035] Furthermore, each of interface circuit 380 and interface circuit 390 is configured to operate in both a transmit mode and a receive mode. Accordingly, control circuit 302b is also configured to determine whether terminated mode or unterminated mode is appropriate and send control signals to control circuit 302a to coordinate operation.

[0036] As described above, interface circuit 380 is a diagram of one of many interface circuits at SoC 100, and interface circuit 390 is a diagram of one of many interface circuits at memory chip 220. In some embodiments, control circuit 302a and power supply 304a may serve more than one interface circuit at SoC 100, and control circuit 302b and power supply 304b may serve more than one interface circuit at memory chip 220. Or in other words, in some embodiments, various interface circuits 100 at SoC may share the same VDDQ and VSSQ power and ground rails, and various interface circuits at memory chip 220 may share the same VDDQ and VSSQ power and ground rails.

[0037] Figure 3 Devices 310, 312, and 314 are shown as NFET devices, but the scope of the embodiments is not limited in this regard. Rather, other embodiments may use a combination of p-type devices and n-type devices (such as complementary metal oxide semiconductor or CMOS embodiments), only p-type devices, or any other suitable device that can be used as a switch. Power supply 304 may include any suitable power supply, such as a switch mode power supply (SMPS), a linear dropout (LDO) voltage regulator, etc.

[0038] As described above, control circuit 302 provides control signals to power supply 304. The logic for determining whether to operate in a terminated mode or an unterminated mode and providing appropriate control signals to facilitate the selected mode can be implemented in hardware, software, or a combination of hardware and software. Such logic can be provided as machine executable code stored in a tangible medium such as RAM on SoC 100 or memory chip 220.

[0039] In an example use case, the interface circuit 380 acts as a transmitter, which transmits data bits to the interface circuit 390 at the memory chip 220 via the transmission channel 320. The control circuit 302 will therefore communicate to coordinate the interface circuit 380 to operate in a transmission mode, and to coordinate in a termination mode or an unterminated operation mode. For the purpose of this example, it is assumed that the interface circuits 380, 390 start in a termination mode. Therefore, the on-chip termination device 314b is turned on (device 314a is turned off).

[0040] Power supply 304a operates at a first voltage level, which is a higher voltage level relative to a second voltage level used during the unterminated mode. For example, the first voltage level of VDDQ can be 1.1V or other appropriate levels. When the transmitted signal is a binary one (high signal), pull-up device 310a is turned on (pull-down device 312a is turned off), and devices 310a and 314b act as a voltage divider, and the voltage observed on the receiving side is approximately 350mV, considering the threshold voltage of device 310a as a voltage drop on the source voltage. When the transmitted signal is a binary zero (low signal), pull-down device 312a is turned on (device 310a is turned off), and the voltage observed on the receiving side is approximately 0V. Therefore, in the terminated mode, the voltage swing observed at the receiving node is approximately 350mV.

[0041] In some LPDDR4 embodiments, the termination mode is suitable for high-speed data transmission (e.g., in the GHz range), while the unterminated mode is more suitable for low-speed data transmission (e.g., in the 100 MHz range). Therefore, when the SOC 100 determines that it is about to switch to low-speed data transmission, it notifies the control circuits 302a and 302b, and the control circuits 302a and 302b send control signals to the corresponding power supplies 304a and 304b to reduce the voltage level of VDDQ. The interface circuits 380, 390 switch to the unterminated mode, in which both terminal devices 314a and 314b are turned off. When the transmitted signal is a binary one (high signal), the pull-up device 310a is turned on, but the voltage is not divided by the termination resistor and is sensed on the receiving side as VDDQ minus the threshold voltage of the pull-up device 310a. In this embodiment, it can be expected that the voltage swing in the unterminated mode is approximately 350 mV, and if the threshold voltage of pull-up device 310a is approximately 150 mV, the voltage applied by power supplies 304a and 304b can be reduced to approximately 500 mV in the unterminated mode.

[0042] Continuing with this example, during the terminated mode of operation, the control circuit 302a sends a control signal to the power supply 304a to cause the power supply 304a to apply a first voltage level (e.g., 1.1V) at the power rail. During the unterminated mode of operation, the control circuit 302a sends a control signal to the power supply 304a to cause the power supply 304a to change its voltage level so that it applies a second voltage level (e.g., 500mV or lower) at the power rail. As the SoC 100 issues read and write operations to the memory chip 220, the SOC 100 (and possibly the memory chip 220) may switch between the terminated mode of operation and the unterminated mode of operation from time to time, thereby providing at least two different voltage levels at the power rail that are suitable for a particular termination mode.

[0043] Furthermore, in this example, interface circuit 390 may be used as a transmitter, and interface circuit 380 may be used as a receiver. Therefore, the actions described above with respect to interface circuit 390 also apply to interface circuit 380 when 380 is used as a receiver. For example, in the terminated operating mode, power supply 304b applies a first voltage to the power rail as VDDQ, and terminal device 314a is turned on (terminal device 314b is turned off). In the unterminated operating mode, power supply 304b applies a second voltage to the power rail as VDDQ, and both terminal devices 314a and 314b are turned off.

[0044] Logic at control circuits 302a and 302b, or at some other appropriate location in SoC 100 or memory chip 220, determines when to switch between high-speed terminated mode and low-speed unterminated mode. Figure 3 It is intended to describe usage at a single set of interfaces sharing common transmission lines, but it should be understood that for each bit of data transferred between the SoC 100 and the memory chip 220, the same or similar actions occur at interfaces associated with other transmission lines.

[0045] Various embodiments may provide one or more advantages over conventional systems. For example, some conventional systems do switch between a terminated high-speed mode and an unterminated low-speed mode, but such conventional systems use the same voltage level for VDDQ for both modes. Due to the use of terminal devices, the terminated mode experiences DC power losses. The unterminated mode has no DC power losses from the terminal devices (because the terminal devices are turned off), but the increased voltage swing causes AC power losses to be greater than the AC power losses in the terminated mode. In fact, AC power losses increase with the square of the voltage level, so as the voltage swing increases, AC power losses can become significant.

[0046] On the contrary, the above Figures 1 to 3 The described embodiment changes the value of the VDDQ voltage depending on the speed and on-chip termination settings. In the unterminated mode, by reducing the VDDQ voltage, the output voltage will be limited to the value of VDDQ, thereby saving power by keeping the AC component of the power the same as in the terminated mode. In addition, Figure 3 The NFET driver can work well over a wide range of VDDQ voltage levels.

[0047] According to one embodiment, Figure 4 The use of Figure 3 Flowchart of an example method 400 for transmitting and receiving data in a system. The method 400 begins at block 410, in which a transmitting data interface transmits a data signal to a receiving data interface through a transmission channel.

[0048] Figure 3 An example is shown in FIG. 1 , where data interface 380 is in a transmission mode and data interface 390 is in a reception mode. Data interface 380 transmits data bits on transmission line 320. Data interface 380 includes device 314b to provide a selectable on-chip termination resistor. Device 314b can be turned on for a terminated transmission mode and turned off for an unterminated transmission mode. Assuming the system is in a terminated mode, the on-chip termination device 314b is turned on.

[0049] Transmitting the data signal at block 410 includes applying a high voltage or a low voltage (binary one or binary zero) to the transmission channel 320 for receipt by the data interface 390. For example, turning on the pull-up device 310a applies a binary one, while turning on the pull-down device 312a (while turning off the pull-up device 310a) applies a binary zero. Figure 3 It is not shown, but it is understood that the memory chip 220 includes components for capturing data, such as latch receivers. Therefore, action 410 may also include capturing the data signal on the receiving side.

[0050] Next, in block 420, the system changes from the first data transmission mode to the second data transmission mode. Continuing with this example, the system is in the terminated mode and changes to the unterminated mode, which includes turning off the on-chip termination resistor (device 314b) so that it does not load the line and changing the speed of the transmitted data signal. In the example including LPDDR4, the terminated mode includes a higher data transmission rate than the unterminated mode. However, the scope of the embodiment may include any appropriate data transmission speed for a given mode.

[0051] The determination as to whether to change from the first data transmission mode to the second data transmission mode may be made based on a programming function in the SOC 100 or the memory chip 220. For example, some conventional systems employing LPDDR4 include a high-speed terminated mode and a low-speed unterminated mode, where such conventional systems include a programming algorithm that determines which mode to use. The scope of the embodiments includes using any suitable algorithm now known or later developed to determine to change the transmission mode at block 420.

[0052] In block 430, the system adjusts the operating voltage of the transmit data interface. Figure 3 In the example of FIG. 1 , the power supply 304a receives a control signal from the control circuit 302a instructing it to reduce the voltage it applies to the power rail. In this example, the operating voltage includes a voltage level at VDDQ, where the pull-up and pull-down devices 310a and 312a are set between VDDQ and VSSQ (complementary voltages or ground). At this time, the interface circuits 380, 390 operate in a low speed unterminated mode and a lower second voltage level.

[0053] Next, in block 440, the system changes back to the first data transmission mode. For example, the interface circuits 380, 390 may operate in a low-speed unterminated mode for a period of time until the logic at the SOC 100 or data chip 220 determines that a high-speed terminated operating mode is more appropriate. Therefore, in one example, block 440 includes turning on the on-chip termination resistor (device 314b), and the power supply 304a returns the voltage to the first voltage level in response to the control signal from the control circuit 302a.

[0054] The scope of the embodiments is not limited to Figure 4 The specific method shown in the figure. Other embodiments may add, omit, rearrange or modify one or more actions. For example, in many real-world applications, the actions of blocks 410-440 are not performed in a strict sequence. For example, the data signal transmission of action 410 is performed in both data transmission modes. In addition, in many applications, method 400 is performed continuously while the processor chip and the memory chip transmit data back and forth, and the increase or decrease of activity can correspond to various processing tasks.

[0055] It should also be understood that the above discussion of method 400 also applies when the data chip 220 is in a transmission mode (such as in a read operation) and the SoC 100 is in a receive mode. In this case, the on-chip termination resistor (device 314a) will be turned on during the terminated transmission mode and turned off during the unterminated transmission mode, and the power supply 304b will change the operating voltage of the interface circuit 390 according to the specific terminated or unterminated transmission mode. Moreover, it can be understood that in a system where there are multiple data transmission channels (e.g., 32 or 64), the method 400 will be performed on each transmission channel.

[0056] As those skilled in the art will now appreciate, depending on the specific application at hand, many modifications, substitutions and changes may be made to the materials, devices, configurations and methods of use of the apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments illustrated and described herein, as they are merely examples, and the scope of the present disclosure should be fully commensurate with the scope of the appended claims and their functional equivalents.

Claims

1. A memory interface circuit, comprising: a first transmit and receive data interface in communication with a second transmit and receive data interface via a transmit channel, wherein the second transmit and receive data interface includes a selectable intra-chip termination to ground, the selectable intra-chip termination to ground being configured to be switched on in a first data transmission mode and switched off in a second data transmission mode; as well as a power supply in communication with the first transmit and receive data interface and configured to apply a first voltage level for the first data transmission mode and a second voltage level for the second data transmission mode, wherein the second voltage level is lower than the first voltage level, and wherein a voltage swing of a single-ended transmission line at the second transmit and receive data interface is the same in the first data transmission mode and the second data transmission mode.

2. The memory interface circuit according to claim 1 , further comprising: Another optional on-chip termination to ground is included in the first transmit and receive data interface.

3. The memory interface circuit of claim 1 , wherein the first transmit and receive data interface comprises: Pull-up transistor; A pull-down transistor, wherein the pull-up transistor is coupled between the power supply and the transmission channel, and wherein the pull-down transistor is coupled between the transmission channel and ground.

4. The memory interface circuit of claim 3, wherein the pull-up transistor and the pull-down transistor comprise N-type field effect transistors (NFETs).

5. The memory interface circuit of claim 1, wherein the memory interface circuit is included in a system on a chip (SoC).

6. The memory interface circuit of claim 1, wherein the memory interface circuit is included in a memory chip.

7. The memory interface circuit according to claim 1, wherein the transmission channel comprises a wire for communicating between the system on chip and the memory chip.

8. A system on chip, comprising: a first memory interface configured to perform transmission and reception; A second memory interface communicates with the first memory interface via a transmission line, the second memory interface being configured to perform transmission and reception and having: Pull-up device; a pull-down device, wherein the pull-up device is coupled between a power rail and the transmission line, and wherein the pull-down device is coupled between the transmission line and ground; as well as A power supply configured to provide a first supply voltage to the power rail during a terminated data transmission mode, in which the first memory interface coupled to the transmission line has an on-chip termination to ground, wherein the on-chip termination to ground is coupled to the second memory interface through the transmission line, and wherein the power supply is further configured to provide a second supply voltage to the power rail during an unterminated data transmission mode, in which the on-chip termination does not load the transmission line, the second supply voltage is less than the first supply voltage, and a single-ended voltage swing of the transmission line at the first memory interface is made the same in the unterminated data transmission mode and the terminated data transmission mode.

9. The system of claim 8, wherein the first memory interface comprises a dynamic random access memory (DRAM) interface.

10. The system of claim 9, wherein the DRAM interface comprises a low power fourth generation double data rate (LPDDR4) DRAM interface.

11. The system of claim 8, wherein the power supply comprises a linear dropout voltage regulator.

12. The system of claim 8, wherein the power supply comprises a switch mode power supply.

13. The system of claim 8, wherein the pull-up device and the pull-down device comprise N-type field effect transistors (NFETs).

14. The system of claim 8, wherein the on-chip termination matches a characteristic impedance of the transmission line.

15. The system of claim 8, wherein the first memory interface is included in a system on a chip (SoC).

16. A method for varying voltage based on a terminated or unterminated transmission mode, comprising: transmitting a data signal at a transmit data interface in communication with a transmit channel and a receive data interface, the receive data interface having an on-chip termination to ground, the on-chip termination to ground being configured to be switched on for a first data transmission mode and switched off for a second data transmission mode; changing from the first data transmission mode to the second data transmission mode comprises changing a speed at which the data signal is transmitted; as well as In response to changing from the first data transmission mode to the second data transmission mode, an operating voltage of the transmit data interface is adjusted so that a voltage swing of a single-ended transmission line at the receive data interface is the same in the first data transmission mode and the second data transmission mode.

17. The method according to claim 16, further comprising: A control signal is provided to the power supply of the transmit data interface to adjust the operating voltage.

18. The method of claim 16, wherein changing the speed at which the data signal is transmitted comprises: The speed at which the data signal is transmitted is reduced.

19. The method according to claim 16, further comprising: At the receive data interface, bits of the data signal are captured using a latching receiver.

20. The method of claim 16, wherein the transmit data interface comprises a low power fourth generation double data rate (LPDDR4) dynamic random access memory (DRAM) interface.

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