Method for generating clock signal based on superconducting XOR gate and clock generator

Abstract

A method for generating a clock signal based on a superconducting exclusive-OR gate is provided. The superconducting exclusive-OR gate includes a first input terminal, a second input terminal, a clock terminal, and an output terminal. The method includes: inputting a trigger control signal to the first input terminal and the clock terminal of the exclusive-OR gate; transmitting the data at the output terminal of the exclusive-OR gate to the clock terminal and the second input terminal of the exclusive-OR gate; and outputting the clock signal from the output terminal of the exclusive-OR gate. Wherein, the time when the trigger control signal reaches the clock terminal of the exclusive-OR gate is later than the time when it reaches the first input terminal of the exclusive-OR gate, and the time when the data at the output terminal of the exclusive-OR gate reaches the clock terminal of the exclusive-OR gate is later than the time when it reaches the second input terminal of the exclusive-OR gate.

Description

Technical Field

[0001] The present invention relates to the field of superconducting electronic circuits, and particularly to a method for generating a clock signal based on a superconducting exclusive-OR gate and a clock generator. Background Art

[0002] Currently, the research on superconducting circuits based on Rapid Single Flux Quantum (RSFQ) is still at the level of basic principles and physical manufacturing, and there are not many related inventions in terms of structural design. The advantage of RSFQ circuits lies in their high operating frequency. In the existing RSFQ superconducting circuit designs, the clock signal used to drive the circuit operation is generally externally provided. Due to physical condition limitations, the externally provided clock signal cannot achieve a high-speed frequency above 1 GHz. At the same time, the existing clock generators are formed by the closed-loop of Josephson transmission lines and cannot be stopped once started, so it is impossible to arbitrarily control the start and stop of the clock generator. Summary of the Invention

[0003] According to the above problems of the prior art, the present invention provides a method for generating a clock signal based on a superconducting exclusive-OR gate. The superconducting exclusive-OR gate includes a first input terminal, a second input terminal, a clock terminal, and an output terminal. The method includes:

[0004] Inputting a trigger control signal to the first input terminal and the clock terminal of the exclusive-OR gate;

[0005] Transmitting the data at the output terminal of the exclusive-OR gate to the clock terminal and the second input terminal of the exclusive-OR gate; and

[0006] Outputting the clock signal from the output terminal of the exclusive-OR gate;

[0007] wherein the time when the trigger control signal reaches the clock terminal of the exclusive-OR gate is later than the time when it reaches the first input terminal of the exclusive-OR gate, and

[0008] the time when the data at the output terminal of the exclusive-OR gate reaches the clock terminal of the exclusive-OR gate is later than the time when it reaches the second input terminal of the exclusive-OR gate.

[0009] Preferably, the time when the trigger control signal reaches the clock terminal of the exclusive-OR gate is greater than the time when the trigger control signal reaches the first input terminal of the exclusive-OR gate plus the setup time of the exclusive-OR gate.

[0010] Preferably, the time when the data at the output terminal of the exclusive-OR gate reaches the clock terminal of the exclusive-OR gate is greater than the time when the data at the output terminal of the exclusive-OR gate reaches the second input terminal of the exclusive-OR gate plus the setup time of the exclusive-OR gate.

[0011] Preferably, the first trigger control signal is input to the first input terminal and the clock terminal of the exclusive-OR gate to start outputting the clock signal.

[0012] Preferably, the second trigger control signal is input to the first input terminal and the clock terminal of the exclusive-OR gate to stop outputting the clock signal.

[0013] Preferably, the period of the clock signal is the time for the data at the output terminal of the exclusive-OR gate to reach the clock terminal of the exclusive-OR gate plus the time delay required for the data to be output from the output terminal of the exclusive-OR gate after the clock input is received at the clock terminal of the exclusive-OR gate.

[0014] The present invention also provides a clock generator, which includes:

[0015] A first SPL, which includes an input terminal for receiving a trigger control signal, and a first output terminal and a second output terminal for outputting data;

[0016] A CB, which includes a first input terminal for receiving the trigger control signal from the second output terminal of the first SPL; a second input terminal; and an output terminal for outputting data.

[0017] A superconducting exclusive-OR gate, which includes:

[0018] A first input terminal for receiving the trigger control signal from the first output terminal of the first SPL;

[0019] A second input terminal;

[0020] A clock terminal for receiving the data from the output terminal of the CB; and

[0021] An output terminal for outputting the operation result of the exclusive-OR gate;

[0022] A second SPL, which includes:

[0023] An input terminal for receiving the data from the output terminal of the exclusive-OR gate;

[0024] A first output terminal for outputting the clock signal of the clock generator;

[0025] A second output terminal for outputting data to the second input terminal of the CB; and

[0026] A third output terminal for outputting data to the second input terminal of the exclusive-OR gate,

[0027] wherein the time for the trigger control signal to reach the clock terminal of the exclusive-OR gate is later than the time to reach the first input terminal of the exclusive-OR gate, and

[0028] The time when the data at the output end of the XOR gate reaches the clock end of the XOR gate is later than the time when it reaches the second input end of the XOR gate.

[0029] Preferably, the first SPL is SPL2, the second SPL is SPL3 or the second SPL includes two SPL2s.

[0030] Preferably, the first SPL, the CB, the superconducting XOR gate and the second SPL are connected by Josephson transmission lines.

[0031] Preferably, the time delay from the second output end of the second SPL to the second input end of the CB is greater than the time delay from the third output end of the second SPL to the second input end of the XOR gate.

[0032] The present invention utilizes the existing RSFQ superconducting circuit process to implement a method for generating a clock signal based on a superconducting XOR gate and a controllable superconducting RSFQ clock generator device, which can stably generate a clock pulse signal with a fixed frequency. And the start and stop of the clock generator can be controlled by triggering a control signal. By adjusting the time delay of the Josephson transmission lines inside the clock signal generator, the frequency of the generated clock signal can be adjusted. The controllable clock generator for RSFQ circuits of the present invention has a wide range of application requirements in circuits such as superconducting processors that require high-frequency clock signals. Description of the Drawings

[0033] Figure 1A Schematic diagram of an SPL device in the prior art;

[0034] Figure 1B Schematic diagram of a CB device in the prior art;

[0035] Figure 1C Schematic diagram of an XOR device in the prior art;

[0036] Figure 2 Schematic diagram showing the timing constraints of the clock signal and data signal of the RSFQ superconducting element in the prior art;

[0037] Figure 3 Schematic diagram showing the RSFQ circuit clock generator according to an embodiment of the present invention; and

[0038] Figure 4 Schematic diagram showing the working waveform of the clock generator according to an embodiment of the present invention. Detailed Embodiments

[0039] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below through specific embodiments with reference to the accompanying drawings. It should be noted that the embodiments given in the present invention are only for illustration and do not limit the scope of the present invention.

[0040] In a superconducting RSFQ circuit, the binary information is represented not by the DC voltage in a conventional digital circuit, but by the presence or absence of a data SFQ pulse between two adjacent clock pulses in a superconducting RSFQ digital circuit. The logical values "1" and "0" of the binary information are represented, where 0 represents the state without an SFQ pulse input, and 1 represents the state with an SFQ pulse input.

[0041] The RSFQ circuit clock generator in the present invention includes an existing superconducting element splitter (SPL), a confluence buffer (CB), and an exclusive OR gate (XOR). The following will be combined with Figures 1A - 1C to elaborate on the superconducting elements SPL, CB, and XOR devices in detail.

[0042] Figure 1A FIG. is a schematic diagram of an SPL device in the prior art. The SPL device does not require a clock input. As Figure 1A shown, the SPL device includes an input end in for receiving input data, a first output end out1 and a second output end out2 for outputting data. When a pulse is input to the SPL device, two identical SFQ pulses will be directly output. The SPL device may also include three output ends. When a pulse is input, three identical SFQ pulses will be directly output. In the following, the SPL that can generate two output pulses will be denoted as SPL2, as Figure 1A shown; the SPL that can generate three output pulses will be denoted as SPL3 (not shown in the figure).

[0043] Figure 1B FIG. is a schematic diagram of a CB device in the prior art. It includes a first input end in1 and a second input end in2 for receiving input data, and an output end out for outputting data. Its function is to output the SFQ pulses of the two input ends in1 and in2 from the same output end out. When an SFQ pulse is input to any one of the first input end in1 and the second input end in2, the output end out will output the input SFQ pulse.

[0044] Figure 1CSchematic diagram of an XOR device in the prior art, which includes a first input terminal ina for receiving input data, a second input terminal inb, a clock terminal clk for receiving a clock signal clock, and an output terminal out for data output. Before the arrival of the clock signal clock, if a pulse signal has ever reached the first input terminal ina or the second input terminal inb, its input is considered to be 1. If no pulse signal reaches the first input terminal ina or the second input terminal inb during two arrivals of the clock signal clock, its input is considered to be 0. The XOR device is driven by the clock signal clock. After the arrival of the clock signal clock, the input data of the first input terminal ina and the second input terminal inb are subjected to an exclusive-OR calculation, and the operation result is output via the output terminal out. Table 1 shows the logic truth table of the XOR device of the present invention. It can be seen from Table 1 that when the input data of the first input terminal ina and the second input terminal inb are the same, the output of the output terminal out is 0; when the input data of the first input terminal ina and the second input terminal inb are different, the output of the output terminal out is 1.

[0045] ina inb out 0 0 0 0 1 1 1 0 1 1 1 0

[0046] Table 1 Logic truth table of the XOR device

[0047] Figure 2 Schematic diagram showing the timing constraints of the clock signal and data signal of the RSFQ superconducting element in the prior art. In the actual superconducting circuit design, the RSFQ superconducting element data input signal needs to arrive between two clock signals, and the time interval should meet the requirements for the arrival times of the clock signal and data signal in the corresponding RSFQ superconducting element process library. In the present invention, the working timing requirements for the RSFQ superconducting element are described as follows. For the RSFQ superconducting element that requires clock signal drive, the time t data when the data signal of the superconducting element arrives and the time t c when the clock signal arrives satisfy the following relationship:

[0048] t c +t hold <t data <t c +t cycle -t setup (1)

[0049] wherein, t hold is the buffer time of the superconducting element. After the clock signal arrives to drive the superconducting element to work, the superconducting element needs to buffer for a time t hold before it can process the data. t setupis the setup time of the superconducting element, that is, the shortest time for the superconducting element to read data. If it is less than this time, the input data cannot be input into the superconducting element. t cycle is the period of the clock signal input to the clock terminal of the superconducting element. If the arrival time of t data does not fall at the appropriate position between two clock signals and is too close to the clock pulse signal interval, that is, the time interval from the previous clock signal is less than t hold or the time interval from the next clock signal is less than t setup , it will cause the superconducting element to operate abnormally. Among them, t hold and t setup are specific values determined by the circuit manufacturing process of the superconducting element.

[0050] Figure 3 shows a schematic diagram of an RSFQ circuit clock generator according to an embodiment of the present invention. The clock generator is designed based on the RSFQ circuit, and its input and output signals are both single-flux quantum pulses. Figure 3 The arrows in it are composed of Josephson transmission lines (JTLs). The single-flux quantum pulses are transmitted unidirectionally on the JTLs, and the propagation time is proportional to the path length.

[0051] As Figure 3 shown, the clock generator 300 includes an XOR 301, an SPL 302, an SPL 303, and a CB 304. Among them, the SPL302 includes an input terminal for receiving a trigger control signal, and a first output terminal 11 and a second output terminal 12 for outputting the trigger control signal. The CB 304 includes a first input terminal 21 for receiving the trigger control signal from the second output terminal 12 of the SPL 302; a second input terminal 22 for receiving the data from the second output terminal 32 of the SPL 303; and an output terminal for outputting the data to the clock terminal of the XOR 301. The SPL 303 includes an input terminal for receiving the output data of the XOR 301; a first output terminal 31 for outputting the clock signal of the clock generator 300; a second output terminal 32 for outputting the data to the second input terminal 22 of the CB 304, and a third output terminal 33. The XOR 301 includes a first input terminal ina for receiving the trigger control signal from the first output terminal 11 of the SPL 302; a second input terminal inb for receiving the output data from the third output terminal 33 of the SPL 303; a clock terminal clk for receiving the data from the output terminal of the CB 304; and an output terminal out for outputting the operation result of the XOR301 to the input terminal of the SPL 303.

[0052] For convenience, the input end of SPL 302 is used as the trigger control signal input end of the clock generator 300, and the first output end 31 of SPL 303 is used as the clock signal output end of the clock generator 300. The moment when the trigger control signal arrives at the input end of SPL 302 is defined as t, and the time delays of the pulse signal on each data connection line JTL are respectively defined as a, b, c, d, e, and f. Among them, the time delay a is the time for the pulse signal to be transmitted from the second output end 12 of SPL 302 to the first input end 21 of CB 304; the time delay b is the time for the pulse signal to be transmitted from the output end of CB 304 to the clock terminal clk of XOR 301; the time delay c is the time for the pulse signal to be transmitted from the second output end 32 of SPL 303 to the second input end 22 of CB 304; the time delay d is the time for the pulse signal to be transmitted from the first output end 11 of SPL 302 to the first input end ina of XOR 301; the time delay e is the time for the pulse signal to be transmitted from the output end of XOR 301 to the input end of SPL 303; and the time delay f is the time for the pulse signal to be transmitted from the third output end 33 of SPL 303 to the second input end inb of XOR 301.

[0053] In the present invention, the arrival time of the data input signal and the arrival time of the clock signal of XOR 301 also need to satisfy the above relationship (1), and from relationship (1), it can be obtained that Figure 3 The timing requirements of the signal generator 300 for its JTL connection line in

[0054] a + b > d + t setup (2)

[0055] c + b + e > e + f + t setup (3)

[0056] Among them, t in relationships (2) and (3) setup is the setup time of XOR 301. Relationship (2) makes the time when the trigger control signal arrives at the clock terminal clk of XOR 301 greater than the time when the trigger control signal arrives at the first input end ina of XOR 301 plus the setup time of XOR 301. Relationship (3) makes the time when the data at the output end out of XOR 301 arrives at the clock terminal clk of XOR 301 greater than the time when the data at the output end out of XOR 301 arrives at the second input end inb of XOR 301 plus the setup time of XOR 301. Therefore, when the above relationships are satisfied, the arrival time of the input data of XOR 301 can fall into a suitable position between two clock signals.

[0057] Continue to refer to Figure 3, when it is necessary to start the clock generator 300, the first trigger control signal is input to the input terminal of the SPL 302. After passing through the SPL 302, the first trigger control signal is respectively input to the first input terminal 21 of the CB 304 and the first input terminal ina of the XOR 301. The CB 304 inputs the first trigger control signal to the clock terminal clk of the XOR 301. Due to the above time delay design, the pulse signal reaching the first input terminal ina of the XOR 301 arrives earlier than the clock signal of the XOR 301. At this time, since there is no data output at the output terminal out of the XOR 301, there is no pulse signal input at its second input terminal inb. When the first trigger control signal reaches the clock terminal clk of the XOR 301, the data input state of the XOR 301 is ina = 1, inb = 0. After the calculation of the XOR 301, 1 XOR 0 will output 1, so a first pulse signal will be output at the output terminal out of the XOR 301.

[0058] After passing through the SPL 303, the first pulse signal branches into 3 paths. The first output terminal 31 of the SPL 303 is used to output the first clock signal pulse of the signal generator 300; the second output terminal 32 of the SPL 303 inputs the first pulse signal to the second input terminal 22 of the CB 304 after a time delay c, and the CB 304 inputs the first pulse signal to the clock terminal clk of the XOR 301 after a time delay b; and the third output terminal 33 of the SPL 303 inputs the first pulse signal to the second input terminal inb of the XOR 301 after a time delay f. By designing the time delay of the JTL, when the first pulse signal reaches the clock terminal clk of the XOR 301, there is already data input at the second input terminal inb of the XOR 301. At this time, the data input state of the XOR 301 is ina = 0, inb = 1. After the calculation of the XOR gate, 1 XOR 0 will output 1, so a second pulse signal will be output at the output terminal out of the XOR 301.

[0059] After that, if there is no trigger control signal input at the input terminal of the SPL 302, the XOR 301 enters a loop state, and it continuously generates data at the output terminal out and outputs it to the second input terminal inb and the clock terminal clk of the XOR 301. At this time, the first output terminal 31 of the SPL 303 will continuously output a clock signal with a stable frequency.

[0060] It can be seen from the above analysis that the period T of the clock signal output by the clock generator 300 = b + c + e + t delay , where t delayIt is the time delay required for the clock input received from the clock terminal of XOR 301 to be output as data at the output terminal out of XOR 301. By controlling the time delays c, b, and e of the JTL wiring, output clock signals with different periods T can be obtained.

[0061] Preferably, the time delay c is much greater than f, for example, greater than 2f, 3f, 5f, 10f, 100f, etc.

[0062] Continue to refer to Figure 3 , when it is necessary to stop the clock generator 300, the second trigger control signal is input to the input terminal of SPL 302. The second trigger control signal reaches the first input terminal ina of XOR 301 via SPL 302, and reaches the clock terminal clk of XOR 301 via SPL 302 and CB 304. When the next clock signal reaches the clock terminal clk of XOR 301, the data input state of XOR 301 is ina = 1, inb = 1. After the calculation of XOR 301, 1 XOR 1 will output 0, so no pulse will be output at the output terminal out of XOR 301. Subsequently, if the trigger control signal is no longer input, the clock signal generator 300 stops working.

[0063] Figure 4 shows the working waveform of the clock generator according to an embodiment of the present invention. As Figure 4 shown, the clock generator of the present invention can be controlled by the first trigger control signal to start the clock generator to output a clock signal, and can be controlled by the second trigger control signal to stop the clock generator to stop outputting the clock signal.

[0064] According to the above embodiment of the present invention, SPL 302 is an SPL2 device, and SPL 303 is an SPL3 device. According to other embodiments of the present invention, SPL 303 can also be implemented by two SPL2 devices.

[0065] According to the above embodiment of the present invention, the present invention also provides a method for generating a clock signal based on a superconducting XOR gate, which includes: inputting a trigger control signal to the first input terminal inb and the clock terminal clk of the XOR gate; inputting the data at the output terminal out of the XOR gate to the clock terminal clk and the second input terminal inb of the XOR gate; and outputting the clock signal from the output terminal out of the XOR gate; wherein, the time when the trigger control signal reaches the clock terminal clk of the XOR gate is later than the time when it reaches the first input terminal ina of the XOR gate, and the time when the data at the output terminal out of the XOR gate reaches the clock terminal clk of the XOR gate is later than the time when it reaches the second input terminal inb of the XOR gate.

[0066] The clock generator according to the embodiment of the present invention mainly consists of an exclusive-OR logic gate with a clock terminal and a Josephson transmission line. The generated clock generator has a trigger control signal input terminal and a clock signal output terminal. After a flux pulse is input at the trigger signal input terminal, the clock generator will continuously output a pulsed clock signal with a fixed frequency at the clock signal output terminal. When a flux pulse is input again at the trigger control signal input terminal, the clock signal output terminal stops outputting clock pulses. Therefore, the start and stop of the clock generator of the present invention can be controlled by the trigger control signal, and by adjusting the time delay of the Josephson transmission line inside the clock signal generator, the frequency of the clock signal generation can be adjusted.

[0067] The clock generator and the method for generating a clock signal of the present invention can generate a clock signal inside the circuit to provide a clock signal that can take advantage of the high operating frequency of the RSFQ circuit, and it can achieve a high-speed frequency above 1 GHz.

[0068] Although the present invention has been described through preferred embodiments, the present invention is not limited to the embodiments described herein, and various changes and variations made without departing from the scope of the present invention are also included.

Claims

1. A method for generating a clock signal based on a superconducting XOR gate, the superconducting XOR gate including a first input terminal, a second input terminal, a clock terminal, and an output terminal, the method comprising: Inputting a trigger control signal to the first input terminal and the clock terminal of the XOR gate; Transmitting the data at the output terminal of the XOR gate to the clock terminal and the second input terminal of the XOR gate; and Outputting the clock signal from the output terminal of the XOR gate; Wherein, the time when the trigger control signal reaches the clock terminal of the XOR gate is greater than the time when the trigger control signal reaches the first input terminal of the XOR gate plus the setup time of the XOR gate; The time when the data at the output terminal of the XOR gate reaches the clock terminal of the XOR gate is greater than the time when the data at the output terminal of the XOR gate reaches the second input terminal of the XOR gate plus the setup time of the XOR gate; Inputting a first trigger control signal to the first input terminal and the clock terminal of the XOR gate to start outputting the clock signal; and Inputting a second trigger control signal to the first input terminal and the clock terminal of the XOR gate to stop outputting the clock signal.

2. The method for generating a clock signal based on a superconducting XOR gate according to claim 1, wherein, The period of the clock signal is the time when the data at the output terminal of the XOR gate reaches the clock terminal of the XOR gate plus the time delay required for the data to be output from the output terminal of the XOR gate after the clock input is received at the clock terminal of the XOR gate.

3. A clock generator, the clock generator comprising: A first superconducting element splitter SPL, which includes an input terminal for receiving a trigger control signal, and a first output terminal and a second output terminal for outputting data; A fusion buffer CB, which includes a first input terminal for receiving the trigger control signal from the second output terminal of the first superconducting element splitter SPL; A second input terminal; And an output terminal for outputting data; A superconducting XOR gate, which includes: A first input terminal for receiving the trigger control signal from the first output terminal of the first superconducting element splitter SPL; A second input terminal; A clock terminal for receiving the data from the output terminal of the fusion buffer CB; and An output terminal for outputting the operation result of the XOR gate; A second superconducting element splitter SPL, which includes: An input terminal for receiving the data from the output terminal of the XOR gate; A first output terminal for outputting the clock signal of the clock generator; A second output terminal for outputting data to the second input terminal of the fusion buffer CB; and A third output terminal for outputting data to the second input terminal of the XOR gate; Wherein, the time when the trigger control signal reaches the clock terminal of the XOR gate is greater than the time when the trigger control signal reaches the first input terminal of the XOR gate plus the setup time of the XOR gate; The time when the data at the output terminal of the XOR gate reaches the clock terminal of the XOR gate is greater than the time when the data at the output terminal of the XOR gate reaches the second input terminal of the XOR gate plus the setup time of the XOR gate; Inputting a first trigger control signal to the first input terminal and the clock terminal of the XOR gate to start outputting the clock signal; and Input the second trigger control signal to the first input terminal and the clock terminal of the exclusive OR gate to stop the output of the clock signal.

4. The clock generator according to claim 3, wherein, The first superconducting element splitter SPL is SPL2, the second superconducting element splitter SPL is SPL3, or the second superconducting element splitter SPL includes two SPL2s.

5. The clock generator according to claim 3, wherein, The first superconducting element splitter SPL, the fusion buffer CB, the superconducting exclusive OR gate, and the second superconducting element splitter SPL are connected by Josephson transmission lines.

6. The clock generator according to claim 3, wherein, The time delay from the second output terminal of the second superconducting element splitter SPL to the second input terminal of the fusion buffer CB is greater than the time delay from the third output terminal of the second superconducting element splitter SPL to the second input terminal of the exclusive OR gate.

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