Interposer, semiconductor packaging device and electronic device

Abstract

The embodiments of the present disclosure provide an interposer and a semiconductor packaging device. The interposer includes: a carrier layer; a plurality of metal layers sequentially laid on the carrier layer; and an insulating dielectric layer filled between adjacent metal layers of the plurality of metal layers, wherein a first group of interconnection traces between a first semiconductor chip and a second semiconductor chip is formed by using a conductive pattern of at least one first metal layer of the plurality of metal layers, and a second group of interconnection traces between a first semiconductor chip and a second semiconductor chip is formed by using a conductive pattern of at least one second metal layer of the plurality of metal layers, the first semiconductor chip and the second semiconductor chip are arranged on the interposer, at least one other metal layer is spaced between at least one first metal layer and at least one second metal layer, and at least one of the at least one other metal layer is used as a grounding layer. The interposer provided by the embodiments of the present disclosure achieves effective optimization of electrical performance by performing routing layer layout on a specific metal layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor device preparation, and in particular, to an interposer, a semiconductor packaging device and an electronic device. Background Art

[0002] As the performance requirements for high-performance computing (HPC) chips continue to increase, packaging multiple semiconductor chips (including bare chips) in a single chip has become an important way to achieve small-volume, high-performance chips. Among them, 2.5D packaging and 3D packaging are both popular means to achieve this today. 2.5D packaging technology, also known as interposer technology, mainly places multiple semiconductor chips on top of an interposer and interconnects them through the pins of the chip and the wiring in the interposer.

[0003] Through analysis, it is found that in 2.5D packaging technology, the interposer includes at least one metal layer and a dielectric layer, so one or more metal layers are selected as signal layers, and the wiring area of ​​the signal layer presents a lumped parameter effect (RC effect), so it is necessary to try to reduce resistance and capacitance to improve the electrical performance of the signal layer. However, due to process limitations, the metal layer is thinner and has greater loss, that is, greater resistance, and in order to isolate the electrical signal crosstalk between the two signal layers, a ground layer is placed around the signal layer, which, according to the capacitance principle, leads to a larger capacitance. On this basis, the organization and design of the interposer becomes the key to improving the electrical performance of the signal. Summary of the invention

[0004] In view of this, the present disclosure provides an interposer, a semiconductor packaging device and an electronic apparatus, the purpose of which is to improve the electrical performance of the signal through the organization and design of the interposer.

[0005] In a first aspect, an embodiment of the present disclosure provides an intermediary layer, including:

[0006] Carrier layer;

[0007] A plurality of metal layers sequentially laid on the carrier layer; and

[0008] an insulating dielectric layer filled between adjacent metal layers of the plurality of metal layers,

[0009] A first group of interconnection traces between a first semiconductor chip and a second semiconductor chip is formed by using a conductive pattern of at least one first metal layer of the multiple metal layers, and a second group of interconnection traces between the first semiconductor chip and the second semiconductor chip is formed by using a conductive pattern of at least one second metal layer of the multiple metal layers, the first semiconductor chip and the second semiconductor chip are arranged on the intermediate layer, at least one other metal layer is spaced between the at least one first metal layer and the at least one second metal layer, and at least one of the at least one other metal layer is used as a ground layer.

[0010] In some embodiments, the number of the plurality of metal layers is at least five.

[0011] In some embodiments, when the number of the multiple metal layers is five, the second and fifth metal layers counted upward from the carrier layer are respectively used as the at least one first metal layer and the at least one second metal layer, and the two metal layers between the second and fifth metal layers are both used as ground layers.

[0012] In some embodiments, when the number of the multiple metal layers is five, the second and fifth metal layers counted upward from the carrier layer are used as the at least one first metal layer and the at least one second metal layer, respectively, and the conductive pattern of the third metal layer counted upward from the carrier layer is used to form a third group of interconnection traces between the first semiconductor chip and the second semiconductor chip, and the fourth metal layer counted upward from the carrier layer is used as a ground layer.

[0013] In some embodiments, when the number of the multiple metal layers is five, the first and second metal layers counted upward from the carrier layer are used as the at least one first metal layer, the fourth and fifth metal layers counted upward from the carrier layer are used as the at least one second metal layer, and the third metal layer counted upward from the carrier layer is used as the ground layer.

[0014] In some embodiments, when the number of the multiple metal layers is five, the second and third metal layers counted upward from the carrier layer are used as the at least one first metal layer, the fifth metal layer counted upward from the carrier layer is used as the at least one second metal layer, and the fourth metal layer counted upward from the carrier layer is used as a ground layer.

[0015] In some embodiments, the interposer further includes: a plurality of connection pads for carrying and electrically connecting to signal pins of the first semiconductor chip and the second semiconductor chip, respectively.

[0016] In some embodiments, the insulating dielectric layer is provided with conductive through holes.

[0017] In some embodiments, the first group of interconnection traces and the second group of interconnection traces have the same length.

[0018] In some embodiments, the carrier layer is a silicon layer, or a composite layer consisting of a glass substrate, a metal substrate, a silicon substrate or a ceramic substrate and a passivation layer disposed on the corresponding substrate.

[0019] In a second aspect, an embodiment of the present disclosure provides a semiconductor packaging device, including:

[0020] substrate;

[0021] The above-mentioned interposer is disposed above the substrate;

[0022] the first semiconductor chip and the second semiconductor chip disposed above the interposer,

[0023] The first semiconductor chip and the second semiconductor chip are electrically interconnected via the interposer, and are electrically connected to the substrate via the interposer.

[0024] In some embodiments, the substrate is a BGA package substrate.

[0025] In some embodiments, the first semiconductor chip is a graphics processor, and the second semiconductor chip is a high-performance memory unit.

[0026] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: a semiconductor package device as described in any one of the above; and a printed circuit board for supporting and electrically connecting to the semiconductor package device.

[0027] Based on the existing processing technology, the embodiments of the present disclosure achieve effective optimization of electrical performance by performing routing layer layout of the intermediate layer on a specific metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0029] Figure 1 is a schematic diagram of an electronic device;

[0030] Figure 2a This is a cross-sectional view of two chips integrated into a single package device based on 2.5D packaging technology;

[0031] Figure 2b is with Figure 2a The corresponding top view;

[0032] Figure 2c is a schematic cross-sectional view of a single packaged device mounted on a motherboard based on 2.5D packaging technology;

[0033] Figure 3 is a screenshot of an exemplary interposer;

[0034] Figures 4a to 4d To illustrate the Figure 3 The interposer shown implements four routing designs for interconnection routing between two chips;

[0035] Figure 5 yes Figure 4d A 3D diagram of a portion of the outlet design is provided. DETAILED DESCRIPTION

[0036] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0037] This article uses the following terms.

[0038] Die: Also known as bare chip, bare crystal or wafer, it refers to the chip cut from the wafer without being packaged. Each bare die is an independent chip that has not been packaged and cannot be directly used in actual circuits. Because the bare die is easily affected by the temperature, impurities and physical forces of the external environment and is easily damaged, it needs to be sealed in a closed space and lead out the corresponding pins before it can be used as a basic component.

[0039] Electronic Devices

[0040] Figure 1It is a schematic diagram of an electronic device. As shown in the figure, the electronic device 10 provides a mainboard 1000, and various components are arranged on the mainboard 1000. The mainboard 1000 is, for example, a printed circuit board. The mainboard 1000 carries various components, including but not limited to a processor (CPU) 1002, a graphics processor 1003, a dynamic random access memory 1004, a static random access memory 1010, a flash memory 1006, a GPS chip 1008, and the like. These components are coupled to the mainboard 1000 by physical and electrical means. The mainboard 1000 provides communication functions between various components. In a further embodiment, for example, the functions of some components can be integrated into the processor, for example, the dynamic random access memory 1004 and the static random access memory 1010 can be integrated into a system on a chip and used as the processor 1002 in this embodiment.

[0041] The processor (CPU) comes from a traditional computer system and is a processor that plays a role in overall control and scheduling. It is very effective in logic control, but often lacks in specialization, so it is sometimes integrated with various special acceleration units, such as an acceleration unit dedicated to neural network model calculation, a graphics processor with higher efficiency in graphics processing, etc. In this embodiment, the processor 1002 and the graphics processor 1003 are integrated into the same electronic device 10 through the motherboard 1000.

[0042] The communication chip implements wireless communication to facilitate the transmission of data to and from the electronic device 10. The term "wireless" does not mean that the associated devices do not contain any wires, although in some embodiments they may not contain wires. The communication chip can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. Since there are many different communication protocols, independent communication chips can be constructed based on each communication protocol. For example, the main board 1000 in the figure is provided with a GPS chip 1008 and a Bluetooth chip 1007. In addition, the board 1000 is also provided with some chips dedicated to longer-distance wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc. In addition, other functions, such as video codec, compass, various component drivers, etc., can also form various components and be integrated into the electronic device 10 through the mainboard 1000.

[0043] In addition, the electronic device also includes some components that are not integrated into the device 10 through the mainboard 1000, such as a sound card 1009, a keyboard 1012, a network card 1014, and a mouse 1013. These components provide input and output functions for the device 10.

[0044] The electronic device 10 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 10 is not limited thereto but may be any other electronic device that processes data.

[0045] Semiconductor packaging devices

[0046] Typically, a large number of microelectronic circuits are integrated into semiconductor chips (including bare chips). However, the semiconductor chip itself may not be used as a finished product and may be damaged by external physical or chemical impact. Therefore, the semiconductor chip needs to be used in an electronic device in a packaged state, and such a package is referred to as a semiconductor package device in this article.

[0047] In terms of electrical connection, semiconductor packaging devices are usually used to compensate for the connection between semiconductor chips and motherboards of electronic devices (e.g. Figure 1 Specifically, the size of the signal pins of the semiconductor chip and the spacing between the respective signal pins of the semiconductor chip are very small, while the size of the component mounting parts of the mainboard used in the electronic device and the spacing between the component mounting parts of the mainboard are significantly larger than the size of the signal pins of the semiconductor chip and the spacing between the signal pins of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and generally a packaging technology is required to compensate for the difference in circuit width between the semiconductor chip and the mainboard of the electronic device.

[0048] Semiconductor packaging devices based on various packaging technologies are used for Figure 1 In the electronic device 10 shown in the figure, when used, the semiconductor package device is physically and electrically connected to the mainboard 1000, for example, a semiconductor package device is used as Figure 1 The processor 1002 in the embodiment is physically and electrically connected to the motherboard 1000. For example, a graphics processor and a high-performance storage unit are packaged in a semiconductor package device and physically and electrically connected to the motherboard 1000. Then, the package device can be used as Figure 1 The graphics processor 1003 in.

[0049] As is known to all, the current packaging technology has developed from the traditional 2D packaging technology to 2.5D packaging and 3D packaging. Among them, 2.5D packaging is a packaging technology based on an interposer to interconnect multiple chips. The semiconductor packaging device packaged using the 2.5D packaging technology and the interposer used in the embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0050] Figure 2a This is a cross-sectional view of two chips integrated into a single package device based on 2.5D packaging technology. Figure 2b is with Figure 2a The corresponding top view.

[0051] As shown in the figure, the interposer 103 is arranged on the upper surface of the substrate 101, and the semiconductor chips 105 and 106 are arranged on the upper surface of the interposer 103. The semiconductor chips 105 and 106 are electrically connected to the interposer 103 via signal pins 109 and 111 respectively, and the interposer 103 is electrically connected to the substrate 101 via the connector 110. The figure schematically shows the wiring 102, 104 and 108 for electrical connection inside the interposer 103, wherein the wiring 108 is used for interconnection between the chips 105 and 106, and the wiring 104 and 102 are used to electrically connect the chips 105 and 106 to the connector 110, so as to further electrically connect to the substrate 101. The lower surface of the substrate 101 is provided with BGA solder balls 107 to connect with, for example Figure 1 The component mounting members of the motherboard 1000 are shown to be electrically connected.

[0052] As can be seen from the figure, the chips 105 and 106 can transmit signals indirectly through the substrate 101, or directly through the interconnection lines between the two. Obviously, direct signal transmission through the interconnection lines has lower signal delay. Of course, in certain specific scenarios, if the interconnection lines are subject to more interference from other signals, there may be a higher delay.

[0053] It can also be seen from the figure that there are multiple interconnection lines between chips 105 and 106. In fact, for signal synchronization, the lengths of the interconnection lines should be the same or substantially the same. At the same time, since a shorter length of the interconnection line is helpful for signal transmission, both considerations should be taken into account when determining the length of the interconnection line.

[0054] Figure 2cIt is a schematic cross-sectional view of a single packaged device based on 2.5D packaging technology installed on a mainboard. Since application-specific integrated circuits (ASICs) in semiconductor chips (such as graphics processing units (GPUs)) can be very expensive, it can be very important to package them with a relatively high yield. For this purpose, a BGA substrate 101 with a ball grid array (BGA) can be prepared before installing the semiconductor chip. Next, an interposer 103 is installed on the BGA substrate 101, and then semiconductor chips 105 and 106 are installed on the interposer 103 through surface mounting technology (SMT) and the like and packaged. Finally, the BGA substrate 101 is mounted on the mainboard 201 through solder balls 107 and component mounting parts (i.e., pads) on the mainboard.

[0055] It should be understood that although Figure 2a to Figure 2c The number of chips in the embodiment is 2, but the present disclosure does not limit the number of chips, and the present disclosure also does not limit the types of chips packaged in the same packaged device. For example, the chip located at the center of the upper surface of the intermediate layer is a GPU chip, and high-performance memory units (HBMs) formed by stacking multiple DDR chips are arranged around it. The intermediate layer, GPU chip and high-performance memory unit are packaged together to form a graphics processor with powerful data storage capabilities.

[0056] Figure 3 It is a schematic cross-sectional view of an interposer. As shown in the figure, the interposer 300 includes a carrier layer 301, on which a plurality of metal layers M1 to M5 are sequentially arranged, and insulating dielectrics are filled between adjacent metal layers of the plurality of metal layers M1 to M5 to form insulating dielectric layers D1 to D4. Among them, the metal layer is composed of a conductive pattern depicted based on a metal patterning process, and the insulating dielectric layer fills and covers the conductive pattern of the metal layer. At the same time, the insulating dielectric layers D1 to D4 are provided with conductive through holes V1 to V4, and each conductive through hole realizes conductivity by filling with conductive metal.

[0057] In some cases, the carrier layer 301 is formed of silicon material. In this case, the through hole in the carrier layer 301 for electrical signal extraction is a through silicon via (TSV). However, since the formation of through silicon vias (TSV) may be very difficult and its manufacturing cost may also be quite large, it may not be conducive to increasing the area of ​​semiconductor packages and reducing the manufacturing cost of semiconductor packages. Therefore, in other cases, the carrier layer 301 includes a glass substrate, a metal substrate, a silicon substrate or a ceramic substrate and a passivation layer prepared from an inorganic material or an organic material and arranged on the corresponding substrate. The inorganic material or organic material includes, but is not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), polyimide (PI), polybenzoxazole (PBO) or a combination thereof.

[0058] As shown in the figure, the interposer 300 further includes a plurality of connection pads 302 disposed on the upper surface of the interposer 300 and bumps 311 disposed on the lower surface of the interposer 300. The connection pads 302 are used to carry and electrically connect micro bumps 310, and the bumps 311 are used to electrically connect to the substrate of the packaged device (e.g. Figure 2a to Figure 2c The substrate 101 in the combination Figure 2a As shown, the micro bump 310 is equivalent to Figure 1 The signal pins 109 and 111 of the semiconductor chip in the embodiment of the present invention and the bump 311 have the same function as Figure 2a to Figure 2c The connecting piece 110 in.

[0059] It should be noted that due to the limitations of processing technology and package volume, the stacking structure of the interposer is fixed. For example, the interposer including 5 metal layers shown in this embodiment is a typical current design mode. Therefore, in order to optimize the electrical performance of the interposer, its electrical performance can only be improved from two perspectives, one of which is to reduce resistance (R) and the other is to reduce capacitance (C). In order to reduce the resistance R, adjacent metal layers can be connected together through vias, such as connecting the M5 and M4 layers through vias. In order to reduce the capacitance C, appropriate metal layers can be selected as signal layers and ground layers respectively, so as to achieve the goal of optimizing electrical performance without changing any physical structure.

[0060] Figures 4a to 4d To illustrate the Figure 3 The interposer shown in the figure implements four types of interconnection routing designs between two chips. First of all, it should be noted that Figures 4a to 4d In the figure, the insulating dielectric layers D1 to D4 between the metal layers are represented by symbol 312, 313 represents interconnection wiring, and 314 represents grounding wire.

[0061] refer to Figure 4a As shown, in this design, a portion of the interconnection trace 313 is formed by the conductive patterns of the metal layers M5 and M4 and the conductive vias between the metal layers M5 and M4, and another portion of the interconnection trace 313 is formed by the conductive patterns of the metal layers M1 and M2 and the conductive vias between the metal layers M1 and M2. At the same time, the metal layer M3 is used as a ground layer, and in the metal layers M1 to M4, the conductive patterns other than those used as the interconnection trace 313 can be connected to the ground.

[0062] refer to Figure 4b As shown, in this design, a portion of the interconnection wiring 313 is formed by the conductive pattern of the metal layer M5, and another portion of the interconnection wiring 313 is formed by the conductive patterns of the metal layers M2 and M3 and the conductive vias between the metal layers M2 and M3. At the same time, the metal layer M4 can be used as a grounding layer, and in order to avoid deterioration of electrical performance, the metal layer M1 is used as a dummy metal layer. The dummy metal layer is a metal layer that is arranged in the device but is not electrically connected to the signal line, and thus does not perform any signal transmission. The dummy metal layer is mainly used for purposes such as isolating and protecting the signal line and meeting the copper coverage requirements. In addition, in the metal layers M1 to M4, the conductive patterns other than those used as the interconnection wiring 313 can be connected to the ground.

[0063] refer to Figure 4c As shown, in this design, the interconnection traces 313 are all formed by the conductive patterns of a single metal layer, that is, the conductive patterns of the metal layers M5, M3 and M2 in the figure each form a part of the interconnection traces 313. At the same time, the metal layer M4 is used as a ground layer and the metal layer M1 is used as a dummy metal layer. In addition, in the metal layers M1 to M4, the conductive patterns other than those used as the interconnection traces 313 can be connected to the ground.

[0064] refer to Figure 4d As shown, in this design, the interconnection traces 313 are all formed by the conductive pattern of a single metal layer, that is, the conductive patterns of the metal layers M5 and M2 in the figure each form a part of the interconnection traces 313. At the same time, the metal layers M3 and M4 are used as ground layers, and M1 is used as a dummy metal layer.

[0065] Figure 5 yes Figure 4d A three-dimensional diagram of a portion of the outlet design is provided. It should be noted that only metal layers M5 to M2 are shown in the figure, and the insulating dielectric layer is not shown. Figure 3 and Figure 4d, the micro-bump 310 is a signal pin of the semiconductor chip (for example, chip 105), and there is a connection pad 313 under the micro-bump 310. The connection pad 313 is electrically connected to some routing lines in the conductive pattern of the metal layer M5, and then connected to another connection pad 313 through these routing lines, and then electrically connected to another micro-bump 310. The other micro-bump 310 is, for example, a signal pin of the chip 106. In this way, the interconnection of the two signal pins based on the M5 layer routing between the two chips is completed, and so on. Similarly, routing can be designed in the metal layer M2 layer. For example, a micro-bump 310 of the chip 105 is electrically connected to another micro-bump 310 of the chip 106 through the conductive through-holes on the insulating dielectric layer D2-D4 and the routing of the metal layer M2 layer. In this way, the interconnection of the two signal pins based on the M2 layer routing between the two chips is completed.

[0066] Through simulation experiments, it can be found that Figure 4d The wiring scheme shown has the best electrical performance in the wiring area. Figure 4c Shown next, Figure 4a and Figure 4b The electrical performance of the routing scheme shown is comparable, but slightly worse than the previous two. In summary, in the design of the interposer including 5 metal layers, a metal layer is required as a ground layer between the two metal layers used for interconnect routing design, but it is more preferable to use a metal layer like Figure 4d That way, design the interconnect traces on the second and fifth metal layers and use the two metal layers in between as ground planes.

[0067] It should be pointed out that if the carrier layer uses silicon dielectric, since the silicon material is not an ordinary dielectric layer, but a semiconductor layer with a certain conductivity, this part will deteriorate the electrical performance of the adjacent wiring layer. Therefore, there are two solutions. One is to reduce the conductivity of the silicon layer, and the other is not to wire in the metal layer adjacent to the silicon layer. In addition, if the number of metal layers in the subsequent interposer increases, for example, to 6 layers, 7 layers, or even more, the signal layer and the ground layer can be separated by at least one or two layers to improve the capacitance effect of the signal.

[0068] The commercial value of the disclosed embodiments

[0069] The interposer provided in the embodiment of the present disclosure performs interconnection routing design on a specific metal layer to improve the electrical performance of the signal. The interposer is used for 2.5D packaged devices, so that such devices also have economic value and commercial value.

[0070] It should be understood that the same or similar parts between the various embodiments in this specification can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0071] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0072] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0073] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. An intermediary layer, comprising: Carrier layer; A plurality of metal layers laid sequentially on the carrier layer; as well as an insulating dielectric layer filled between adjacent metal layers of the plurality of metal layers, wherein a first group of interconnection traces between a first semiconductor chip and a second semiconductor chip is formed by using a conductive pattern of at least one first metal layer of the plurality of metal layers, and a second group of interconnection traces between the first semiconductor chip and the second semiconductor chip is formed by using a conductive pattern of at least one second metal layer of the plurality of metal layers, the first semiconductor chip and the second semiconductor chip are arranged on the interposer, at least one other metal layer is spaced between the at least one first metal layer and the at least one second metal layer, and at least one of the at least one other metal layer is used as a ground layer; The number of layers of the multiple metal layers is five, and the second and fifth metal layers counted upward from the carrier layer are respectively used as the at least one first metal layer and the at least one second metal layer, and the conductive pattern of the third metal layer counted upward from the carrier layer is used to form a third group of interconnection traces between the first semiconductor chip and the second semiconductor chip, and the fourth metal layer counted upward from the carrier layer is used as a ground layer, and the first metal layer is used as a dummy metal layer, which does not perform any signal transmission and is used to protect the signal line and meet the copper coating ratio requirements.

2. The interposer according to claim 1, wherein: When the number of the multiple metal layers is five, the second and fifth metal layers counted upward from the carrier layer are respectively used as the at least one first metal layer and the at least one second metal layer, and the two metal layers between the second and fifth metal layers are both used as ground layers.

3. The interposer according to claim 1, wherein: When the number of the multiple metal layers is five, the first and second metal layers counted upward from the carrier layer are used as the at least one first metal layer, the fourth and fifth metal layers counted upward from the carrier layer are used as the at least one second metal layer, and the third metal layer counted upward from the carrier layer is used as the ground layer.

4. The interposer according to claim 1, wherein: When the number of the multiple metal layers is five, the second and third metal layers counted upward from the carrier layer are used as the at least one first metal layer, the fifth metal layer counted upward from the carrier layer is used as the at least one second metal layer, and the fourth metal layer counted upward from the carrier layer is used as the ground layer.

5. The interposer according to claim 1, further comprising: A plurality of connection pads are used to carry and be electrically connected to the signal pins of the first semiconductor chip and the second semiconductor chip respectively.

6. The interposer according to claim 1, wherein: The insulating medium layer is provided with conductive through holes.

7. The interposer according to claim 1, wherein: The first group of interconnection traces and the second group of interconnection traces have the same length.

8. The interposer according to claim 1, wherein: The carrier layer is a silicon layer, or a composite layer consisting of a glass substrate, a metal substrate, a silicon substrate or a ceramic substrate and a passivation layer arranged on the corresponding substrate.

9. A semiconductor packaging device, comprising: substrate; An interposer according to any one of claims 1 to 8 disposed above the substrate; The first semiconductor chip and the second semiconductor chip are arranged above the interposer, wherein the first semiconductor chip and the second semiconductor chip are electrically interconnected via the interposer, and are electrically connected to the substrate via the interposer, and the substrate is a BGA package substrate; The semiconductor package device is mounted on the mainboard by the following method: Mounting the interposer on the BGA package substrate; Mounting the first semiconductor chip and the second semiconductor chip on the interposer by surface mounting technology and packaging them; The BGA package substrate is mounted on the mainboard via solder balls and component mounting members on the mainboard.

10. The semiconductor package device according to claim 9, wherein: The first semiconductor chip is a graphics processor, and the second semiconductor chip is a high-performance storage unit.

11. An electronic device comprising: The semiconductor package device according to any one of claims 9 to 10; And a printed circuit board for supporting and electrically connecting with the semiconductor package device.

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