An array substrate, a testing device thereof, and a display panel

Abstract

An embodiment of the present invention discloses an array substrate, a testing device thereof, and a display panel. The array substrate includes: a substrate; a pixel driving circuit layer disposed on the substrate; the pixel driving circuit layer includes a plurality of pixel driving circuits; a plurality of anode electrodes; the anode electrodes are connected to the output ends of the corresponding pixel driving circuits; a plurality of test pads are disposed on a side of the pixel driving circuit layer away from the substrate; the test pads are connected to the corresponding anode electrodes; the test pads are used to transmit the output current of the pixel driving circuit output by the corresponding anode electrode to the testing device so that the testing device detects the output current. The technical solution provided by the embodiment of the present invention transmits the output current of the pixel driving circuit output by the corresponding anode electrode to the testing device through the provided test pads, realizes electrical testing of the array substrate before component mounting, and solves the problems of resource waste and large parsing difficulty in electrical testing after component mounting in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a testing device thereof, and a display panel. Background Art

[0002] A mini light emitting diode (Mini-LED) panel or a micro light emitting diode (micro-LED) panel is driven by a pixel driving circuit configured one-to-one. That is, each micro-LED / Mini-LED in the panel is driven by the current of the corresponding pixel driving circuit. In the manufacturing process of the above display panel, first, an array substrate provided with a plurality of pixel driving circuits is formed, and then the micro-LED / Mini-LED chips are arranged on the array substrate by a pick-and-place method to complete the connection between the micro-LED / Mini-LED and the corresponding pixel driving circuit.

[0003] However, after the array substrate process is completed and before the pick-and-place process, the display panel cannot be electrically tested, and can only be tested after the pick-and-place process. This causes defective products formed in the array substrate process to flow into the subsequent pick-and-place process, wasting pick-and-place resources and increasing costs. Moreover, when testing is performed after the pick-and-place process, it is impossible to trace whether the problem of the detected defective products occurs in the array substrate process or the pick-and-place process, which affects the analysis of defective products. Summary of the Invention

[0004] Embodiments of the present invention provide an array substrate, a testing device thereof, and a display panel to complete the electrical testing of the array substrate before the pick-and-place process and detect defective array substrates, effectively avoiding the waste of pick-and-place resources.

[0005] In a first aspect, embodiments of the present invention provide an array substrate, including: a substrate;

[0006] A pixel driving circuit layer disposed on the substrate; the pixel driving circuit layer includes a plurality of pixel driving circuits;

[0007] A plurality of anode electrodes; the anode electrodes are connected to the output ends of the corresponding pixel driving circuits;

[0008] A plurality of test pads disposed on a side of the pixel driving circuit layer away from the substrate; the test pads are connected to the corresponding anode electrodes;

[0009] The test pads are used to transmit the output current of the pixel driving circuit output by the corresponding anode electrode to a testing device so that the testing device detects the output current.

[0010] Second aspect, an embodiment of the present invention provides a test device for an array substrate, which is applicable to detecting the array substrate described in any item of the first aspect, and includes: a substrate;

[0011] A plurality of test light-emitting chips are arranged on the substrate; test probes electrically connected to the test light-emitting chips one by one are also arranged on the substrate;

[0012] The test probes are arranged corresponding to the test pads of the array substrate one by one, and are used to output the output current of the pixel driving circuit to the corresponding test light-emitting chips after the pre-process of the array substrate is completed.

[0013] Third aspect, an embodiment of the present invention further provides a display panel, including the array substrate described in any item of the first aspect; the array substrate includes an anode electrode and a cathode electrode arranged in pairs; the display panel further includes:

[0014] A light-emitting chip arranged on the array substrate; the light-emitting chip is electrically connected to the corresponding anode electrode and cathode electrode;

[0015] A packaging layer is arranged on the side of the light-emitting chip away from the array substrate.

[0016] The array substrate provided by the embodiment of the present invention includes a substrate, and a pixel driving circuit layer, a plurality of anode electrodes and a plurality of test pads arranged on the substrate. The anode electrode outputs the output current of the pixel driving circuit. The test pad is connected to the corresponding anode electrode. The test pad can acquire the output current of the pixel driving circuit output by the anode electrode and transmit it to the test device. The test device detects the output current to realize the electrical test of the array substrate before component mounting. In the manufacturing process of the array substrate in this embodiment, the above test pads are formed and the output current of the pixel driving circuit is detected, so as to complete the performance detection of the pixel driving circuit during the manufacturing process of the array substrate, and timely repair or eliminate the array substrate with defective pixel driving circuits found, rather than performing electrical tests after bonding the light-emitting chips, solving the problem of wasting component mounting resources when performing electrical tests after component mounting on the array substrate, and at the same time avoiding the situation where it is difficult to analyze defective problems when performing electrical tests after component mounting on the array substrate. Description of the Drawings

[0017] Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0018] Figure 2 is a circuit element diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0019] Figure 3It is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0020] Figure 4 It is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0021] Figure 5 It is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0022] Figure 6 It is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0023] Figure 7 It is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0024] Figure 8 It is a top view schematic diagram of an array substrate provided by an embodiment of the present invention;

[0025] Figure 9 It is a top view schematic diagram of another array substrate provided by an embodiment of the present invention;

[0026] Figure 10 It is a top view schematic diagram of another array substrate provided by an embodiment of the present invention;

[0027] Figure 11 It is a schematic structural diagram of a test device for an array substrate provided by an embodiment of the present invention;

[0028] Figure 12 It is a schematic structural diagram of another test device for an array substrate provided by an embodiment of the present invention;

[0029] Figure 13 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings, rather than all the structures.

[0031] In the prior art, the manufacturing process of a display panel successively includes an array substrate process, a component mounting process, and a module process. After the array substrate process is completed, electrical testing cannot be directly performed, and the component mounting process will be directly executed. That is, after a light-emitting element is bonded to the anode electrode of the array substrate, electrical testing is carried out. Specifically, whether the driving circuit in the array substrate is normal is judged according to the light-emitting condition of the light-emitting element. However, currently, the component mounting process is often outsourced. After the component mounting process is completed, it is impossible to determine whether the problem lies in the array substrate or in the bonding of the light-emitting element when the brightness of the light-emitting element is abnormal. That is, it is difficult to trace and locate the defective situation, and the analysis of the defective situation is difficult. At the same time, if there is an abnormality in the array substrate, it can only be judged after the light-emitting element is bonded, resulting in waste of component mounting resources and light-emitting elements, and increasing the manufacturing cost.

[0032] Based on the above technical problems, an embodiment of the present invention provides an array substrate, including: a substrate; a pixel driving circuit layer disposed on the substrate; the pixel driving circuit layer includes a plurality of pixel driving circuits; a plurality of anode electrodes; the anode electrodes are connected to the output ends of the corresponding pixel driving circuits; a plurality of test pads are disposed on the side of the pixel driving circuit layer away from the substrate; the test pads are connected to the corresponding anode electrodes; the test pads are used to transmit the output current of the pixel driving circuit output by the corresponding anode electrode to a test device so that the test device detects the output current.

[0033] The array substrate provided by the embodiment of the present invention includes a substrate, and a pixel driving circuit layer, a plurality of anode electrodes, and a plurality of test pads disposed on the substrate. The anode electrodes output the output current of the pixel driving circuit. The test pads are connected to the corresponding anode electrodes. The test pads can obtain the output current of the pixel driving circuit output by the anode electrodes and transmit it to a test device. The test device detects the output current, realizing electrical testing of the array substrate before component mounting. In the manufacturing process of the array substrate in this embodiment, the above test pads are formed, and the output current of the pixel driving circuit is detected, so as to complete the performance detection of the pixel driving circuit in the manufacturing process of the array substrate, and timely repair or eliminate the array substrate with defective pixel driving circuits found, rather than performing electrical testing after the light-emitting chip is bonded, solving the problem of waste of component mounting resources when performing electrical testing after component mounting on the array substrate, and at the same time avoiding the situation of difficult analysis of defective problems when performing electrical testing after component mounting on the array substrate.

[0034] The above is the core idea of the present invention. Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0035] Figure 1It is a schematic structural diagram of an array substrate provided by an embodiment of the present invention. Figure 2 It is a circuit element diagram of a pixel driving circuit provided by an embodiment of the present invention. Refer to Figure 1 and Figure 2 As shown, the array substrate 10 provided by the embodiment of the present invention includes a substrate 100; a pixel driving circuit layer 200 disposed on the substrate 100; the pixel driving circuit layer 200 includes a plurality of pixel driving circuits PC; a plurality of anode electrodes 300; the anode electrodes 300 are connected to the output terminals P of the corresponding pixel driving circuits PC; a plurality of test pads 400 are disposed on a side of the pixel driving circuit layer 200 away from the substrate 100; the test pads 400 are connected to the corresponding anode electrodes 300; the test pads 400 are used to transmit the output current of the pixel driving circuit PC output by the corresponding anode electrode 300 to a test device (not shown in the figure) so that the test device can detect the output current.

[0036] Specifically, the array substrate 10 provided by the embodiment of the present invention includes a pixel driving circuit layer 200 located above the substrate 100. The pixel driving circuit layer 200 includes an insulating layer and a metal layer arranged alternately. Optionally, as Figure 1 shown, it includes a buffer layer 210, an active layer 211, a gate insulating layer 220, a gate layer 221, an inter-metal insulating layer 230, a capacitive metal layer 231, an interlayer insulating layer 240, and a source-drain layer 241. The embodiment of the present invention does not limit the specific interlayer structure in the pixel circuit layer 200. The pixel circuit layer 200 includes a plurality of pixel driving circuits PC. Specifically, those skilled in the art can set the specific implementation manners of the pixel driving circuit PC according to actual situations, which are not limited herein. Exemplarily, the pixel driving circuit PC includes "7T1C", "2T1C", etc., where "T" represents a transistor and "C" represents a capacitor.

[0037] Exemplarily, as Figure 2As shown, the pixel driving circuit PC is a "7T1C" pixel circuit, including a first reset transistor M5, a data writing transistor M2, a driving transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M1, a second light-emitting control transistor M6, a second reset transistor M7, and a storage capacitor Cst. Among them, the first pole of the data writing transistor M2 is electrically connected to the data signal terminal Data, the gates of the data writing transistor M2 and the threshold compensation transistor M4 are both electrically connected to the second scan signal terminal Scan2, the first poles of the first reset transistor M5 and the second reset transistor M7 are both electrically connected to the initialization signal terminal Vref, the gate of the first reset transistor M5 is electrically connected to the first scan signal terminal Scan1, the gate of the second reset transistor M7 is electrically connected to the third scan signal terminal Scan3, the gates of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are both electrically connected to the light-emitting control signal terminal Emit, the first pole of the first light-emitting control transistor M1 is electrically connected to the first level, the first pole of the second light-emitting control transistor M6 is electrically connected to the positive pole of the packaged light-emitting chip L, and the negative pole of the packaged light-emitting chip L is electrically connected to the second level PVEE. Among them, the first pole of the second light-emitting control transistor M6 serves as the output terminal P of the pixel driving circuit PC.

[0038] Exemplarily, the array substrate 10 provided by the embodiment of the present invention includes a plurality of anode electrodes 300 and a plurality of test pads 400. The anode electrodes 300 are connected to the output terminal P of the corresponding pixel driving circuit PC, and the output current of the pixel driving circuit PC can be obtained at the anode electrodes 300. The material of the anode electrodes 300 is a material that can be directly used for the packaging operation, such as copper, to ensure the success rate of the packaging and facilitate the bonding of the light-emitting chip. In addition, the material of the anode electrodes 300 can also be other materials, such as an aluminum-nickel alloy, etc. In order to ensure the success of the packaging on the anode electrodes 300, in this embodiment, a copper layer is coated on the side of the anode electrodes 300 away from the substrate 11, and the packaging is performed on this copper layer. The embodiment of the present invention does not specifically limit the material of the anode electrodes 300.

[0039] Furthermore, as Figure 1 and Figure 2 shown, the pixel driving circuit layer 200 includes a plurality of pixel driving circuits PC, Figure 1 and Figure 2Taking a pixel driving circuit PC as an example for illustration. By setting a test pad 400, the test pad 400 is connected to the anode electrode 300, and the output current of the driving circuit PC is transmitted to the test device through the test pad 400, so as to test the output current of the pixel driving circuit PC, realizing the detection of the output current of the pixel driving circuit without bonding the light-emitting chip L on the anode electrode. By setting a plurality of test pads 400 to detect a plurality of pixel driving circuits PC, the defective points of the array substrate 10 can be effectively detected and the defective rate of the array substrate 10 can be judged.

[0040] In summary, in the process of manufacturing the array substrate in this embodiment, the performance detection of the pixel driving circuit is completed. If it is detected that there is an abnormal output current, it means that there is a defect in the pixel driving circuit, and the array substrate needs to be repaired or eliminated, avoiding the situation where the analysis of defective problems is difficult. Moreover, the electrical test of the pixel driving circuit is completed before component mounting, effectively preventing defective products that already exist in the process of manufacturing the array substrate from flowing into the subsequent component mounting process and module process, avoiding the waste of subsequent resources, and improving the yield of the final display panel.

[0041] Figure 3 It is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. Refer to Figure 1 and Figure 2 As shown, the array substrate 10 provided by the embodiment of the present invention further includes: a first insulating layer 250, disposed on a side of the anode electrode 300 away from the substrate 100; a first metal layer 270, disposed on a side of the first insulating layer 250 away from the substrate 100; a second insulating layer 260, disposed on a side of the first metal layer 270 away from the substrate 100; and a surface of the second insulating layer 260 away from the substrate 100 exposes the anode electrode 300.

[0042] Among them, the array substrate 10 further includes a first insulating layer 250, a first metal layer 270, and a second insulating layer 260. The first insulating layer 250 is located on a side of the anode electrode 300 away from the substrate 100, and the first insulating layer 250 can be a pixel definition layer, and the pixel definition layer can define and expose each anode electrode 300. The first metal layer 270 is located on a side of the first insulating layer 250 away from the substrate 100, and the first metal layer 270 can be a reflective layer, enhancing the reflection effect of the display panel and enabling the routing of double-layer voltage signals. The second insulating layer 260 is located on a side of the first metal layer 270 away from the substrate 100, and the second insulating layer 260 is an interlayer insulating layer in the array substrate 10. In a through-hole form area a on a side of the second insulating layer 260 away from the substrate 100, the corresponding anode electrode 300 is exposed in the area a, and a test pad 400 is provided at the edge, facilitating the implementation of the subsequent component mounting process.

[0043] Continue to refer to Figure 3As shown, the second insulating layer 260 includes at least one of an organic layer 262 and an inorganic layer 261.

[0044] Wherein, as Figure 3 shown, the second insulating layer 260 includes an organic layer 262 and an inorganic layer 261, and the inorganic layer 261 is located on the side of the organic layer 262 away from the substrate 100. By disposing the inorganic layer 261 above the organic layer 262, damage to the array substrate 10 caused by factors such as water or oxygen can be effectively prevented, that is, by disposing the inorganic layer 261, water and oxygen can be prevented from invading the array substrate 10, ensuring the service life of the array substrate 10.

[0045] Exemplarily, as Figure 1 shown, the second insulating layer 260 may only include the organic layer 262 or the second insulating layer 260 may only include the inorganic layer 261. As Figure 2 shown, the second insulating layer 260 may include both the organic layer 262 and the inorganic layer 261 at the same time, and the embodiments of the present invention do not limit the specific interlayer structure of the second insulating layer 260.

[0046] Embodiments of the present invention provide test pads in different forms. Next, one of the test pads will be taken as an example for illustration.

[0047] Continuing to refer to Figure 3 shown, the test pad 400 is disposed on the side of the second insulating layer 260 away from the substrate 100; the test pad 400 includes a bottom portion 410, a top portion 420, and a connecting portion 430; the bottom portion 410 is connected to the corresponding anode electrode 300; the top portion 420 overlaps at least partially with the second insulating layer 260 in a plane parallel to the substrate 100; the connecting portion 430 is used to connect the bottom portion 410 and the top portion 420; the top portion 420 is used to connect to a test device (not shown in the figure).

[0048] Among them, the test pad 400 is located on the side of the second insulating layer 260 away from the substrate 100 and is connected to the anode electrode 300 in area a. The test pad 400 includes a bottom end portion 410, a top end portion 420, and a connecting portion 430. The connection with the exposed anode electrode 300 is achieved through the bottom end portion 410. The top end portion 420 is parallel to the substrate 100 and is located above the second insulating layer 260. The test pad 400 is connected to the test device through the top end portion 420, thereby enabling the test device to perform electrical detection on the array substrate 10. The connecting portion 430 is used to connect the bottom end portion 410 and the top end portion 420. The test pad 400 climbs from the anode electrode 300 to the second insulating layer 260 by providing three parts: the bottom end portion 410, the top end portion 420, and the connecting portion 430, which facilitates the electrical detection of the array substrate 10 by the test device and effectively avoids the problem of poor contact between the test device and the test pad due to the insufficient protrusion of the test pad 400.

[0049] Figure 4 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. Refer to Figures 1 to 4 As shown, the array substrate 10 includes a pre-test process and a post-test process; in the post-test process, a first ink layer 440 is further provided on the side of the test pad 400 away from the substrate 100; the first ink layer 440 covers the top end portion 420 and / or the connecting portion 430 of the test pad 400.

[0050] Specifically, the array substrate 10 includes a pre-test process and a post-test process. As Figure 3 shown, the pre-test process is the process from the buffer layer to the completion of the production of the test pad 400. After the pre-test process is completed, the output current of the pixel driving circuit PC in the array substrate 10 is detected by using the test pad 400. As Figure 4As shown, the post-test process, which is the process of forming the first ink layer 440, should be noted that the post-test process also belongs to the array substrate process and is carried out before the component mounting process. The array substrate 10 is tested by a testing device. After the defective points are checked, the post-test process is executed. Specifically, an insulating substance is provided on the side of the test pad 400 away from the substrate 100 to prevent problems such as short circuits when the metal test pad 400 is exposed to water vapor, etc., to protect the test pad 400. Optionally, in this embodiment, a first ink layer 440 is also provided on the side of the test pad 400 away from the substrate 100. The test pad 400 is a conductive material. By providing an insulating first ink layer 440 on the test pad 400 on the side away from the substrate 100, the test pad 400 is protected from short circuits and other situations. Exemplarily, the first ink layer 440 can cover the top portion 420 and / or the connecting portion 430 of the test pad 400. Preferably, the first ink layer 440 can cover the top portion 420 and the connecting portion 430 of the test pad 400 and extend to cover the second insulating layer 260, as Figure 4 shown, the first ink layer 440 covers the top portion 420 and the connecting portion 430 of the test pad 400, but does not cover the bottom portion 410 of the test pad 400, ensuring that the bottom portion 410 can complete the subsequent component mounting process. It should be noted that the first ink layer 440 also does not cover other anode electrodes and cathode electrodes for bonding light-emitting chips to avoid affecting the subsequent component mounting process.

[0051] Next, another test pad will be used as an example for illustration.

[0052] Figure 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. Refer to Figure 5 shown, the test pad 400 is provided on the same layer as the anode electrode 300; the side of the second insulating layer 260 away from the substrate 100 exposes the test pad 400; a conductive filling material is provided on the side of the test pad 400 away from the substrate 100; the conductive filling material is used to connect to a testing device (not shown in the figure).

[0053] Among them, as Figure 5As shown, a through-hole forming region b is provided in the first insulating layer 250 and the second insulating layer 260 to expose the corresponding anode electrode 300. In this embodiment, the test pad 400 is disposed on the same layer as the anode electrode 300 and is electrically connected to the anode electrode 300. Optionally, the test pad 400 and the anode electrode 300 can be formed as a single entity. In order to facilitate contact with the test pad 400 when the test device tests the array substrate 10, a conductive filling material is filled in the region b in this embodiment, which is equivalent to raising the position of the test pad 400 so that the test pad 400 can protrude to contact the external test device, facilitating the current detection of the pixel driving circuit PC in the array substrate 10. At the same time, through-holes are also provided in the first insulating layer 250 and the second insulating layer 260 to form a region c, so that the anode electrode 300 is exposed on the side of the second insulating layer 260 away from the substrate, facilitating the subsequent component mounting process of the array substrate 10.

[0054] Continue to refer to Figure 5 , optionally, the side of the conductive filling material away from the substrate 100 is higher than the side of the second insulating layer 260 away from the substrate 100.

[0055] Among them, the height of the conductive filling material on the side away from the substrate 100 is H1, and the height of the side of the second insulating layer 260 away from the substrate 100 is H2. Specifically, H1 is greater than H2, that is, the conductive filling material protrudes relative to the second insulating layer 260, ensuring that when the test device performs an electrical test on the array substrate 10, accurate contact with the test pad can be achieved on the premise of not damaging the film layer of the array substrate 10.

[0056] Optionally, the conductive filling material is silver paste. Exemplarily, the conductive filling material provided in the test pad 400 can be silver paste, which is convenient for filling. The conductive filling material can also be other conductive materials, and the specific material of the conductive filling material is not limited in the embodiments of the present invention.

[0057] Figure 6 is a schematic structural diagram of another array substrate provided by the embodiments of the present invention. Refer to Figure 5 and Figure 6 As shown, the array substrate 10 includes a pre-test process and a post-test process; in the post-test process, a second ink layer 450 is further provided on the side of the conductive filling material away from the substrate 100; the second ink layer 450 covers the conductive filling material.

[0058] Specifically, the array substrate 10 includes a pre-test process and a post-test process. As Figure 5 shown, the pre-test process is the process from the buffer layer to the completion of the production of the test pad 400. After the pre-test process is completed, the output current of the pixel driving circuit PC in the array substrate 10 is detected by using the test pad 400 and the conductive filling material above the test pad 400. AsFigure 6 As shown, the post-test process, which is the process of forming the second ink layer 450, should be noted that the post-test process also belongs to the array substrate process and is carried out before the component placement process. The array substrate 10 is tested by a testing device. After the defective pixels are detected, the post-test process is executed. Specifically, an insulating substance is provided on the side of the conductive filling material above the test pad 400 away from the substrate 100 to prevent the problem of short circuit when the metal test pad 400 is exposed to water vapor, etc., to protect the test pad 400. Optionally, in this embodiment, a second ink layer 450 is further provided on the side of the test pad 400 away from the substrate 100, and a conductive filling material is provided above the test pad 400. By providing the insulating second ink layer 450 on the test pad 400 on the side away from the substrate 100, the test pad 400 provided with the conductive filling material is protected from short circuit and other situations. It should be noted that the second ink layer 450 does not cover the anode electrode and cathode electrode for bonding the light-emitting chip either, to avoid affecting the subsequent component placement process.

[0059] Figure 7 FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. The array substrate 10 includes a plurality of pixel regions A; each pixel region A includes at least one pixel driving circuit PC and at least one anode electrode 300; each pixel region A further includes at least one test pad 400; the test pad 400 is used to transmit the output current of the pixel driving circuit PC in the pixel region A where it is located to the testing device.

[0060] Among them, the array substrate 10 includes a plurality of pixel regions A. Each pixel region A includes a pixel driving circuit PC and an anode electrode 300, and the component placement process of the array substrate 10 is realized by bonding a light-emitting chip on the anode electrode 300. By outputting the current of the pixel driving circuit PC, the light-emitting chip on the anode electrode 300 is controlled to emit light. At least one anode electrode 300 can be provided in each pixel region A. By providing a plurality of anode electrodes 300, more light-emitting chips can be bonded, thereby improving the light-emitting brightness of the pixel region A and ensuring a good display effect.

[0061] Exemplarily, the number of pixel regions A included in the array substrate 10 provided by the embodiment of the present invention is not specifically limited. For example, Figure 7 as shown, taking two pixel regions A in the array substrate 10 as an example for illustration, each pixel region A includes one pixel driving circuit PC, one test pad 400 and a plurality of anode electrodes 300 ( Figure 7 the specific number of anode pads 300 is not shown in FIG. 5). Furthermore, by connecting one test pad 400 to any one of the plurality of anode electrodes 300, the detection of the output current of the pixel driving circuit PC in the pixel region A where it is located can be ensured.

[0062] Figure 8 It is a top view schematic diagram of an array substrate provided by an embodiment of the present invention. Figure 9 It is a top view schematic diagram of another array substrate provided by an embodiment of the present invention. Refer to Figures 3 to 9 As shown, each pixel region A includes N anode electrodes 300; N is an integer greater than 1; each pixel region A further includes cathode electrodes 500 corresponding one-to-one to the anode electrodes 300; among the N anode electrodes 300, the cathode electrode 500 corresponding to the i-th anode electrode 300 is connected to the (i + 1)-th anode electrode 300; i is an integer greater than zero and less than N; the test pad 400 provided in the pixel region A is connected to the first anode electrode 300 among the N anode electrodes 300.

[0063] Specifically, in the pixel region A, there are a pixel driving circuit PC, a test pad 400, anode electrodes 300, and cathode electrodes 500, where the cathode electrodes 500 correspond one-to-one to the anode electrodes 300. As Figure 8 shown, the anode electrodes 300 are electrically connected to the pixel driving circuit PC and are used to output the output current of the pixel driving circuit PC. The test pad 400 is connected to the anode electrodes 300, and the test pad 400 transmits the output current to a test device to detect the pixel driving circuit PC. The cathode electrodes 500 are provided at positions corresponding to the anode electrodes 300, that is, there are as many cathode electrodes 500 as there are anode electrodes 300 provided in the pixel region A, and the positions of the cathode electrodes 500 correspond to those of the anode electrodes 300.

[0064] Each pixel region A includes N anode electrodes 300. At the same time, each pixel region A further includes N cathode electrodes 500 corresponding one-to-one to the anode electrodes 300, and N is an integer greater than 1. For example, each pixel region A includes 2 anode electrodes 300 and 2 cathode electrodes 500. Specifically, among the N anode electrodes 300 and the N cathode electrodes 500, the cathode electrode 500 corresponding to the i-th anode electrode 300 is connected to the (i + 1)-th anode electrode 300; where i is an integer greater than zero and less than N. Exemplarily, as Figure 9As shown, the pixel region A includes two anode electrodes 300 and two cathode electrodes 500. The cathode electrode 500 corresponding to the first anode electrode 300 is connected to the second anode electrode 300. By the form of connecting part of the anode electrodes 300 and the cathode electrodes 500, the arrangement of the anode electrodes 300 and the cathode electrodes 500 in the pixel region A is improved to ensure the stable output of the current of the pixel driving circuit PC. And the test pad 400 is connected to the first anode electrode 300 among the N anode electrodes 300 to ensure accurate detection of the pixel driving circuit PC. In the embodiment of the present invention, the number of the anode electrodes 300 and the number of the cathode electrodes 500 are not specifically limited. If multiple pairs of anode electrodes 300 and cathode electrodes 500 are provided in each pixel region, then multiple light-emitting chips can be bound to each pixel region A, so that the light-emitting brightness of each pixel region A is improved. In this embodiment, the multiple light-emitting chips in each pixel region A are connected in series.

[0065] Figure 10 is a top view schematic diagram of another array substrate provided by the embodiment of the present invention. Refer to Figure 10 As shown, each pixel region A includes M of the anode electrodes 300; M is an integer greater than 1; the M anode electrodes 300 in each pixel region A are connected in series; the test pad 400 provided in the pixel region A is connected to one of the M anode electrodes 300.

[0066] Wherein, each pixel region A may further include M anode electrodes 300, and at the same time each pixel region A further includes M cathode electrodes 500 corresponding to the anode electrodes 300 one by one, and M is an integer greater than 1. For example, each pixel region A includes 3 anode electrodes 300 and 3 cathode electrodes 500.

[0067] Specifically, the M anode electrodes 300 in each pixel region A are connected in series, and at the same time the M cathode electrodes 500 are connected in series to ensure the stable output of the current of the pixel driving circuit PC. Exemplarily, as Figure 10 shown, the 3 anode electrodes 300 in each pixel region A are connected in series, and at the same time the M cathode electrodes 500 in the pixel region A are connected in series. The anode electrodes 300 and the cathode electrodes 500 correspond to each other in terms of position and quantity. Further, the test pad 400 provided in the pixel region A is connected to any one of the M anode electrodes 300 to ensure the detection of the output current of the pixel driving circuit PC. Exemplarily, as Figure 10As shown, a test pad 400 provided in a pixel region A is connected to a first anode electrode 300 among the three anode electrodes 300. In the embodiment of the present invention, the number of serially connected anode electrodes 300 and the number of serially connected cathode electrodes 500 are not limited, and at the same time, the position of the anode pad 300 to which the test pad 400 is specifically connected is not limited. Then, multiple light-emitting chips can be bonded to each pixel region A, so that the light-emitting brightness of each pixel region A is improved. In this embodiment, the multiple light-emitting chips in each pixel region A are connected in parallel. When one light-emitting chip in the pixel region is damaged, the other light-emitting chips will continue to work and emit light, improving the quality and reliability of the display panel and effectively extending the life of the display panel.

[0068] Continue to refer to Figure 2 and Figure 3 As shown, the array substrate 10 provided in the embodiment of the present invention further includes a first power supply line (not specifically marked in the figure) and a second power supply line (not specifically marked in the figure) provided on the same layer as the anode electrode 300; the first power supply line is electrically connected to the first level terminal PVDD; the second power supply line is electrically connected to the second level terminal PVEE; the first level is greater than the second level; a third power supply line (not specifically marked in the figure) and a fourth power supply line (not specifically marked in the figure) are provided on the first metal layer 270; the third power supply line is electrically connected to the first power supply line; the fourth power supply line is electrically connected to the second power supply line; the third power supply line at least partially overlaps the first power supply line in a plane parallel to the substrate 100; the fourth power supply line at least partially overlaps the second power supply line in a plane parallel to the substrate 100.

[0069] Among them, the first power supply line and the second power supply line are both provided on the same layer as the anode electrode 300. The first power supply line is electrically connected to the first level terminal PVDD, and the first power supply line is used to receive the electrical signal transmitted by the first level terminal PVDD. The second power supply line is used to receive the electrical signal transmitted by the second level terminal PVEE. Further, the first level is greater than the second level. The electrical signal transmitted by the first level terminal PVDD is transmitted to the anode electrode 300 through the first power supply line, and the electrical signal transmitted by the second level terminal PVEE is transmitted to the cathode electrode 500 through the second power supply line.

[0070] Further, by providing a third power supply line and a fourth power supply line in the first metal layer 270, and electrically connecting the third power supply line to the first power supply line, the signal strength of the first level terminal PVDD transmitted to the anode electrode 300 can be ensured. The fourth power supply line is electrically connected to the second power supply line, which can ensure the signal strength of the second level terminal PVEE transmitted to the cathode electrode 500. Among them, the third power supply line overlaps at least partially with the first power supply line in a plane parallel to the substrate 100, which can reduce the resistance of the power supply line and enhance the signal strength of the first level terminal PVDD transmitted to the anode electrode 300. The fourth power supply line overlaps at least partially with the second power supply line in a plane parallel to the substrate 100, which can reduce the resistance of the power supply line and enhance the signal strength of the second level terminal PVEE transmitted to the cathode electrode 500.

[0071] Based on the same inventive concept, an embodiment of the present invention further provides a test device for an array substrate. Figure 11 FIG. is a schematic structural diagram of a test device for an array substrate provided by an embodiment of the present invention. As Figure 11 shown, the test device 20 for the array substrate is applicable to detecting the array substrate 10 provided by any embodiment of the present invention. The test device 20 includes: a substrate 21; a plurality of test light-emitting chips 22 are provided on the substrate 21; test probes 23 electrically connected to the test light-emitting chips 22 one by one are further provided on the substrate 21; the test probes 23 are arranged in one-to-one correspondence with the test pads 400 of the array substrate 10, and are used to output the output current of the pixel driving circuit PC to the corresponding test light-emitting chips 22 after the pre-process of the array substrate 10 is completed.

[0072] Among them, the test device 20 includes test probes 23, and the test probes 23 are arranged in one-to-one correspondence with the test pads 400. By connecting the test probes 23 to the test pads 400, the output current of the pixel driving circuit PC in the array substrate 10 is introduced into the test device 20, and the test device 20 detects the output current.

[0073] Specifically, the test device 20 further includes a substrate 21 and test light-emitting chips 22. The test light-emitting chips 22 are provided on the substrate 21, and the test light-emitting chips 22 are correspondingly connected to the test probes 23. When the test probes 23 obtain the output current of the pixel driving circuit PC, the test light-emitting chips 22 show brightness. If the test probes 23 do not obtain the output current of the pixel driving circuit PC, the test light-emitting chips 22 do not show brightness. By judging the light-emitting condition of the test light-emitting chips 22 provided on the substrate 21, it is judged whether there is current input to the test pads 400 connected by the test probes 23, and further whether the pixel driving circuit PC in the array substrate 10 connected to the test pads 400 is normal. The test device 20 realizes the detection before the array substrate 10 is assembled by setting the test pads 400.

[0074] In this embodiment, the anode electrode outputs the output current of the pixel driving circuit to the test pad, and the test device obtains the output current of the pixel driving circuit through the test pad. The test device detects the output current to implement the electrical test of the array substrate before component mounting. After the pre-test process of the array substrate is completed in this embodiment, the test probe is inserted into the above-mentioned test pad to detect the output current of the pixel driving circuit, so as to complete the performance detection of the pixel driving circuit during the manufacturing process of the array substrate, and timely repair or eliminate the array substrate with defective pixel driving circuits, rather than performing electrical tests after the light-emitting chips are bonded, thus solving the problem of wasting component mounting resources in the electrical test after component mounting on the array substrate, and at the same time avoiding the difficult situation of analyzing defective problems during the electrical test after component mounting on the array substrate.

[0075] Continue to refer to Figure 11 As shown, the test device 20 provided by the embodiment of the present invention further includes: a support frame 24, and the support frame 24 is arranged on the side of the substrate 21 where the test probe 23 is provided; the support frame 24 is used to support a set gap h between the test device 20 and the array substrate 10 when the test probe 23 is pressed against the test pad 400; the set gap h is greater than or equal to the height of the test probe 23.

[0076] Among them, the test device 20 further includes a support frame 24, and the support frame 24 is located on the side close to the array substrate 10, that is, both the test probe 23 and the test probe 23 are on the same side of the substrate 21. The support frame 24 is used to play a supporting role to realize the stable placement of the test device 20 above the array substrate 10.

[0077] Furthermore, when the test device 20 is placed above the array substrate 10 and the array substrate 10 is tested, the support frame 24 contacts the film layer above the array substrate 10, and at the same time ensures that the test probe 23 is pressed against the test pad 400. In order to prevent the length of the test probe 23 from being too long and generating too much pressure between the test probe 23 and the test pad 400, a set gap h is set between the test device 20 and the array substrate 10. Specifically, as Figure 11 shown, the height of the support frame 24 is the set gap h, the height of the test probe 23 is h1, and the thickness of the test pad 400 close to the test probe 23 and parallel to the substrate 100 side is h2. Among them, h1 < h ≤ h1 + h2 is satisfied, that is, the set gap h is greater than the height of the test probe 23 and less than or equal to the sum of the heights of the test probe 23 and the top part of the test pad 400, ensuring that the test probe 23 contacts the test pad 400 and realizing the electrical test of the test device 20 on the array substrate 10. The embodiment of the present invention does not make specific limitations on the set gap h.

[0078] Figure 12 is a schematic structural diagram of another test device for an array substrate provided by the embodiment of the present invention. Refer toFigure 11 and Figure 12 As shown in Figure 12 , the array substrate 10 includes a plurality of pixel regions A; each pixel region A includes a pixel driving circuit PC, a test pad 400, and at least one anode electrode 300; when the test probe 23 is pressed against the test pad 400, the vertical projection of the test light-emitting chip 22 in the plane where the substrate 100 of the array substrate 10 is located is located in the pixel region A corresponding to the test pad 400.

[0079] Specifically, the array substrate 10 includes a plurality of pixel regions A, and the test device 20 detects each pixel region A. Among them, each pixel region A includes a pixel driving circuit PC, a test pad 400, and at least one anode electrode 300. The test probe 23 of the test device 20 detects the pixel driving circuit PC in each pixel region A through the test pad 400 and the anode electrode 300.

[0080] Furthermore, the test device 20 determines whether the pixel driving circuit PC in each pixel region A is normal by detecting whether the test light-emitting chip 22 emits light. The array substrate 10 includes a plurality of pixel regions A, and the test device 20 includes a plurality of test light-emitting chips 22 and test probes 23. Each test light-emitting chip 22 and test probe 23 corresponds to a pixel region A one by one, which is convenient for analyzing which pixel region A has a problem with the pixel driving circuit PC when the array substrate 10 has a problem. Optionally, as Figure 11 shown, the test light-emitting chip 22 is located on the side of the substrate 21 close to the array substrate. The substrate 21 can be made of a transparent material, which is convenient for more intuitively observing whether there are bad points on the array substrate. Or, as Figure 12 shown, the test light-emitting chip 22 is located on the side of the substrate 21 away from the array substrate. Whether there are bad points on the array substrate can be directly judged by observing the light-emitting situation of the test light-emitting chip 22. Furthermore, by setting the vertical projection of the test light-emitting chip 22 in the plane where the substrate 100 of the array substrate 10 is located in the corresponding pixel region A, since the test light-emitting chip 22 is correspondingly connected to the test pad 400 in the corresponding pixel region A, the corresponding pixel region A can be obtained by observing the abnormal test light-emitting chip 22, and then the abnormal pixel driving circuit PC can be determined. The solution provided in this embodiment can more intuitively check the problem location in the case of an abnormal array substrate 10 and reduce the analysis difficulty.

[0081] Based on the same inventive concept, an embodiment of the present invention further provides a display panel. Figure 13 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. As Figure 9 and Figure 13As shown, the display panel 1 includes the array substrate 10 provided by any embodiment of the present invention. The array substrate 10 includes an anode electrode 300 and a cathode electrode 500 arranged in pairs. The display panel 1 further includes: a light-emitting chip 600 disposed on the array substrate 10; the light-emitting chip 600 is electrically connected to the corresponding anode electrode 300 and cathode electrode 500; and a packaging layer 700 disposed on the side of the light-emitting chip 600 away from the array substrate 10.

[0082] Exemplarily, the display panel 1 includes an array substrate. The array substrate 10 further includes a light-emitting chip 600. The light-emitting chip 600 is driven to emit light by the pixel driving circuit PC in the array substrate 10 to achieve the display effect of the display panel 1. Specifically, the light-emitting chip 600 is respectively connected to the anode electrode 300 and the cathode electrode 500 in the array substrate 10 to ensure the transmission of the driving electrical signal. Further, the display panel 1 further includes a packaging layer 700. The array substrate 10 is packaged by the packaging layer 700 to protect the array substrate 10, thereby ensuring the display effect of the display panel 1.

[0083] This embodiment includes the technical features of the array substrate provided by any embodiment of the present invention and has the beneficial effects corresponding to the technical features, which will not be elaborated here.

[0084] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that, Comprising: A substrate; A pixel driving circuit layer disposed on the substrate; the pixel driving circuit layer includes a plurality of pixel driving circuits; A plurality of anode electrodes; The anode electrode is connected to the output end of the corresponding pixel driving circuit; A plurality of test pads disposed on a side of the pixel driving circuit layer away from the substrate; the test pads are connected to the corresponding anode electrodes; The test pads are used to transmit the output current of the pixel driving circuit output by the corresponding anode electrode to a test device so that the test device can detect the output current; Further comprising: A first insulating layer disposed on a side of the anode electrode away from the substrate; A first metal layer disposed on a side of the first insulating layer away from the substrate; A second insulating layer disposed on a side of the first metal layer away from the substrate; a side of the second insulating layer away from the substrate exposes the anode electrode; The test pads are disposed on a side of the second insulating layer away from the substrate; the test pads include a bottom portion, a top portion, and a connecting portion; the bottom portion is connected to the corresponding anode electrode; the top portion at least partially overlaps with the second insulating layer in a plane parallel to the substrate; the connecting portion is used to connect the bottom portion and the top portion; the top portion is used to connect to the test device; The array substrate includes a pre-test process and a post-test process; in the post-test process, a first ink layer is further disposed on a side of the test pad away from the substrate; the first ink layer covers the top portion and / or the connecting portion of the test pad; the first ink layer does not cover the bottom portion of the test pad, nor does it cover other anode electrodes and cathode electrodes for bonding light-emitting chips.

2. The array substrate according to claim 1, wherein The second insulating layer includes at least one of an organic layer and an inorganic layer.

3. The array substrate according to claim 1, wherein The test pads are disposed on the same layer as the anode electrodes; A side of the second insulating layer away from the substrate exposes the test pads; A conductive filling material is disposed on a side of the test pad away from the substrate; the conductive filling material is used to connect to the test device.

4. The array substrate according to claim 3, wherein A side of the conductive filling material away from the substrate is higher than a side of the second insulating layer away from the substrate.

5. The array substrate according to claim 3, wherein The conductive filling material is silver paste.

6. The array substrate according to claim 3, wherein The array substrate includes a pre-test process and a post-test process; in the post-test process, a second ink layer is further disposed on a side of the conductive filling material away from the substrate; the second ink layer covers the conductive filling material.

7. The array substrate according to claim 1, wherein The array substrate includes a plurality of pixel regions; Each pixel region includes at least one of the pixel driving circuits and at least one of the anode electrodes; Each pixel region further includes at least one of the test pads; the test pads are used to transmit the output current of the pixel driving circuit in the pixel region where they are located to the test device.

8. The array substrate according to claim 7, wherein Each pixel region includes N anode electrodes; N is an integer greater than 1; each pixel region further includes cathode electrodes corresponding to the anode electrodes one by one; Among the N anode electrodes, the cathode electrode corresponding to the i-th anode electrode is connected to the (i + 1)-th anode electrode; i is an integer greater than zero and less than N; The test pad provided in the pixel region is connected to the first anode electrode among the N anode electrodes.

9. The array substrate according to claim 7, wherein Each pixel region includes M anode electrodes; M is an integer greater than 1; the M anode electrodes in each pixel region are connected in series; The test pad provided in the pixel region is connected to one of the M anode electrodes.

10. The array substrate according to claim 1, characterized in that, It further includes a first power supply line and a second power supply line provided on the same layer as the anode electrode; the first power supply line is electrically connected to the first level terminal; the second power supply line is electrically connected to the second level terminal; the first level is greater than the second level; The third power supply line and the fourth power supply line are provided on the first metal layer; the third power supply line is electrically connected to the first power supply line; the fourth power supply line is electrically connected to the second power supply line; The third power supply line overlaps at least partially with the first power supply line in a plane parallel to the substrate; the fourth power supply line overlaps at least partially with the second power supply line in a plane parallel to the substrate.

11. A test device for an array substrate, characterized in that, Suitable for detecting the array substrate according to any one of claims 1-10, including: a substrate; A plurality of test light-emitting chips are provided on the substrate; test probes electrically connected to the test light-emitting chips one by one are also provided on the substrate; The test probes are provided in one-to-one correspondence with the test pads of the array substrate, and are used to output the output current of the pixel driving circuit to the corresponding test light-emitting chips after the pre-process of the array substrate is completed.

12. The test device for the array substrate according to claim 11, wherein It further includes: A support frame, the support frame is provided on the side of the substrate where the test probes are provided; The support frame is used to support a set gap between the test device and the array substrate when the test probes are pressed against the test pads; the set gap is greater than or equal to the height of the test probes.

13. The testing device for the array substrate according to claim 11, wherein, The array substrate includes a plurality of pixel regions; each pixel region includes a pixel driving circuit, a test pad and at least one anode electrode; When the test probes are pressed against the test pads, the vertical projection of the test light-emitting chips in the plane of the substrate of the array substrate is located in the pixel region corresponding to the test pads.

14. A display panel, characterized in that, Including the array substrate according to any one of claims 1-10 above; the array substrate includes paired anode electrodes and cathode electrodes; the display panel further includes: A light-emitting chip provided on the array substrate; the light-emitting chip is electrically connected to the corresponding anode electrode and cathode electrode; A packaging layer provided on the side of the light-emitting chip away from the array substrate.

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