A semiconductor device and a method of fabricating the same

Abstract

The embodiment of the present disclosure provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate and a capacitor arranged on the substrate; the capacitor comprises at least an upper electrode layer, the upper electrode layer extends in multiple planes to define a non-closed accommodation cavity; an upper electrode plate is in contact with the upper electrode layer; the upper electrode plate comprises a silicon germanium layer and a first conductive layer covering the silicon germanium layer; the silicon germanium layer fills the accommodation cavity, and the conductivity of the first conductive layer is greater than that of the silicon germanium layer; and a contact plug is in contact with the upper electrode plate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device and a method for manufacturing the same. BACKGROUND

[0002] A semiconductor device, such as a dynamic random access memory (DRAM), includes a capacitor for storing information, which typically has an upper electrode plate on an upper electrode layer.

[0003] However, the contact resistance between the upper electrode plate and other conductive structures in the prior art is large, which is not conducive to the improvement of the electrical performance of the semiconductor device. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor device, which includes a substrate and a capacitor disposed on the substrate; the capacitor at least includes an upper electrode layer, which extends in multiple planes to define a non-closed accommodation cavity; an upper electrode plate, which is in contact with the upper electrode layer; the upper electrode plate includes a silicon germanium layer and a first conductive layer covering the silicon germanium layer; the silicon germanium layer fills the accommodation cavity, and the electrical conductivity of the first conductive layer is greater than that of the silicon germanium layer; and a contact plug, which is in contact with the upper electrode plate.

[0005] In the above solution, the material of the first conductive layer includes silicon germanium, and the atomic percentage of germanium in the first conductive layer is greater than the atomic percentage of germanium in the silicon germanium layer.

[0006] In the above solution, the atomic percentage of germanium in the silicon germanium layer is 5% to 40%, and the atomic percentage of germanium in the first conductive layer is 60% to 80%.

[0007] In the above solution, the material of the first conductive layer includes n-type doped polysilicon.

[0008] In the above solution, the upper electrode plate further includes a second conductive layer, which is on the first conductive layer, and the electrical conductivity of the second conductive layer is greater than that of the first conductive layer.

[0009] In the above solution, the material of the first conductive layer includes silicon germanium, and the material of the second conductive layer includes n-type doped polysilicon.

[0010] In the above solution, the semiconductor device further includes a dielectric layer covering the upper electrode plate; and the dielectric layer has a contact hole therein, and the contact plug is in the contact hole.

[0011] The contact plug includes an adhesion layer and a conductor layer; the adhesion layer covers the sidewall and bottom surface of the contact hole, and the conductor layer covers the adhesion layer and fills the contact hole.

[0012] The disclosure also provides a method for manufacturing a semiconductor device, the method comprising:

[0013] forming a capacitor on a substrate, the capacitor comprising at least an upper electrode layer extending in multiple planes to define a non-closed accommodation cavity;

[0014] forming an upper electrode plate in contact with the upper electrode layer; the forming of the upper electrode plate comprises forming a silicon germanium layer and a first conductive layer covering the silicon germanium layer; the silicon germanium layer fills the accommodation cavity, and the first conductive layer has a conductivity greater than that of the silicon germanium layer;

[0015] forming a contact plug in contact with the upper electrode plate.

[0016] In the above solution, the material of the first conductive layer comprises silicon germanium, and the atomic percentage of germanium in the first conductive layer is greater than the atomic percentage of germanium in the silicon germanium layer.

[0017] In the above solution, the forming of the silicon germanium layer and the first conductive layer covering the silicon germanium layer comprises: introducing a germanium-containing gas and a silicon-containing gas into a reaction chamber; when forming the silicon germanium layer, the flow rate of the germanium-containing gas is controlled to be between 380 sccm and 440 sccm, and the flow rate of the silicon-containing gas is controlled to be between 100 sccm and 200 sccm; when forming the first conductive layer, the flow rate of the germanium-containing gas is controlled to be between 560 sccm and 680 sccm, and the flow rate of the silicon-containing gas is controlled to be between 100 sccm and 200 sccm.

[0018] In the above solution, the material of the first conductive layer comprises n-type doped polysilicon.

[0019] In the above solution, the upper electrode plate further comprises a second conductive layer; the forming of the upper electrode plate further comprises forming a second conductive layer on the first conductive layer, and the second conductive layer has a conductivity greater than that of the first conductive layer.

[0020] In the above solution, the material of the first conductive layer comprises silicon germanium, and the material of the second conductive layer comprises n-type doped polysilicon.

[0021] In the above solution, before the forming of the contact plug, the method further comprises: forming a dielectric layer on the substrate, the dielectric layer covering the upper electrode plate; etching the dielectric layer to form a contact hole accommodating the contact plug.

[0022] In the scheme, the contact plug comprises an adhesion layer and a conductor layer; the forming of the contact plug comprises: forming an adhesion material layer on the dielectric layer, the adhesion material layer covering the surface of the dielectric layer, the sidewall and the bottom surface of the contact hole;

[0023] forming a conductor material layer on the dielectric layer, the conductor material layer filling the contact hole and being in contact with the adhesion material layer;

[0024] removing the adhesion material layer and the conductor material layer on the dielectric layer by a planarization process to form the adhesion layer and the conductor layer, the adhesion layer and the conductor layer being located in the contact hole and constituting the contact plug.

[0025] The semiconductor device comprises a substrate and a capacitor arranged on the substrate; the capacitor comprises at least an upper electrode layer, the upper electrode layer extending in multiple planes to define a non-closed accommodation cavity; an upper electrode plate is in contact with the upper electrode layer; the upper electrode plate comprises a silicon germanium layer and a first conductive layer covering the silicon germanium layer; the silicon germanium layer fills the accommodation cavity, and the first conductive layer has a greater electrical conductivity than the silicon germanium layer; and a contact plug is in contact with the upper electrode plate. The upper electrode plate is formed by using the silicon germanium layer and the first conductive layer with greater electrical conductivity, so that the electrical conductivity of the upper electrode plate is increased, the contact resistance between the upper electrode plate and the contact plug is reduced, and the electrical performance of the semiconductor device is improved.

[0026] Details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0028] Figure 1 A structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure;

[0029] Figure 2 A flowchart of the preparation method of the semiconductor device provided by the embodiments of the present disclosure;

[0030] Figures 3 to 10 A process flowchart of the preparation method of the semiconductor device provided by the embodiments of the present disclosure;

[0031] Figure 11This is a schematic diagram of a method for fabricating a semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0032] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0033] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0034] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0036] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] A semiconductor device, such as a DRAM, includes a capacitor for storing information, which is a vertical capacitor, and generally includes a lower electrode layer, a dielectric layer, an upper electrode layer, and an upper electrode plate deposited in sequence. The upper electrode plate needs to fill a receiving cavity defined by the upper electrode layer.

[0039] In the related art, a silicon germanium layer is used to form the upper electrode plate, and a contact plug is formed on the upper electrode plate. However, the contact plug has a large contact resistance with the upper electrode plate, which deteriorates the electrical performance of the semiconductor device.

[0040] Based on this, the following technical solutions of the embodiments of the disclosure are proposed:

[0041] The embodiments of the disclosure provide a semiconductor device, including:

[0042] A substrate and a capacitor disposed on the substrate; the capacitor at least includes an upper electrode layer, the upper electrode layer extends in multiple planes and defines a non-closed receiving cavity;

[0043] an upper electrode plate in contact with the upper electrode layer; the upper electrode plate comprises a silicon germanium layer and a first conductive layer covering the silicon germanium layer; the silicon germanium layer fills the accommodation cavity, and the first conductive layer has a conductivity greater than that of the silicon germanium layer;

[0044] a contact plug in contact with the upper electrode plate.

[0045] In the embodiments of the present disclosure, the upper electrode plate is formed by using the silicon germanium layer and the first conductive layer with greater conductivity, so that the conductivity of the upper electrode plate can be increased, the contact resistance between the upper electrode plate and the contact plug can be reduced, and the electrical performance of the semiconductor device can be improved.

[0046] To make the above objectives, characteristics and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure will be described in detail below with reference to the drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

[0047] Figure 1 A structure schematic diagram of a semiconductor device provided by the embodiments of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the semiconductor device comprises a substrate 20 and a capacitor 21 disposed on the substrate 20; the capacitor 21 at least comprises an upper electrode layer 213 extending in multiple planes to define a non-closed accommodation cavity 29; an upper electrode plate 22 in contact with the upper electrode layer 213; the upper electrode plate 22 comprises a silicon germanium layer 223 and a first conductive layer 221 covering the silicon germanium layer 223; the silicon germanium layer 223 fills the accommodation cavity 29, and the first conductive layer 221 has a conductivity greater than that of the silicon germanium layer 223; and a contact plug 24 in contact with the upper electrode plate 22. Figure 1

[0048] The substrate 20 can comprise a plurality of device regions, which can be subsequently separated by cutting; Figure 1 Only one device region is shown in FIG. 1. In one embodiment, the one device region comprises an array region and a peripheral region, the array region is used to form a memory cell, the peripheral region is used to form a peripheral circuit, and the upper electrode plate 22 is located on the array region.

[0049] The substrate 20 can be a silicon substrate, and other structures such as word lines, bit lines, bit line contacts, etc. are also formed in the substrate 20, which will not be described here.

[0050] ​In one embodiment, the semiconductor device further comprises an insulating layer 27 and node contact plugs 25 formed within the insulating layer 27. Specifically, the insulating layer 27 is formed on the substrate 20, and a plurality of spaced-apart node contact plugs 25 are formed within the insulating layer 27 and electrically connected to the capacitor 21.

[0051] The capacitor 21 can include a lower electrode layer 211, a dielectric layer 212, and an upper electrode layer 213. The materials of the lower electrode layer 211 and the upper electrode layer 213 can include one or more conductive materials, such as a doped semiconductor, a conductive metal nitride, a metal, a metal silicide, a conductive oxide, or a combination thereof, for example, titanium nitride, tungsten, tantalum nitride, etc. It can be appreciated that the materials of the lower electrode layer 211 and the upper electrode layer 213 can be the same or different.

[0052] The material of the dielectric layer 212 can include, but is not limited to, a nitride, an oxide, a metal oxide, or a combination thereof. For example, silicon nitride, silicon oxide, etc. In some embodiments, a high-K dielectric material can be used as the material of the dielectric layer 212.

[0053] The semiconductor device further comprises a capacitor support structure 26 that supports the capacitor 21. The capacitor support structure 26 can include a lower support layer 261, a middle support layer 262, and an upper support layer 263. The material of the capacitor support structure 26 can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0054] With continued reference to Figure 1 It can be seen that the lower electrode layer 211 is disposed within the capacitor support structure 26 and in contact with the node contact plugs 25 to form an electrical connection. That is, the capacitor 21 is in contact with the node contact plugs 25 through the lower electrode layer 211.

[0055] In actual practice, the capacitor 21 can be formed using one or more thin film deposition processes, including, but not limited to, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.

[0056] In one embodiment, the material of the first conductive layer 221 includes silicon germanium, and the atomic percentage of germanium in the first conductive layer 221 is greater than the atomic percentage of germanium in the silicon germanium layer 223. The silicon germanium layer 223 needs to fill the accommodation cavity 29, and thus, by using silicon germanium material with a small atomic percentage of germanium, the filling capacity of the silicon germanium material can be improved, and the porosity of the finally formed silicon germanium layer 223 can be greatly reduced. In addition, the first conductive layer 221 needs to be connected with the contact plug 24, and thus, by using silicon germanium material with a large atomic percentage of germanium, the electrical conductivity of the first conductive layer can be improved, and thus, the contact resistance between the upper electrode plate 22 and the contact plug 24 can be reduced.

[0057] In conclusion, by adjusting the atomic percentage of germanium in the upper electrode plate 22, the upper electrode plate 22 can have both good filling capacity and small contact resistance. In some specific embodiments, the atomic percentage of germanium in the silicon germanium layer 223 is 5% to 40%, for example, 10% to 35%, 15% to 30%, or 20% to 25%. The atomic percentage of germanium in the first conductive layer 221 is 60% to 80%, for example, 65% to 75%.

[0058] In another embodiment of the present disclosure, the material of the first conductive layer 221 includes n-type doped polysilicon. The n-type doped polysilicon can be phosphorus (P) doped polysilicon or arsenic (As) doped polysilicon, and the purpose of doping is to improve the electrical conductivity of the polysilicon. Thus, when forming the silicon germanium layer 223, silicon germanium material with a low atomic percentage of germanium can be used to improve the filling capacity, and the porosity of the finally formed silicon germanium layer 223 can be greatly reduced. In this embodiment, the atomic percentage of germanium in the silicon germanium layer 223 can be 5% to 40%, for example, 10% to 35%, 15% to 30%, or 20% to 25%.

[0059] In another embodiment of the present disclosure, the upper electrode plate 22 further comprises a second conductive layer 222, which is located above the first conductive layer 221, and the electrical conductivity of the second conductive layer 222 is greater than that of the first conductive layer 221. In this way, the contact resistance between the upper electrode plate 22 and the contact plug 24 can be further reduced. In a specific embodiment, the material of the first conductive layer 221 comprises silicon germanium, and the material of the second conductive layer 222 comprises n-doped polysilicon. Here, the atomic percentage of germanium in the first conductive layer 221 is 60% to 80%, for example, 65% to 75%. The n-doped polysilicon can be phosphorus (P) doped polysilicon or arsenic (As) doped polysilicon. At this time, the atomic percentage of germanium in the silicon germanium layer 223 is 5% to 40%, for example, 10% to 35%, 15% to 30%, or 20% to 25%. It should be noted that as long as the materials with the above-mentioned relationship of electrical conductivity can be used to form the first conductive layer 221 and the second conductive layer 222.

[0060] Continuing to refer to Figure 1 , the semiconductor device further comprises a dielectric layer 28 covering the upper electrode plate 22, and the dielectric layer 28 has a contact hole TH1 therein, and the contact plug 24 is located in the contact hole TH1. The material of the dielectric layer 28 can include, but is not limited to, silicon oxide, silicon nitride, silicon carbide, etc.

[0061] In an embodiment, the contact plug 24 comprises an adhesion layer 241 and a conductor layer 242, the adhesion layer 241 covers the sidewall and bottom surface of the contact hole TH1, and the conductor layer 242 covers the adhesion layer 241 and fills the contact hole TH1.

[0062] The adhesion layer 241 can comprise a titanium layer, which reacts with silicon in the upper electrode plate 22 to form titanium silicide (TiSi x ), so that the contact plug 24 forms an ohmic contact with the upper electrode plate 22, thereby reducing the contact resistance. The titanium layer can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The thickness of the titanium layer can be between 5 nm and 10 nm, for example, 6 nm. In other embodiments, the adhesion layer 241 can further comprise a titanium nitride layer on the titanium layer, which acts as a diffusion barrier layer and can block the ions in the conductor layer 242 from diffusing into the adhesion layer 241, the dielectric layer 28, and the upper electrode plate 22.

[0063] The material of the conductor layer 242 can be tungsten, but is not limited thereto, and other conductive materials can also be used as the conductor layer 242.

[0064] Optionally, the dielectric layer 28 may further include a conductive plug 23, which can be electrically connected to the peripheral circuit in the peripheral area. The conductive plug 23 may be formed simultaneously with the contact plug 24, and the material of the conductive plug 23 may be the same as that of the contact plug 24, which will not be elaborated here.

[0065] This disclosure also provides a method for fabricating a semiconductor device; please refer to the following for details. Figure 2 As shown in the figure, the method includes the following steps:

[0066] Step 210: Form a capacitor on a substrate, the capacitor including at least an upper electrode layer extending in a plurality of planes to define a non-closed receiving cavity;

[0067] Step 220: Form an upper electrode plate, wherein the upper electrode plate is in contact with the upper electrode layer; the formation of the upper electrode plate includes: forming a silicon-germanium layer and a first conductive layer covering the silicon-germanium layer; the silicon-germanium layer fills the receiving cavity, wherein the conductivity of the first conductive layer is greater than the conductivity of the silicon-germanium layer;

[0068] Step 230: Form a contact plug, which is in contact with the upper electrode plate.

[0069] Below, in conjunction with Figures 3 to 10 The method for fabricating the semiconductor device provided in the embodiments of this disclosure will be described in further detail.

[0070] First, such as Figure 3 As shown, step 210 is performed to form a capacitor 21 on the substrate 20. The capacitor 21 includes at least an upper electrode layer 213 that extends in a plurality of planes and defines a non-closed receiving cavity 29.

[0071] The substrate can be a semiconductor substrate, such as a silicon substrate. Other structures, such as word lines, bit lines, and bit line contacts, are also formed within the substrate, which will not be described in detail here.

[0072] The substrate may contain multiple device regions, which can be subsequently separated by dicing. Figure 3 Only one device area is shown. In one embodiment, the device area includes an array area and a peripheral area, the array area being used to form memory cells and the peripheral area being used to form peripheral circuitry, and the capacitor 21 being formed on the array area.

[0073] In one embodiment, before forming the capacitor 21, the method further includes: forming an insulating layer 27 over the substrate 20; forming a plurality of spaced-apart node contact plugs 25 within the insulating layer 27, wherein the node contact plugs 25 form an electrical connection with the capacitor 21.

[0074] The capacitor 21 may include a lower electrode layer 211, a dielectric layer 212, and an upper electrode layer 213. The materials forming the lower electrode layer 211 and the upper electrode layer 213 may include one or more conductive materials, such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof, for example, titanium nitride, tungsten, tantalum nitride, etc. It is understood that the materials of the lower electrode layer 211 and the upper electrode layer 213 may be the same or different.

[0075] The material of the dielectric layer 212 includes, but is not limited to, nitrides, oxides, metal oxides, or combinations thereof. For example, silicon nitride, silicon oxide, etc. In some embodiments, a high-k dielectric material may be used as the material of the dielectric layer 212.

[0076] In one embodiment, before forming the capacitor 21, the method further includes forming a capacitor support structure 26 on the substrate. The capacitor support structure 26 supports the capacitor 21. The capacitor support structure 26 may include a lower support layer 261, a middle support layer 262, and an upper support layer 263. The material of the capacitor support structure 26 may include, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride.

[0077] Combination Figure 3 As can be seen, the lower electrode layer 211 is disposed within the capacitor support structure 26 and contacts the node contact plug 25 to form an electrical connection. That is, the capacitor 21 contacts the node contact plug 25 through the lower electrode layer 211.

[0078] In actual processes, the first capacitor 21 can be formed using one or more thin film deposition processes; the various thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0079] Next, as Figures 4 to 6 As shown, step 220 is performed to form an upper electrode plate 22, which is in contact with the upper electrode layer 213. Forming the upper electrode plate 22 includes forming a silicon-germanium layer 223 and a first conductive layer 221 covering the silicon-germanium layer 223. The silicon-germanium layer 223 fills the receiving cavity 29, and the conductivity of the first conductive layer 221 is greater than the conductivity of the silicon-germanium layer 223. Using a silicon-germanium layer 223 and a first conductive layer 221 with higher conductivity to form the upper electrode plate 22 can increase the conductivity of the upper electrode plate 22, reduce the contact resistance between the upper electrode plate 22 and the contact plug 24, and improve the electrical performance of the semiconductor device.

[0080] Optionally, the upper electrode plate 22 is formed by: forming an upper electrode plate material layer 22a covering the array region and the peripheral region; and removing the upper electrode plate material layer 22a above the peripheral region to form the upper electrode plate 22 on the array region. Figure 6 As shown in FIG. 2B, the upper electrode plate material layer 22a is removed above the peripheral region to form the upper electrode plate 22 on the array region. It can be understood that, when the upper electrode plate material layer 22a is removed above the peripheral region, if the dielectric layer 212 and the upper electrode layer 213 are formed on the peripheral region, the dielectric layer 212 and the upper electrode layer 213 on the peripheral region should also be removed.

[0081] It should be noted that, when the substrate includes a plurality of device regions, the lower electrode layer, the dielectric layer, the upper electrode layer and the upper electrode plate material layer can be sequentially formed on the plurality of device regions at the same time, and then the dielectric layer, the upper electrode layer and the upper electrode plate material layer on the peripheral region in each device region are removed to form the capacitor and the upper electrode plate corresponding to the plurality of device regions.

[0082] More specifically, the method for forming the upper electrode plate material layer 22a includes: depositing a silicon germanium material layer 223a in the non-closed accommodation cavity 29, as shown in FIG. 2A; and then depositing a first conductive material layer 221a above the silicon germanium material layer 223a, the first conductive material layer 221a having a conductivity greater than that of the silicon germanium material layer 223a, as shown in FIG. 2B. Figure 4 Figure 5

[0083] ​​In one embodiment, the material of the first conductive layer 221 includes silicon germanium, and the atomic percentage of germanium in the first conductive layer 221 is greater than the atomic percentage of germanium in the silicon germanium layer 223. The silicon germanium layer 223 needs to fill the accommodation cavity 29, and using silicon germanium material with a smaller atomic percentage of germanium can improve the filling capacity of the silicon germanium material, so that the porosity of the finally formed silicon germanium layer 223 is greatly reduced. In addition, the first conductive layer 221 needs to be connected with the contact plug 24, and using silicon germanium material with a greater atomic percentage of germanium can improve the conductivity of the first conductive layer, thereby reducing the contact resistance between the upper electrode plate 22 and the contact plug 24. In actual processes, the silicon germanium layer 223 and the first conductive layer 221 can be formed in the same process or in different processes. In one embodiment, chemical vapor deposition (CVD) is used to form the silicon germanium layer 223 and the first conductive layer 221. Specifically, germanium-containing gas (such as GeH4) and silicon-containing gas (such as SiH4) are introduced into the reaction chamber, and by controlling the flow rates of the germanium-containing gas and / or the silicon-containing gas, the atomic percentage of germanium in the formed silicon germanium layer 223 and the first conductive layer 221 can be controlled. In a specific embodiment, when forming the silicon germanium layer 223, the flow rate of the germanium-containing gas is controlled to be between 380 sccm and 440 sccm, and the flow rate of the silicon-containing gas is controlled to be between 100 sccm and 200 sccm; when forming the first conductive layer 221, the flow rate of the germanium-containing gas is controlled to be between 560 sccm and 680 sccm, and the flow rate of the silicon-containing gas is controlled to be between 100 sccm and 200 sccm. In this way, the atomic percentage of germanium in the first conductive layer 221 can be greater than the atomic percentage of germanium in the silicon germanium layer 223. Optionally, when forming the silicon germanium layer 223 and the first conductive layer 221, a doping gas (such as BCl3) can also be introduced into the reaction chamber, and the flow rate of the doping gas is between 10 sccm and 30 sccm.

[0084] In summary, by adjusting the atomic percentage of germanium in the upper electrode plate 22, the upper electrode plate 22 can have both good filling capacity and small contact resistance. In some specific embodiments, the atomic percentage of germanium in the silicon germanium layer 223 is 5% to 40%, for example, 10% to 35%, 15% to 30%, or 20% to 25%. The atomic percentage of germanium in the first conductive layer 221 is 60% to 80%, for example, 65% to 75%.

[0085] In another embodiment of the present disclosure, the material of the first conductive layer 221 comprises n-doped polysilicon. The n-doped polysilicon can be phosphorus (P) doped polysilicon or arsenic (As) doped polysilicon, and the purpose of the doping is to increase the conductivity of the polysilicon. Thus, when forming the silicon germanium layer 223, a silicon germanium material with a low atomic percentage of germanium can be used to improve the filling ability, so that the porosity of the finally formed silicon germanium layer 223 is greatly reduced. In this embodiment, the atomic percentage of germanium in the silicon germanium layer 223 can be 5% to 40%, for example, 10% to 35%, 15% to 30%, or 20% to 25%.

[0086] In another embodiment of the present disclosure, as shown in Figure 11 The upper electrode plate 22 further comprises a second conductive layer 222, and the forming of the upper electrode plate 22 further comprises forming the second conductive layer 222 on the first conductive layer 221, and the second conductive layer 222 covers the first conductive layer 221. The conductivity of the second conductive layer 222 is greater than the conductivity of the first conductive layer 221. Thus, the contact resistance between the upper electrode plate 22 and the contact plug 24 can be further reduced.

[0087] In a specific embodiment, the material of the first conductive layer 221 comprises silicon germanium, and the material of the second conductive layer 222 comprises n-doped polysilicon. Here, the atomic percentage of germanium in the first conductive layer 221 is 60% to 80%, for example, 65% to 75%. The n-doped polysilicon can be phosphorus (P) doped polysilicon or arsenic (As) doped polysilicon. At this time, the atomic percentage of germanium in the silicon germanium layer 223 is 5% to 40%, for example, 10% to 35%, 15% to 30%, or 20% to 25%. It should be noted that as long as the material has the above-mentioned relationship of conductivity, it can be used to form the first conductive layer 221 and the second conductive layer 222.

[0088] Finally, as shown in Figures 7 to 10 Step 230 is performed: forming a contact plug 24, which is in contact with the upper electrode plate 22.

[0089] Specifically, the contact plug 24 is formed on the upper electrode plate 22 and is in contact with the top layer of the upper electrode plate 22, such as the first conductive layer 221 or the second conductive layer 222.

[0090] It can be understood that before forming the contact plug 24, the method further comprises: forming a dielectric layer 28 on the substrate 20, the dielectric layer 28 covering the upper electrode plate 22, as shown in Figure 7 Etching the dielectric layer 28 to form a contact hole TH1 accommodating the contact plug, as shown in Figure 8The material forming the dielectric layer 28 includes, but is not limited to, silicon oxide, silicon nitride, silicon carbide, etc.

[0091] In some embodiments, the contact plug 24 includes an adhesion layer 241 and a conductor layer 242. The forming of the contact plug 24 includes: forming an adhesion material layer 241a on the dielectric layer 28, the adhesion material layer 241a covering the surface of the dielectric layer 28, the sidewall and the bottom surface of the contact hole TH1.

[0092] forming a conductor material layer 242a on the dielectric layer 28, the conductor material layer 242a filling the contact hole TH1 and contacting the adhesion material layer 241a, for details, please refer to Figure 9 ;

[0093] The adhesion material layer 241a and the conductor material layer 242a on the dielectric layer are removed by a planarization process to form the adhesion layer 241 and the conductor layer 242, which are located in the contact hole TH1 and constitute the contact plug 24, as shown in Figure 10 .

[0094] The adhesion layer 241 can include a titanium layer, which reacts with silicon in the upper electrode plate 22 to form titanium silicide (TiSi x ), so that the contact plug 24 forms an ohmic contact with the upper electrode plate 22, reducing the contact resistance. The titanium layer can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The thickness of the titanium layer can be between 5 nm and 10 nm, for example, 6 nm. In other embodiments, the adhesion layer 241 can also include a titanium nitride layer on the titanium layer, which acts as a diffusion barrier layer and can block the diffusion of ions in the conductor layer 242 into the adhesion layer 241, the dielectric layer 28 and the upper electrode plate 22.

[0095] The material of the conductor layer 242 can be tungsten, but is not limited to this, other conductive materials can also be used as the conductor layer 242.

[0096] Optionally, in the process of forming the contact plug 24, a conductive plug 23 can also be formed in the dielectric layer 28, which can be electrically connected with the peripheral circuit in the peripheral area. The material of the conductive plug 23 can be the same as that of the contact plug 24, which is not described here.

[0097] It should be noted that the preparation method of the semiconductor device provided by the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited here. The embodiments of the semiconductor device preparation method provided by the present disclosure belong to the same concept as the embodiments of the semiconductor device. In the technical solutions described in each embodiment, the technical features are not in conflict and can be combined arbitrarily.

[0098] The above merely describes preferred embodiments of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate and a capacitor disposed on the substrate; the capacitor includes at least an upper electrode layer extending in a plurality of planes to define a non-closed receiving cavity; An upper electrode plate is in contact with the upper electrode layer; the upper electrode plate includes a silicon-germanium layer and a first conductive layer covering the silicon-germanium layer; the silicon-germanium layer fills the receiving cavity, and the conductivity of the first conductive layer is greater than that of the silicon-germanium layer; The contact plug is connected to the upper electrode plate. The material of the first conductive layer includes silicon germanium, and the atomic percentage of germanium in the first conductive layer is greater than the atomic percentage of germanium in the silicon germanium layer.

2. The semiconductor device according to claim 1, characterized in that, The silicon-germanium layer contains 5% to 40% germanium atoms, and the first conductive layer contains 60% to 80% germanium atoms.

3. The semiconductor device according to claim 1, characterized in that, The material of the first conductive layer includes n-type doped polycrystalline silicon.

4. The semiconductor device according to claim 1, characterized in that, The upper electrode plate further includes a second conductive layer, which is located on the first conductive layer, and the conductivity of the second conductive layer is greater than that of the first conductive layer.

5. The semiconductor device according to claim 4, characterized in that, The first conductive layer is made of silicon germanium, and the second conductive layer is made of n-type doped polycrystalline silicon.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: a dielectric layer covering the upper electrode plate; the dielectric layer having a contact hole, and the contact plug located within the contact hole.

7. The semiconductor device according to claim 6, characterized in that, The contact plug includes an adhesive layer and a conductor layer; the adhesive layer covers the sidewalls and bottom surface of the contact hole, and the conductor layer covers the adhesive layer and fills the contact hole.

8. A method for fabricating a semiconductor device, characterized in that, The method includes: A capacitor is formed on a substrate, the capacitor including at least an upper electrode layer extending in a plurality of planes to define a non-closed receiving cavity; An upper electrode plate is formed, which is in contact with the upper electrode layer; the formation of the upper electrode plate includes: forming a silicon-germanium layer and a first conductive layer covering the silicon-germanium layer; the silicon-germanium layer fills the receiving cavity, and the conductivity of the first conductive layer is greater than the conductivity of the silicon-germanium layer; A contact plug is formed, and the contact plug is in contact with the upper electrode plate; The material of the first conductive layer includes silicon germanium, and the atomic percentage of germanium in the first conductive layer is greater than the atomic percentage of germanium in the silicon germanium layer.

9. The method according to claim 8, characterized in that, Forming a silicon-germanium layer and a first conductive layer covering the silicon-germanium layer includes: introducing a germanium-containing gas and a silicon-containing gas into a reaction chamber; during the formation of the silicon-germanium layer, controlling the flow rate of the germanium-containing gas to be between 380 sccm and 440 sccm, and the flow rate of the silicon-containing gas to be between 100 sccm and 200 sccm; during the formation of the first conductive layer, controlling the flow rate of the germanium-containing gas to be between 560 sccm and 680 sccm, and the flow rate of the silicon-containing gas to be between 100 sccm and 200 sccm.

10. The method according to claim 8, characterized in that, The material of the first conductive layer includes n-type doped polycrystalline silicon.

11. The method according to claim 8, characterized in that, The upper electrode plate further includes a second conductive layer; forming the upper electrode plate further includes forming a second conductive layer on the first conductive layer, wherein the conductivity of the second conductive layer is greater than that of the first conductive layer.

12. The method according to claim 11, characterized in that, The first conductive layer is made of silicon germanium, and the second conductive layer is made of n-type doped polycrystalline silicon.

13. The method according to claim 8, characterized in that, Before forming the contact plug, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the upper electrode plate; and etching the dielectric layer to form a contact hole for accommodating the contact plug.

14. The method according to claim 13, characterized in that, The contact plug includes an adhesive layer and a conductor layer; forming the contact plug includes: forming an adhesive material layer on the dielectric layer, the adhesive material layer covering the surface of the dielectric layer, the sidewalls of the contact hole and the bottom surface; A conductor material layer is formed on the dielectric layer, the conductor material layer filling the contact hole and contacting the adhesive material layer; An adhesive material layer and a conductor material layer on the dielectric layer are removed using a planarization process to form an adhesive layer and a conductor layer. The adhesive layer and the conductor layer are located within the contact hole, forming the contact plug.

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