Circuit and method of operation thereof

Abstract

This disclosure generally relates to circuits and methods of operation thereof. One circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to provide a first supply voltage, a second supply voltage, and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit and is in either the first state or the second state at least in response to the first supply voltage provided by the power management circuit.

Description

Technical Field

[0001] This disclosure generally relates to circuits and their operating methods. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to solve problems in many different fields. Some of these digital devices (such as level shifter circuits) are configured to enable circuit operation in different voltage domains. As ICs become smaller and more complex, the operating voltage of these digital devices continues to decrease, affecting IC performance. Summary of the Invention

[0003] According to a first aspect of this disclosure, a provider offers a circuit comprising: a power management circuit configured to receive a first control signal and a second control signal, and to provide a first supply voltage, a second supply voltage, and a third supply voltage, the first control signal having a first voltage swing, and the second control signal having a second voltage swing different from the first voltage swing, the first control signal causing the power management circuit to enter a power management mode having a first state and a second state; and a memory circuit coupled to the power management circuit and being in either the first state or the second state at least in response to the first supply voltage provided by the power management circuit.

[0004] According to a second aspect of this disclosure, a circuit is provided, comprising: a power control circuit coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage, the power control circuit being configured to generate a first output control signal, a second output control signal, and a third output control signal in response to at least a first control signal, a second control signal, or a third control signal, wherein at least the first voltage or the first control signal has a first voltage swing, and at least the second voltage, the second control signal, or the third control signal has a second voltage swing different from the first voltage swing, the first control signal causing the power control circuit to enter a power management mode having a first power reduction state and a second power reduction state; and a first head circuit coupled to the power control circuit and configured to provide at least a first supply voltage, a second supply voltage, or a third supply voltage in response to at least the first output control signal, the second output control signal, or the third output control signal, wherein the power management mode includes the second voltage supply being turned off.

[0005] According to a third aspect of this disclosure, a method of operating a circuit is provided, the method comprising: receiving at least a first control signal, a second control signal, or a third control signal by a power control circuit, the power control circuit being coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage; generating a first output control signal, a second output control signal, and a third output control signal by the power control circuit in response at least to the first control signal, the second control signal, or the third control signal, wherein at least the first voltage or the first control signal has a first voltage swing, and at least the second voltage, the second control signal, or the third control signal has a second voltage swing different from the first voltage swing; and from a head The circuit provides at least a first supply voltage, a second supply voltage, or a third supply voltage in response to at least the first output control signal, the second output control signal, or the third output control signal; the power control circuit enters a power management mode in response to a first value of the first control signal, the power management mode having a first power reduction state and a second power reduction state, wherein entering the power management mode includes: shutting off the second voltage supply; and causing the memory circuit to be in the first power reduction state or the second power reduction state in response to at least the first supply voltage or the first control signal, the memory circuit being coupled to the power control circuit and the head circuit. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram of an integrated circuit according to some embodiments.

[0008] Figure 2 This is a circuit diagram of a circuit according to some embodiments.

[0009] Figure 3 According to some embodiments Figure 1 or Figure 2 The truth table of the circuit in the diagram.

[0010] Figures 4A-4E These are waveform diagrams of circuits according to some embodiments.

[0011] Figure 5 This is a circuit diagram of the output circuit according to some embodiments.

[0012] Figure 6 This is a circuit diagram of a circuit according to some embodiments.

[0013] Figures 7A-7B These are waveform diagrams of circuits according to some embodiments.

[0014] Figure 8 This is a circuit diagram of a circuit according to some embodiments.

[0015] Figure 9 According to some embodiments Figure 1 or Figure 8 The truth table of the circuit in the diagram.

[0016] Figures 10A-10B These are waveform diagrams of circuits according to some embodiments.

[0017] Figure 11 This is a circuit diagram of a level shifter circuit according to some embodiments.

[0018] Figure 12 This is a circuit diagram of a circuit according to some embodiments.

[0019] Figure 13 This is a flowchart of a method for operating circuits according to some embodiments. Detailed Implementation

[0020] The following disclosure provides various embodiments or examples of features for implementing the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. These are, of course, merely examples and not limiting. Other components, materials, values, steps, arrangements, etc., are contemplated. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0022] According to some embodiments, a circuit includes a power control circuit coupled to a first voltage source having a first voltage and a second voltage source having a second voltage. In some embodiments, the power control circuit is configured to generate a first output control signal, a second output control signal, and a third output control signal in response to at least a first control signal, a second control signal, or a third control signal. In some embodiments, the first control signal causes the power control circuit to enter a power management mode having a first power reduction state and a second power reduction state.

[0023] In some embodiments, the circuit further includes a first header circuit coupled to the power control circuit and configured to supply at least a first supply voltage, a second supply voltage, or a third supply voltage in response to at least a first output control signal, a second output control signal, or a third output control signal. In some embodiments, the power management mode includes disabling or turning off the second voltage source. In some embodiments, the power control circuit and the first header circuit are part of the power management circuit.

[0024] In some embodiments, the circuit further includes a memory circuit coupled to the power control circuit and the first header circuit. In some embodiments, the memory circuit is in a first reduced power state or a second reduced power state at least in response to a first supply voltage or the power control circuit entering a power management mode. In some embodiments, the first reduced power state corresponds to a sleep mode of the memory circuit, and the second reduced power state corresponds to a shutdown mode of the memory circuit.

[0025] In some embodiments, at least a first voltage or a first control signal has a first voltage swing, and at least a second voltage, a second control signal, or a third control signal has a second voltage swing that is different from the first voltage swing, allowing the circuit to have a dual-rail design and / or implementation.

[0026] In some embodiments, the circuit can automatically enter a power management mode by using a first control signal, thereby reducing power consumption and allowing for a more flexible design compared to other methods.

[0027] In some embodiments, the circuit can enter power management mode even when the power management mode includes the second voltage source being disabled or turned off, resulting in less power consumption and more flexible design compared to other methods.

[0028] integrated circuit

[0029] Figure 1 This is a block diagram of an integrated circuit 100 according to some embodiments.

[0030] Integrated circuit 100 includes power management circuit 102, memory circuit 104 and output circuit 105.

[0031] The power management circuit 102 is configured to receive control signals PISO, SDB, and SLPB, and generate voltages VDDAI, VDDMH, and VDDH.

[0032] In some embodiments, the power management circuit 102 is coupled to a first voltage supply node N1 and a second voltage supply node N2. In some embodiments, the first voltage supply node N1 has a first supply voltage VDD1 and is therefore referred to as being in the VDD voltage domain. In some embodiments, the first supply voltage VDD1 has a first voltage swing. In some embodiments, one or more of the control signals SDB or SLPB have the first voltage swing. In some embodiments, the voltage VDDH has the first voltage swing.

[0033] In some embodiments, the second voltage supply node N2 has a second supply voltage VDDM1 and is therefore referred to as being in the VDDM voltage domain. In some embodiments, the second supply voltage VDDM1 has a second voltage swing that is different from the first voltage swing.

[0034] In some embodiments, the control signal PISO has a second voltage swing. In some embodiments, at least the voltage VDDAI or VDDMH has a second voltage swing.

[0035] Power management circuitry 102 is configured to control the operating mode of memory circuitry 104. For example, power management circuitry 102 is configured to adjust at least voltages VDDAI, VDDMH, or VDDH, thereby placing memory circuitry 104 in a normal mode, a sleep mode (holding state), or a shutdown mode (non-holding state). In some embodiments, sleep mode (holding mode) corresponds to memory circuitry 104 operating at lower power than normal mode, but memory circuitry 104 is able to retain data stored in memory cell array 104a (as described below). In some embodiments, shutdown mode (non-holding mode) corresponds to memory circuitry 104 being turned off, and data previously stored in memory cell array 104a is not retained. Other operating modes are within the scope of this disclosure.

[0036] The power management circuit 102 includes a control circuit 102a coupled to the head circuit 102b.

[0037] Control circuit 102a is configured to receive at least control signals PISO, SDB, or SLPB, and to generate at least power management control signals SD_VDDM, SLP_VDDM, or SLP_VDD. In some embodiments, control circuit 102a is configured to control the operating mode of memory circuit 104. Control circuit 102a is configured to control head circuit 102b via power management control signals SD_VDDM, SLP_VDDM, and SLP_VDD. In some embodiments, control circuit 102a is configured to adjust at least the voltage VDDAI, VDDMH, or VDDH of head circuit 102b in response to the corresponding power management control signals SD_VDDM, SLP_VDDM, or SLP_VDD, thereby placing memory circuit 104 in normal mode, sleep mode (holding state), or off mode (non-holding state).

[0038] In some embodiments, the control signal SLP_VDD has a first voltage swing. In some embodiments, at least the control signal SLP_VDDM or SD_VDDM has a second voltage swing.

[0039] The control circuit 102a includes a level shifter circuit 106, an inverter 108, a NAND logic gate 110, a level shifter circuit 112, a level shifter circuit 114, a header circuit 116, a latch 122, an OR logic gate 124, and an OR logic gate 126.

[0040] Level shifter circuit 106 is configured to receive at least a control signal PISO. Level shifter circuit 106 is a level shifter circuit configured to shift the control signal PISO from the VDDM voltage domain (using a second supply voltage VDDM1) to the VDD voltage domain (using a first supply voltage VDD1), thereby generating a control signal PISO1. In some embodiments, the control signal PISO1 is referred to as a first level shift control signal. In some embodiments, the control signal PISO1 has a first voltage swing.

[0041] Level shifter circuit 106 is coupled to header circuit 116 and OR logic gate 126. In some embodiments, level shifter circuit 106 is coupled to the gate of PMOS transistor 118 and to the first input terminal of OR logic gate 126. In some embodiments, level shifter circuit 106 is coupled to first voltage supply node N1 and second voltage supply node N2 (not shown).

[0042] Inverter 108 is coupled to level shifter circuit 114. Inverter 108 is also coupled to head circuit 116 via voltage supply node N3. In some embodiments, inverter 108 is coupled to the drain of PMOS transistor 118 via voltage supply node N3. Inverter 108 is configured to generate control signal SD1 in response to control signal SDB. In some embodiments, control signal SD1 is inverted from control signal SDB. In some embodiments, control signal SD1 has a first voltage swing. The input terminal of inverter 108 is configured to receive control signal SDB. The output terminal of inverter 108 is coupled to the input of level shifter circuit 114. The voltage supply node (not labeled) of inverter 108 is coupled to node N3. In some embodiments, the voltage supply node of inverter 108 is configured to receive voltage VDDHD of node N3.

[0043] NAND logic gate 110 is coupled to at least level shifter circuit 116 or OR logic gate 126. NAND logic gate 110 is also coupled to head circuit 116 via voltage supply node N3. In some embodiments, NAND logic gate 110 is coupled to the drain of PMOS transistor 118 via voltage supply node N3. NAND logic gate 110 is configured to generate NAND control signal SLP1 in response to control signal SLPB. In some embodiments, NAND control signal SLP1 has a first voltage swing. NAND logic gate 110 includes an output terminal configured to output NAND control signal SLP1 and coupled to the input of shifter circuit 112 and a second input terminal of OR logic gate 126. NAND logic gate 124 also includes a first input terminal configured to receive control signal SDB and a second input terminal configured to receive control signal SLPB.

[0044] Level shifter circuit 112 is configured to receive at least NAND control signal SLP1. Level shifter circuit 112 is configured to shift NAND control signal SLP1 from the VDD voltage domain (using a first supply voltage VDD1) to the VDDM voltage domain (using a second supply voltage VDDM1), thereby generating NAND control signal SLP2. In some embodiments, NAND control signal SLP2 is referred to as a level-shifted NAND control signal. In some embodiments, NAND control signal SLP2 has a second voltage swing.

[0045] Level shifter circuit 112 is coupled to NAND logic gate, header circuit 116, and OR logic gate 124. In some embodiments, level shifter circuit 112 is coupled to the drain of PMOS transistor 118 via node N3 and to the drain of PMOS transistor 120 via node N4. In some embodiments, the output of level shifter circuit 112 is coupled to the second input terminal of OR logic gate 124. In some embodiments, the output of level shifter circuit 112 is configured to output NAND control signal SLP2 to the second input terminal of OR logic gate 124. In some embodiments, level shifter circuit 112 is coupled to first voltage supply node N1 and second voltage supply node N2.

[0046] Level shifter circuit 114 is configured to receive at least control signal SD1. Level shifter circuit 114 is configured to shift control signal SD1 from the VDD voltage domain (using a first supply voltage VDD1) to the VDDM voltage domain (using a second supply voltage VDDM1), thereby generating control signal SD2. In some embodiments, control signal SD2 is referred to as a second level-shift control signal. In some embodiments, control signal SD2 has a second voltage swing.

[0047] Level shifter circuit 114 is coupled to inverter 108, header circuit 116, and latch circuit 122. In some embodiments, level shifter circuit 114 is coupled to the drain of PMOS transistor 118 via node N3 and to the drain of PMOS transistor 120 via node N4. In some embodiments, the output of level shifter circuit 114 is coupled to a first input terminal of latch circuit 122. In some embodiments, the output of level shifter circuit 114 is configured to output control signal SD2 to the first input terminal of latch circuit 122. In some embodiments, level shifter circuit 114 is coupled to a first voltage supply node N1 and a second voltage supply node N2.

[0048] Header circuit 116 includes PMOS transistors 118 and 120. In some embodiments, head circuit 116 is enabled or disabled in response to a control signal PISO. In some embodiments, head circuit 116 is configured to provide a first supply voltage VDD1 to node N3 in response to being enabled by the control signal PISO, and to provide a second supply voltage VDDM1 to node N4 in response to being enabled by the control signal PISO1. In some embodiments, if the voltage of node N3 is equal to the first supply voltage VDD1, and if the voltage of node N4 is equal to the second supply voltage VDDM1, then at least inverter 108, NAND logic gate 110, level shifter circuit 112, or level shifter circuit 114 is enabled.

[0049] In some embodiments, if the head circuit 116 is disabled by the control signal PISO or PISO1, then nodes N3 and N4 are floating or in a high-impedance state. In some embodiments, if nodes N3 and N4 are floating or in a high-impedance state, then at least inverter 108, NAND logic gate 110, level shifter circuit 112, or level shifter circuit 114 is disabled.

[0050] The source terminal of PMOS transistor 118 is configured as a first voltage supply node N1. The first voltage supply node N1 is configured to receive a first supply voltage VDD1 from the first voltage supply. The gate terminal of PMOS transistor 118 is configured to receive a control signal PISO1 from level shifter circuit 106. The drain terminal of PMOS transistor 118 is coupled through node N3 to level shifter circuit 112, level shifter circuit 114, inverter 108, and NAND logic gate 110. In some embodiments, PMOS transistor 118 is configured to set the voltage VDDHD of node N3 in response to the control signal PISO1.

[0051] In some embodiments, PMOS transistor 118 is configured to provide a first supply voltage VDD1 to node N3 in response to being enabled by control signal PISO1. In some embodiments, if PMOS transistor 118 is disabled by control signal PISO1, node N3 is floating or in a high-impedance state.

[0052] The source terminal of PMOS transistor 120 is configured as a second voltage supply node N2. The second voltage supply node N2 is configured to receive a second supply voltage VDDM1 from a second voltage supply. The gate terminal of PMOS transistor 120 is configured to receive a control signal PISO1. The drain terminal of PMOS transistor 120 is coupled to level shifter circuits 112 and 114 via node N4. In some embodiments, PMOS transistor 120 is configured to set the voltage VDDMHD of node N4 in response to the control signal PISO.

[0053] In some embodiments, PMOS transistor 120 is configured to provide a second supply voltage VDDM1 to node N4 in response to being enabled by control signal PISO. In some embodiments, if PMOS transistor 120 is disabled by control signal PISO, node N4 is floating or in a high-impedance state.

[0054] For the head circuit 116, other transistor types or other numbers of transistors are within the scope of this disclosure. For example, in some embodiments, the head circuit 116 includes at least one N-type metal-oxide-semiconductor (NMOS) transistor.

[0055] Latch circuit 122 is configured to receive control signal SD2 and control signal PISO. Latch circuit 122 is configured to generate control signal SD_VDDM. In some embodiments, latch circuit 122 is configured to latch the state of control signal SD2 in response to control signal PISO. In some embodiments, latch circuit 122 is configured to latch a previous state of control signal SD2 in response to control signal PISO. In some embodiments, control signal SD_VDDM is the latched state of control signal SD2 in response to the rising edge of control signal PISO. In some embodiments, control signal SD_VDDM is the latched state of control signal SD2 in response to the falling edge of control signal PISO.

[0056] The first input terminal of latch circuit 122 is coupled to the output of level shifter circuit 114 and configured to receive control signal SD2. The second input terminal of latch circuit 122 is configured to receive control signal PISO. In some embodiments, the second input terminal of latch circuit 122 is the clock input terminal of latch circuit 122. The output terminal of latch circuit 122 is coupled to the gate of PMOS transistor 130 of header circuit 102b and configured to output control signal SD_VDDM.

[0057] In some embodiments, latch circuit 122 corresponds to a device triggered by a positive or negative level. In some embodiments, latch circuit 122 corresponds to a flip-flop triggered by a positive or negative level. In some embodiments, latch circuit 122 corresponds to an SR flip-flop. In some embodiments, latch circuit 122 includes a DQ flip-flop, a T flip-flop, a JK flip-flop, etc.

[0058] OR logic gate 124 is coupled at least to the gate of PMOS transistor 132 of level shifter circuit 112 or header circuit 102b. OR logic gate 124 is configured to generate a control signal SLP_VDDM in response to control signals PISO and SLP2. OR logic gate 124 includes a first input terminal configured to receive control signal PISO and a second input terminal configured to receive control signal SLP2. The second input terminal of OR logic gate 124 is coupled to the output of level shifter circuit 112. OR logic gate 124 also includes an output terminal coupled to the gate of PMOS transistor 132 of header circuit 102b. The output terminal of OR logic gate 124 is configured to output the control signal SLP_VDDM to the gate of PMOS transistor 132 of header circuit 102b.

[0059] OR logic gate 126 is coupled at least to the output of level shifter circuit 106, NAND logic gate 110, or the gate of PMOS transistor 134 of header circuit 102b. OR logic gate 126 is configured to generate a control signal SLP_VDD in response to control signals PISO1 and SLP1. OR logic gate 126 includes a first input terminal configured to receive control signal PISO1 from level shifter circuit 106 and a second input terminal configured to receive control signal SLP1 from NAND logic gate 110. The first input terminal of OR logic gate 126 is coupled to the output of level shifter circuit 106. The second input terminal of OR logic gate 126 is coupled to the output of NAND logic gate 110. OR logic gate 126 also includes an output terminal coupled to the gate of PMOS transistor 134 of header circuit 102b. The output terminal of OR logic gate 126 is configured to output the control signal SLP_VDD to the gate of PMOS transistor 134 of header circuit 102b.

[0060] The head circuit 102b includes P-type metal-oxide-semiconductor (PMOS) transistors 130, 132 and 134.

[0061] In some embodiments, the header circuit 102b is enabled or disabled in response to at least the control signals SD_VDDM, SLP_VDDM, or SLP_VDD. In some embodiments, the header circuit 102b is configured to provide voltages VDDAI, VDDMH, and VDDH to the respective memory cell array 104a, peripheral circuit 104b, and peripheral circuit 104c in response to the corresponding control signals SD_VDDM, SLP_VDDM, and SLP_VDD. In some embodiments, voltage VDDH is in the VDD voltage domain. In some embodiments, at least voltage VDDAI or voltage VDDMH is in the VDDM voltage domain.

[0062] In some embodiments, if the header circuit 102b is enabled by the control signal SD_VDDM, the header circuit 102b is configured to supply the second supply voltage VDDM1 as voltage VDDAI to the memory cell array 104a, and the memory cell array 104a is in an ON state. In some embodiments, if the header circuit 102b is disabled by the control signal SD_VDDM, the memory cell array 104a is in an OFF state.

[0063] In some embodiments, if the head circuit 102b is enabled by the control signal SLP_VDDM, the head circuit 102b is configured to supply the second supply voltage VDDM1 as voltage VDDMH to the peripheral circuit 104b, and the peripheral circuit 104b is in an ON state. In some embodiments, if the head circuit 102b is disabled by the control signal SLP_VDDM, the peripheral circuit 104b is in an OFF state.

[0064] In some embodiments, if the head circuit 102b is enabled by the control signal SLP_VDD, the head circuit 102b is configured to provide the first supply voltage VDD1 as voltage VDDH to the peripheral circuit 104c, and the peripheral circuit 104c is in an ON state. In some embodiments, if the head circuit 102b is disabled by the control signal SLP_VDD, the peripheral circuit 104c is in an OFF state.

[0065] For the head circuit 102b, other transistor types or numbers of transistors are within the scope of this disclosure. For example, in some embodiments, the head circuit 102b includes at least one NMOS transistor.

[0066] The source terminal of PMOS transistor 130 is configured as a voltage supply node N5. Voltage supply node N5 is configured to receive a second supply voltage VDDM1 from a second voltage supply. The gate terminal of PMOS transistor 130 is configured to receive a control signal SD_VDDM from latch circuit 122. The drain terminal of PMOS transistor 130 is coupled to memory cell array 104a. In some embodiments, PMOS transistor 130 is configured to set voltage VDDAI in response to the control signal SD_VDDM.

[0067] The source terminal of PMOS transistor 132 is configured as a voltage supply node N6. Voltage supply node N6 is configured to receive a second supply voltage VDDM1 from a second voltage supply. The gate terminal of PMOS transistor 132 is configured to receive a control signal SLP_VDDM from OR logic gate 124. The drain terminal of PMOS transistor 132 is coupled to peripheral circuitry 104b. In some embodiments, PMOS transistor 132 is configured to set a voltage VDDMH in response to the control signal SLP_VDDM.

[0068] The source terminal of PMOS transistor 134 is configured as a voltage supply node N7. Voltage supply node N7 is configured to receive a first supply voltage VDD1 from a first voltage supply. The gate terminal of PMOS transistor 134 is configured to receive a control signal SLP_VDD from OR logic gate 126. The drain terminal of PMOS transistor 134 is coupled to peripheral circuitry 104c. In some embodiments, PMOS transistor 134 is configured to set a voltage VDDH in response to the control signal SLP_VDD.

[0069] For the head circuit 102b, other transistor types or other numbers of transistors are within the scope of this disclosure. For example, in some embodiments, the head circuit 102b includes at least one NMOS transistor.

[0070] Memory circuit 104 is coupled to power management circuit 102 and output circuit 105. Memory circuit 104 is configured to receive supply voltages VDDAI, VDDMH, and VDDH from header circuit 102b. In some embodiments, memory circuit 104 is configured to store data Doutb. In some embodiments, memory circuit 104 is configured to output the stored data Doutb to output circuit 105.

[0071] The memory circuit 104 includes a memory cell array 104a, peripheral circuits 104b, and peripheral circuits 104c. Figure 1 In this embodiment, memory circuit 104 is a static random access memory (SRAM) circuit. SRAM is used for illustration, and other types of memory are within the scope of various embodiments. In some embodiments, memory circuit 104 is a dynamic random access memory (DRAM) circuit, other forms of volatile RAM memory, etc. In some embodiments, memory circuit 104 is a resistive random access memory (RRAM) circuit, ferroelectric RAM (F-RAM), magnetoresistive RAM (MRAM), phase-change memory (PCM), other forms of non-volatile RAM memory, etc.

[0072] Both the memory cell array 104a and the peripheral circuitry 104b are configured to operate in the VDDM voltage domain. The peripheral circuitry 104c is configured to operate in the VDD voltage domain.

[0073] Memory cell array 104a is configured to store data Doutb. At least one memory cell in memory cell array 104a is configured to store logic "1" or logic "0". At least one memory cell in memory cell array 104a is coupled to supply voltage node N5 via PMOS transistor 130. At least one memory cell in memory cell array 104a is configured to receive voltage VDDAI. In some embodiments, voltage VDDAI corresponds to a second supply voltage VDDM1.

[0074] In some embodiments, the memory cell array 104a includes one or more 4-transistor (4T) SRAM cells, 5-transistor (5T) SRAM cells, 6-transistor (6T) SRAM cells, 8-transistor (8T) SRAM cells, etc. In some embodiments, the memory cell array 104a includes one or more single-port (SP) SRAM cells. In some embodiments, the memory cell array 104a includes one or more dual-port (DP) SRAM cells. Different types of memory cells in the memory cell array 104a are within the scope of this disclosure. In some embodiments, the memory cell array 104a is a DRAM cell array, other forms of volatile RAM memory cell arrays, etc. In some embodiments, the memory cell array 104a is an RRAM memory cell array, an F-RAM memory cell array, an MRAM memory cell array, a PCM memory cell array, other forms of non-volatile RAM memory cell arrays, etc.

[0075] Peripheral circuitry 104b is coupled to and configured to control memory cell array 104a. Peripheral circuitry 104b is configured to operate in the VDDM voltage domain. At least one circuit in peripheral circuitry 104b is coupled to supply voltage node N6 via PMOS transistor 132. At least one circuit in peripheral circuitry 104b is configured to receive voltage VDDMH. In some embodiments, voltage VDDMH corresponds to a second supply voltage VDDM1.

[0076] In some embodiments, the peripheral circuitry 104b includes one or more of a row decoder, a column decoder, read bit line precharge logic, a readout amplifier, timing and control circuitry, etc., configured to operate in the VDDM voltage domain. Different types of circuitry in the peripheral circuitry 104b are within the scope of this disclosure.

[0077] Peripheral circuitry 104c is coupled to and configured to control memory cell array 104a. Peripheral circuitry 104c is configured to operate in the VDD voltage domain. At least one circuit in peripheral circuitry 104c is coupled to supply voltage node N7 via PMOS transistor 134. At least one circuit in peripheral circuitry 104c is configured to receive voltage VDDH. In some embodiments, voltage VDDH corresponds to a first supply voltage VDD1.

[0078] In some embodiments, the peripheral circuitry 104c includes one or more of a row decoder, a column decoder, read bit line precharge logic, a readout amplifier, timing and control circuitry, etc., configured to operate in the VDD voltage domain. Different types of circuitry in the peripheral circuitry 104c are within the scope of this disclosure.

[0079] Output circuit 105 is coupled to memory cell array 104a. Output circuit 105 is configured to receive stored data Doutb from memory cell array 104a and is configured to generate a clamped output data signal Qvdd. In some embodiments, clamped output data signal Qvdd corresponds to the stored data Doutb. In some embodiments, output circuit 105 includes buffer circuit 502 ( Figure 5 The buffer is configured to buffer the stored data Doutb. In some embodiments, the stored data Doutb is in the VDDM voltage domain, and the clamped output data signal Qvdd is in the VDD voltage domain.

[0080] Figure 2 This is a circuit diagram of circuit 200 according to some embodiments.

[0081] Circuit 200 is Figure 1 An embodiment of the control circuit 102a.

[0082] and Figure 2 , Figure 5-6 , Figure 8 , Figure 11 and Figure 12 Components that are the same or similar to those in one or more of the figures shown below are given the same reference numerals, and therefore their detailed descriptions are omitted.

[0083] Circuit 200 includes level shifter circuit 206, inverter 108, NAND logic gate 110, level shifter circuit 112, level shifter circuit 114, header circuit 116, latch 122, NOR logic gate 224a, inverter 224b, NOR logic gate 226a, inverter 226b, inverter 240, inverter 242, inverter 244 and inverter 246.

[0084] and Figure 1 Compared to control circuit 102a, level shifter circuit 206 replaces level shifter circuit 106, NOR logic gate 224a and inverter 224b of circuit 200 replace OR logic gate 124, and NOR logic gate 226a and inverter 226b of circuit 200 replace OR logic gate 126, therefore similar detailed descriptions are omitted.

[0085] and Figure 1 Compared to the control circuit 102a, circuit 200 also includes inverters 240, 242, 244 and 246.

[0086] NOR logic gate 224a is coupled to at least level shifter circuit 112. NOR logic gate 224a is configured to generate a control signal SLP_VDDMB in response to control signals PISO and SLP2. In some embodiments, the control signal SLP_VDDMB has a second voltage swing. NOR logic gate 224a includes a first input terminal configured to receive control signal PISO and a second input terminal configured to receive control signal SLP2. The second input terminal of NOR logic gate 224a is coupled to the output of level shifter circuit 112. NOR logic gate 224a also includes an output terminal coupled to the input terminal of inverter 224b. The output terminal of NOR logic gate 224a is configured to output the control signal SLP_VDDMB to the input terminal of inverter 224b. A voltage supply node (unlabeled) of NOR logic gate 224a is configured to receive a second supply voltage VDDM1.

[0087] Inverter 224b is coupled to NOR logic gate 224a. Inverter 224b is configured to generate control signal SLP_VDDM in response to control signal SLP_VDDMB. In some embodiments, control signal SLP_VDDM is inverted from control signal SLP_VDDMB. The input terminal of inverter 224b is coupled to the output terminal of NOR logic gate 224a and is configured to receive control signal SLP_VDDMB. The output terminal of inverter 224b is configured to output control signal SLP_VDDM. The voltage supply node (unlabeled) of inverter 224b is configured to receive a second supply voltage VDDM1. In some embodiments, NOR logic gate 224a and inverter 224b have... Figure 1 It has the same function as the OR logic gate 124.

[0088] NOR logic gate 226a is coupled to at least the output of inverter 242, NAND logic gate 110, or the input terminal of inverter 226b. NOR logic gate 226a is configured to generate a control signal SLP_VDDB in response to control signals PISO1 and SLP1. In some embodiments, the control signal SLP_VDDB has a first voltage swing. NOR logic gate 226a includes a first input terminal configured to receive the control signal PISO1 from inverter 242 and a second input terminal configured to receive the control signal SLP1 from NAND logic gate 110. The first input terminal of NOR logic gate 226a is coupled to the output terminal of inverter 242. The second input terminal of NOR logic gate 226a is coupled to the output of NAND logic gate 110. NOR logic gate 226a also includes an output terminal coupled to the input terminal of inverter 226b. The output terminal of NOR logic gate 226a is configured to output the control signal SLP_VDDB to the input terminal of inverter 226b. The voltage supply node (unlabeled) of the NOR logic gate 226a is configured to receive the first supply voltage VDD1.

[0089] Inverter 226b is coupled to NOR logic gate 226a. Inverter 226b is configured to generate a control signal SLP_VDD in response to a control signal SLP_VDDB. In some embodiments, the control signal SLP_VDD is inverted from the control signal SLP_VDDB. The input terminal of inverter 226b is coupled to the output terminal of NOR logic gate 226a and is configured to receive the control signal SLP_VDDB. The output terminal of inverter 226b is configured to output the control signal SLP_VDD. The voltage supply node (unlabeled) of inverter 226b is configured to receive a first supply voltage VDD1. In some embodiments, NOR logic gate 226a and inverter 226b have... Figure 1 It has the same function as the OR logic gate 126.

[0090] Inverter 240 is coupled to the input of level shifter circuit 206. Inverter 240 is configured to generate control signal PISOB in response to control signal PISO. In some embodiments, control signal PISOB is inverted from control signal PISO. In some embodiments, control signal PISOB has a second voltage swing. The input terminal of inverter 240 is configured to receive control signal PISO. The output terminal of inverter 240 is coupled to the input of level shifter circuit 206 and is configured to output control signal PISOB. The voltage supply node (unlabeled) of inverter 240 is configured to receive a second supply voltage VDDM1.

[0091] Level shifter circuit 206 is Figure 1A variation of the level shifter circuit 106, with similar detailed descriptions omitted. (And...) Figure 1 Compared to the level shifter circuit 106, the input of the level shifter circuit 206 is coupled to the output terminal of the inverter 240 and configured to receive the signal PISOB, and the output of the level shifter circuit 206 is coupled to the input terminal of the inverter 242 and configured to output the signal PISOB1.

[0092] The level shifter circuit 206 is configured to shift the control signal PISOB from the VDDM voltage domain (using the second supply voltage VDDM1) to the VDD voltage domain (using the first supply voltage VDD1), thereby generating the control signal PISOB1. In some embodiments, the control signal PISOB1 has a first voltage swing, and the control signal PISOB has a second voltage swing.

[0093] Inverter 242 is coupled to the output of level shifter circuit 206. Inverter 242 is configured to generate control signal PISO1 in response to control signal PISOB1. In some embodiments, control signal PISO1 is inverted from control signal PISOB1. In some embodiments, control signal PISOB1 has a first voltage swing. The input terminal of inverter 242 is coupled to the output of level shifter circuit 206 and is configured to receive control signal PISOB1. The output terminal of inverter 242 is configured to output control signal PISO1. The output terminal of inverter 242 is coupled to the gate of PMOS transistor 118 and the first input terminal of NOR logic gate 226a. The voltage supply node (unlabeled) of inverter 242 is configured to receive a second supply voltage VDDM1.

[0094] Inverter 244 is coupled between latch circuit 122 and inverter 246. Inverter 244 is configured to generate an inverted control signal SD_VDDM1B in response to control signal SD_VDDM1. In some embodiments, control signal SD_VDDM1B is inverted from control signal SD_VDDM1. In some embodiments, at least control signal SD_VDDM1B or SD_VDDM1 has a second voltage swing. The input terminal of inverter 244 is coupled to the output of latch circuit 122 and is configured to receive control signal SD_VDDM1. The output terminal of inverter 244 is configured to output control signal SD_VDDM1B. The output terminal of inverter 244 is coupled to the input terminal of inverter 246. The voltage supply node (unlabeled) of inverter 244 is configured to receive a second supply voltage VDDM1.

[0095] Inverter 246 is coupled to inverter 244. Inverter 246 is configured to generate a control signal SD_VDDM in response to a control signal SD_VDDM1B. In some embodiments, the control signal SD_VDDM is inverted from the control signal SD_VDDM1B. In some embodiments, the control signal SD_VDDM is a delayed version of the control signal SD_VDDM1. The input terminal of inverter 246 is coupled to the output terminal of inverter 244 and is configured to receive the control signal SD_VDDM1B. The output terminal of inverter 246 is configured to output the control signal SD_VDDM. The voltage supply node (unlabeled) of inverter 246 is configured to receive a second supply voltage VDDM1.

[0096] Truth table

[0097] Figure 3 According to some embodiments Figure 1 Circuit 100, or Figure 2 Truth table 300 for circuit 200. Values ​​and formats of table 300 are provided as examples, and other values ​​and / or formats of table 300 are within the scope of this disclosure.

[0098] like Figure 3 As shown in the first row of the truth table 300, if the control signal PISO is logic 0, then the control signal SDB is logic 1 and the control signal SLPB is logic 1. Then the power management circuit 102 or the circuit 200 makes the control signals SLP_VDD, SLP_VDDM and SD_VDDM each logic 0, thereby putting the memory circuit 104 in normal mode.

[0099] like Figure 3 As shown in the second row of the truth table 300, if the control signal PISO is logic 0, then the control signal SDB is logic 1 and the control signal SLPB is logic 0. Then the power management circuit 102 or the circuit 200 makes the control signals SLP_VDD and SLP_VDDM logic 1 and the control signal SD_VDDM logic 0 respectively, thereby putting the memory circuit 104 into sleep mode (hold mode).

[0100] like Figure 3 As shown in row 3 of truth table 300, if control signal PISO is logic 0 and control signal SDB is logic 0, then power management circuit 102 or circuit 200 sets each of control signals SLP_VDD, SLP_VDDM, and SD_VDDM to logic 1, thereby putting memory circuit 104 in a shutdown mode (non-holding mode). In some embodiments, at least for row 3 of truth table 300, the value of control signal SLPB is conditional and... Figure 3 The middle part is represented by "-".

[0101] like Figure 3 As shown in rows 4 and 5 of the truth table 300, when the control signal PISO is logic 1, the memory circuit 104 is automatically put into sleep mode (hold mode) or off mode (non-hold mode), thereby reducing the power consumption of at least circuit 100 or 200.

[0102] like Figure 3 As shown in row 4 of truth table 300, if control signal PISO is logic 1 and control signal SDB is logic 1, then power management circuit 102 or circuit 200 sets control signals SLP_VDD and SLP_VDDM to logic 1 respectively, and control signal SD_VDDM to logic 0, causing memory circuit 104 to enter sleep mode (hold mode). In some embodiments, at least for row 4 of truth table 300, the value of control signal SLP is conditional. In some embodiments, at least for row 4 of truth table 300, after signal SD2 is latched by latching circuit 122 and the first supply voltage VDD1 is turned off by control circuit 1200, control signal SDB is in a floating or high impedance state (Z*). Figure 12 ), thereby at least Figure 1-2 The level shifter circuits 114 or 116 in the circuit are disabled.

[0103] like Figure 3 As shown in row 5 of truth table 300, if control signal PISO is logic 1 and control signal SDB is logic 0, then power management circuit 102 or circuit 200 sets each of control signals SLP_VDD, SLP_VDDM, and SD_VDDM to logic 1, thereby putting memory circuit 104 in a shutdown mode (non-holding mode). In some embodiments, at least for row 5 of truth table 300, the value of control signal SLPB is conditional. In some embodiments, at least for row 5 of truth table 300, after signal SD2 is latched by latching circuit 122 and the first supply voltage VDD1 is turned off by control circuit 1200, control signal SDB is in a floating or high-impedance state (Z*). Figure 12 ), thereby at least Figure 1-2 The level shifter circuits 114 or 116 in the circuit are disabled.

[0104] waveform

[0105] Figures 4A-4E This is a graph showing waveforms 400A-400E of a circuit according to some embodiments. In some embodiments, waveforms 400A-400E correspond to... Figure 1 Circuit 100, or Figure 2 The waveform of circuit 200.

[0106] Waveform 400A includes curves 410, 412, 414, and 416 for signals in circuit 100 or 200 in off mode (non-holding). Waveform 400B includes curves 410, 412, 414', and 416 for signals in circuit 100 or 200 in off mode (non-holding). Waveform 400C includes curves 420, 422, 424, and 426 for signals in circuit 100 or 200 in off mode (non-holding). Waveform 400D includes curves 430, 432, 434, and 436 for signals in circuit 100 or 200 in sleep mode (holding). Waveform 400E includes curves 440, 442, 444, and 446 for signals in circuit 100 or 200 in sleep mode (holding).

[0107] In some embodiments, at least curves 410, 420, 430, or 440 represent Figure 1 and Figure 2 The first supply voltage VDD1; at least curves 412, 422, 432 or 442 indicate Figure 1-2 The control signal PISO; at least curves 414, 414', 424, 434, or 444 represent Figure 1-2 The control signal SDB; and at least curves 416, 426, 436, and 446 represent Figure 1-2 The control signal SLPB.

[0108] Waveform 400A includes curves 410, 412, 414, and 416 for signals in circuit 100 or 200 in off mode (non-hold). In some embodiments, waveform 400A illustrates a transition from a normal mode (e.g., row 1 in Table 300) to an off mode (e.g., row 5 in Table 300).

[0109] At time T1, curve 410 represents logic 1, curve 412 represents logic 0, curve 414 represents logic 1, curve 416 represents logic 1, and memory circuit 104 is in normal mode (e.g., Figure 3 (The first row in Table 300). At time T1, curve 414 begins to transition from logic 1 to logic 0. For example, in some embodiments, curves 410, 412, 414, and 416 at time T1 correspond to the first row of the entries shown in Table 300.

[0110] At time T2, curve 414 completes the transition to logic 0, which causes the control signals SLP_VDD and SLP_VDDM to change from logic 0 to logic 1, thereby putting circuit 100 or 200 into the off mode (e.g., row 3 of Table 300).

[0111] At time T3, curve 412 begins to transition from logic 0 to logic 1, thereby causing power management circuit 100 to enter power management mode, which in turn causes memory circuit 104 to enter shutdown mode.

[0112] At time T4, curve 412 is located midway between logic 0 and logic 1. The change of curve 412 from logic 0 to logic 1 causes latch circuit 122 to latch the previous state of curve 414 (e.g., control signal SDB), which is logic 0. In some embodiments, the previous state of curve 414 (e.g., control signal SDB) is the value of curve 414 at time T2. However, latch circuit 122 satisfies both setup time Ts and hold time Th to properly latch stable state information.

[0113] The difference between times T4 and T2 is the setup time Ts of latch circuit 122. In some embodiments, setup time Ts corresponds to the minimum time interval during which the input signal of latch circuit 122 (e.g., control signal SD2) is stable (e.g., constant) before the sampling event of the clock signal (e.g., control signal PISO) (so that the input signal (e.g., control signal SD2) is correctly identified by latch circuit 122). For example, in some embodiments, if curve 414 changes within the setup time Ts of latch circuit 122, latch circuit 122 may not latch the appropriate state of curve 414. Figure 4A As shown, since the transition of curve 414 from logic 1 to logic 0 occurs at time T2 before setup time Ts, the previous state of curve 414 (e.g., control signal SDB) is logic 0 and is properly latched by latching circuit 122. However, if control signal SDB (in Figure 4B (As shown by curve 414') If the state changes between time T2 and T4, the latch circuit 122 can latch the state before the transition.

[0114] At time T5, curve 412 is logic 1, which puts the power management circuit 100 in power management mode, thereby putting the memory circuit 104 in off (non-holding) mode (e.g., row 5 of Table 300).

[0115] The difference between times T4 and T5 is the hold time Th of the latch circuit 122. In some embodiments, the hold time Th is the minimum time interval during which the input signal of the latch circuit 122 (e.g., control signal SD2) remains stable (e.g., unchanged) after a sampling event of a clock signal (e.g., control signal PISO) (so that, for example, control signal SD2 is correctly identified by the latch circuit 122). For example, in some embodiments, if curve 414 changes within the hold time Th of the latch circuit 122, the latch circuit 122 may not latch the appropriate state of curve 414.

[0116] Between time T5 and T6, memory circuit 104 is in a shutdown mode (non-holding) (e.g., row 5 of Table 300).

[0117] At time T7, curve 412 begins to transition from logic 1 to logic 0, thereby causing power management circuit 100 to exit power management mode.

[0118] After time T7, curve 412 becomes logic 0, and power management circuit 100 exits power management mode and returns to normal mode.

[0119] Figure 4B This is a waveform diagram 400B of a circuit according to some embodiments.

[0120] Waveform 400B includes curves 410, 412, 414', and 416 for signals in circuit 100 or 200 in off mode (non-holding). Waveform 400B is a variation of waveform 400A, therefore a similar detailed description is omitted. Compared to waveform 400A, Figure 4B Curve 414' replaces curve 414, therefore a similar detailed description is omitted.

[0121] Waveform 400B shows when curve 414' (e.g., control signal SDB) changes state between times T2 and T4 (within setup time Ts), and therefore latches the state of curve 414' before the transition (e.g., logic 0) at time T2.

[0122] In some embodiments, curve 414' of waveform 400B illustrates the transition from a closed mode (e.g., row 3 in Table 300) to a closed mode (e.g., row 5 in Table 300).

[0123] At time T1, curve 414' begins to transition from logic 0 to logic 1.

[0124] After time T2 and before time T3, curve 414' completes its conversion to logic 1.

[0125] At time T3, curve 412 begins to transition from logic 0 to logic 1, thereby causing power management circuit 100 to enter power management mode, which in turn causes memory circuit 104 to enter shutdown mode.

[0126] At time T4, curve 412 is positioned midway between logic 0 and logic 1. The change of curve 412 from logic 0 to logic 1 causes latch circuit 122 to latch the previous state of curve 414' (e.g., control signal SDB), which is logic 0. Since curve 414' (e.g., control signal SDB) changes state between times T2 and T4 (within the setup time Ts), latch circuit 122 latches the state of curve 414' before the transition at time T2 (e.g., logic 0) to satisfy setup time Ts to properly latch a stable state.

[0127] At time T5, curve 412 is logic 1, which puts the power management circuit 100 in power management mode, thereby putting the memory circuit 104 in off (non-holding) mode (e.g., row 5 of Table 300).

[0128] exist Figure 4B After time T5, similar to Figure 4A Therefore, for the sake of brevity, similar detailed descriptions are omitted.

[0129] Figure 4C This is a diagram of waveform 400C of a circuit according to some embodiments. Waveform 400C is an example of power management circuit 100 being in power management mode and memory circuit 104 being in a shutdown mode (non-holding state). Waveform 400C includes curves 420, 422, 424, and 426 for signals in circuit 100 or 200 in shutdown mode (non-holding). In some embodiments, waveform 400C illustrates a transition from sleep mode (e.g., row 2 in Table 300) to shutdown mode (e.g., row 3 in Table 300).

[0130] At time T1, curve 422 is logic 0, and power management circuit 100 is not in power management mode. At time T2, curve 424 transitions from logic 1 to logic 0, which causes the control signal SD_VDDM to transition from logic 0 (e.g., row 2 in Table 300) to logic 1 (e.g., row 3 in Table 300), thereby putting memory circuit 104 into a shutdown mode (non-holding). For example, in some embodiments, this transition of curve 424 corresponds to the transition from row 3 to row 4 of the entry for a positive level sensitive latch for latch circuit 122 shown in Table 300.

[0131] At time T2, curve 424 is logic 0, which causes the control signal SD_VDDM to switch from logic 0 to logic 1, thereby putting circuit 100 or 200 into shutdown mode (e.g., row 3 of Table 300).

[0132] Between time T3 and T4, memory circuit 104 is in the off mode (non-retained).

[0133] At time T5, curve 422 is logic 0, and curve 424 transitions from logic 0 to logic 1, which causes the control signal SD_VDDM to transition from logic 1 to logic 0, thereby putting memory circuit 104 into sleep mode (hold). For example, in some embodiments, this transition of curve 424 corresponds to the transition from row 3 to row 2 of the entries shown in Table 300.

[0134] After time T5, curve 424 is logic 1.

[0135] Figure 4D This is a diagram of waveform 400D of a circuit according to some embodiments. Waveform 400D is an example of power management circuit 100 entering power management mode and memory circuit 104 entering sleep mode (hold state). Waveform 400D includes curves 430, 432, 434, and 436 for signals in circuit 100 or 200 in off mode (non-hold). In some embodiments, waveform 400D illustrates a transition from a normal mode (e.g., row 1 in Table 300) to a sleep mode (e.g., row 4 in Table 300).

[0136] The timing label for waveform 400D is similar to that for waveform 400A, so for the sake of brevity, similar detailed descriptions have been omitted.

[0137] During time T1-T2, curve 430 represents logic 1, curve 432 represents logic 0, curve 434 represents logic 1, curve 436 represents logic 1, and memory circuit 104 is in normal mode (e.g., Figure 3 (Row 1 in Table 300).

[0138] At time T3, curve 432 begins to transition from logic 0 to logic 1, thereby causing power management circuit 100 to enter power management mode. This causes control signals SLP_VDD and SLP_VDDM to transition from logic 0 to logic 1, thereby causing memory circuit 104 to enter sleep mode.

[0139] At time T4, curve 432 is in the middle position between logic 0 and logic 1. The change of curve 432 from logic 0 to logic 1 causes latch circuit 122 to latch the previous state of curve 434 (e.g., control signal SDB), which is logic 1.

[0140] At time T5, curve 432 is logic 1, which puts the power management circuit 100 into power management mode, thereby putting the memory circuit 104 into sleep (hold) mode (e.g., row 4 of Table 300).

[0141] Between time T5 and T6, memory circuit 104 is in sleep mode (hold) (e.g., row 4 of Table 300).

[0142] At time T7, curve 432 begins to transition from logic 1 to logic 0, thereby causing power management circuit 100 to exit power management mode.

[0143] After time T7, curve 432 is logic 0, and power management circuit 100 leaves power management mode and returns to normal mode (e.g., row 1 of Table 300).

[0144] Figure 4E This is a diagram of waveform 400E according to some embodiments of the circuit. Waveform 400E is an example of power management circuit 100 being in power management mode and memory circuit 104 being in sleep mode (hold state). Waveform 400E includes curves 440, 442, 444, and 446 for signals in circuit 100 or 200 in sleep mode (hold state). For example, in some embodiments, Figure 4E An example is shown in which the memory circuit 104 is in sleep mode (hold state) or row 4 of table 300, regardless of the transition of curve 446.

[0145] At time T1, curve 442 is logic 1, and power management circuit 100 is in power management mode. At time T1, curve 444 is logic 1, therefore memory circuit 104 is in sleep mode (hold). At time T1, curve 446 transitions from logic 1 to logic 0. For example, in some embodiments, time T1 for curves 442, 444, and 446 corresponds to row 4 of the entries shown in Table 300.

[0146] At time T2, curve 446 is logic 0, but since curves 442 and 444 are logic 1, the transition of curve 446 to logic 0 will not affect the output of NOR gates 224a and 226a. Therefore, control signals SLP_VDD and SLP_VDDM are logic 1, and control signal SD_VDDM is logic 1.

[0147] Between time T3 and T4, memory circuit 104 is in sleep mode (hold).

[0148] At time T5, curves 442 and 444 are logic 1, and curve 446 changes from logic 0 to logic 1.

[0149] After time T5, curve 446 represents logic 1.

[0150] Output circuit

[0151] Figure 5 This is a circuit diagram of an output circuit 500 according to some embodiments.

[0152] Output circuit 500 is Figure 1 An embodiment of the output circuit 105.

[0153] Output circuit 500 is configured to clamp signal Qvdd (in VDD domain) using control signal SLP_VDDM (in VDDM domain). In some embodiments, the supply voltage VDD is turned off, so signals in VDD domain cannot be used to clamp signal Qvdd, and signals in VDDM domain are used to clamp signal Qvdd. Other configurations exist that allow other signals in VDDM domain to clamp signal Qvdd.

[0154] The output circuit 500 includes a buffer circuit 502, a NOR logic gate 504, a level shifter circuit 506, an inverter 508, and an NMOS transistor 510.

[0155] Buffer circuit 502 is coupled to NOR logic gate 504. Buffer circuit 502 is configured to receive the data signal Doutb. Buffer circuit 502 is configured to output the data signal Dout. Buffer circuit 502 is configured to buffer the data signal Doutb, thereby generating the data signal Dout. In some embodiments, the data signal Dout is a buffered version of the data signal Doutb. In some embodiments, buffer circuit 502 is a complementary MOS (CMOS) buffer circuit.

[0156] NOR logic gate 504 is coupled at least to the input of buffer circuit 502 or level shifter circuit 506. NOR logic gate 504 is configured to generate a signal preQ in response to a data signal Dout and a control signal SLP_VDDM. In some embodiments, the control signal preQ has a second voltage swing. NOR logic gate 504 includes a first input terminal configured to receive the data Dout signal from buffer circuit 502, and a second input terminal configured to receive the data Dout signal from buffer circuit 502. Figure 1 The control circuit 102a receives the control signal SLP_VDDM at its second input terminal.

[0157] The first input terminal of the NOR logic gate 504 is coupled to the output terminal of the buffer circuit 502. The second input terminal of the NOR logic gate 504 is coupled to... Figure 1 The control circuit 102a is described above. In some embodiments, the second input terminal of the NOR logic gate 504 is coupled to... Figure 2 , Figure 6 and Figure 8 The inverter 224b. In some embodiments, the second input terminal of the NOR logic gate 504 is coupled to... Figure 1 The output of OR logic gate 124 in the code.

[0158] NOR logic gate 504 also includes an output terminal coupled to the input of level shifter circuit 506. The output terminal of NOR logic gate 504 is configured to output the signal preQ to the input of level shifter circuit 506. The voltage supply node (unlabeled) of NOR logic gate 504 is configured to receive a second supply voltage VDDM1.

[0159] Level shifter circuit 506 is configured to receive signal preQ. Level shifter circuit 506 is configured to shift signal preQ from the VDDM voltage domain (using the second supply voltage VDDM1) to the VDD voltage domain (using the first supply voltage VDD1), thereby generating control signal QBvdd. In some embodiments, signal QBvdd is referred to as a level-shifted data signal. In some embodiments, signal QBvdd has a first voltage swing.

[0160] Level shifter circuit 506 is coupled to NOR logic gate 504 and inverter 508. In some embodiments, level shifter circuit 506 is further coupled to header circuit 116 (not shown). In some embodiments, level shifter circuit 506 is coupled to first voltage supply node N1 and second voltage supply node N2 (not shown). The input of level shifter circuit 506 is coupled to the output terminal of NOR logic gate 504. The output of level shifter circuit 506 is coupled to the input terminal of inverter 508 and configured to output signal PISOB1.

[0161] Inverter 508 is coupled to level shifter circuit 506 and NMOS transistor 510. Inverter 508 is configured to generate signal Qvdd in response to signal QBvdd. In some embodiments, signal Qvdd has a first voltage swing. In some embodiments, signal Qvdd is inverted from signal QBvdd. The input terminal of inverter 508 is coupled to the output of level shifter circuit 506 and is configured to receive signal QBvdd. The output terminal of inverter 508 is configured to output signal Qvdd. The voltage supply node (unlabeled) of inverter 508 is coupled to node N3 and is configured to receive a first supply voltage VDD1.

[0162] The drain terminal of NMOS transistor 510 is coupled to the output terminal of inverter 508. The gate terminal of NMOS transistor 510 is coupled to... Figure 1 The control circuit 102a is included. In some embodiments, the gate terminal of the NMOS transistor 510 is coupled to... Figure 2 , Figure 6 and Figure 8 The inverter 224b in the middle. In some embodiments, the gate terminal of the NMOS transistor 510 is coupled to Figure 1The output of OR logic gate 124 in the NMOS transistor 510 is used. The gate terminal of the NMOS transistor 510 is configured to receive the control signal SLP_VDDM. The source terminal of the NMOS transistor 510 is configured as a reference supply node, which is configured to receive the reference supply voltage VSS from the reference power supply.

[0163] In some embodiments, NMOS transistor 510 is configured to set or clamp signal Qvdd in response to control signal SLP_VDDM. For example, in some embodiments, if signal SLP_VDDM is logic 1, transistor 510 is turned on and pulls node N8 to ground, making signal Qvdd logic 0. In other words, signal SLP_VDDM is used to clamp signal Qvdd to logic 0.

[0164] In some embodiments, if the signal SLP_VDDM is logic 0, the NMOS transistor 510 is turned off, and the signal Qvdd on node N8 depends on the data signal Dout. For example, in these embodiments, if the signal SLP_VDDM is logic 0 and the data signal Dout is logic 1, then the signal Qvdd is logic 1. For example, in these embodiments, if the signal SLP_VDDM is logic 0 and the data signal Dout is logic 0, then the signal Qvdd is logic 0. Therefore, when the signal SLP_VDDM is logic 0, the value of the signal Qvdd is equal to the data signal Dout because the memory cell array 104a is in a normal operating mode (state) configured to store or read data.

[0165] In some embodiments, when the power management circuit 100 enters the power management mode by converting the control signal PISO to logic 1, the circuit 1200 ( Figure 12 The supply voltage VDD is turned off, and the output circuit 500 is configured to clamp the signal Qvdd (in the VDD domain) to logic 0 using the control signal SLP_VDDM (in the VDDM domain). In these embodiments, since the supply voltage VDD is turned off, the signal in the VDD domain cannot be used to clamp the signal Qvdd, while the signal in the VDDM domain is used to clamp the signal Qvdd.

[0166] circuit

[0167] Figure 6 This is a circuit diagram of circuit 600 according to some embodiments.

[0168] Circuit 600 is Figure 2 A variation of circuit 200 is used, therefore a similar detailed description is omitted. (And...) Figure 2 Compared to circuit 200, Figure 6 The latch circuit 602 and Figure 6The inverter 604 replaces the NOR logic gate 224a, therefore a similar detailed description is omitted. Circuit 600 is... Figure 1 An embodiment of the control circuit 102a.

[0169] Latch circuit 602 is configured to receive control signal PISO and control signal SLP2 from level shifter circuit 112. Latch circuit 602 is configured to generate control signal SLP3. In some embodiments, control signal SLP3 has a second voltage swing. In some embodiments, latch circuit 602 is configured to latch the state of control signal SLP2 in response to control signal PISO. In some embodiments, latch circuit 602 is configured to latch a previous state of control signal SLP2 in response to control signal PISO. In some embodiments, control signal SLP3 or SLP_VDDM is a latched state of control signal SLP2 in response to a rising edge of control signal PISO. In some embodiments, control signal SLP3 or SLP_VDDM is a latched state of control signal SLP2 in response to a falling edge of control signal PISO.

[0170] The first input terminal of latch circuit 602 is coupled to the output of level shifter circuit 112 and configured to receive control signal SLP2. The second input terminal of latch circuit 602 is configured to receive control signal PISO. In some embodiments, the second input terminal of latch circuit 602 is the clock input terminal of latch circuit 602. The output terminal of latch circuit 602 is coupled to the input terminal of inverter 604 and configured to output control signal SLP3.

[0171] In some embodiments, latch circuit 602 corresponds to a positive-edge or negative-edge triggered flip-flop. In some embodiments, latch circuit 602 corresponds to an SR flip-flop. In some embodiments, edge-triggered flip-flops include DQ flip-flops, T flip-flops, JK flip-flops, etc. The voltage supply node (unlabeled) of latch circuit 602 is configured to receive a second supply voltage VDDM1.

[0172] Inverter 604 is coupled between latch circuit 602 and inverter 224b. Inverter 604 is configured to generate control signal SLP3B in response to control signal SLP3. In some embodiments, control signal SLP3B has a second voltage swing. In some embodiments, control signal SLP3B is inverted from control signal SLP3. The input terminal of inverter 604 is coupled to the output terminal of latch circuit 602 and is configured to receive control signal SLP3. The output terminal of inverter 604 is coupled to the input terminal of inverter 224b and is configured to output control signal SLP3B to the input terminal of inverter 224b. The voltage supply node (unlabeled) of inverter 604 is configured to receive a second supply voltage VDDM1.

[0173] Figure 6 The inverter 224b is configured to generate a control signal SLP_VDDM in response to a control signal SLP3B. In some embodiments, the control signal SLP_VDDM is inverted from the control signal SLP3B. In some embodiments, the control signal SLP_VDDM is a delayed version of the control signal SLP3B.

[0174] waveform

[0175] Figures 7A-7B This is a diagram of waveforms 700A-700B of a circuit according to some embodiments. In some embodiments, waveforms 700A-700B correspond to... Figure 1 Circuit 100, or Figure 6 The waveform of circuit 600.

[0176] Waveform 700A is an example of power management circuits 100 and 600 entering power management mode, thereby causing memory circuit 104 to enter sleep mode (hold state).

[0177] Waveform 700A includes curves 710, 712, 714, and 716 for signals in circuit 100 or 600 in sleep mode (hold). Waveform 700B includes curves 720, 722, 724, and 726 for signals in circuit 100 or 600 in off mode (non-hold).

[0178] In some embodiments, at least curve 710 or 720 represents Figure 1 and Figure 6 The first supply voltage VDD1; at least curve 712 or 722 indicates Figure 1 and Figure 6 The control signal PISO; at least curve 714 or 724 indicates Figure 1 and Figure 6 The control signal SDB; and at least curve 716 or 726 indicates Figure 1 and Figure 6 The control signal SLPB. The timing labels for waveforms 700A-700B are similar to those for waveforms 400A-400E, so similar detailed descriptions are omitted for brevity. In some embodiments, waveform 700A shows a transition from a normal mode (e.g., row 1 in Table 300) to a sleep mode (e.g., row 4 in Table 300).

[0179] At time T1, curve 710 is logic 1, curve 712 is logic 0, curve 714 is logic 1, curve 716 is logic 1, and memory circuit 104 is in normal mode (e.g., Figure 3(The first row in Table 300). For example, in some embodiments, curves 710, 712, 714, and 716 at time T1 correspond to the first row of the entries shown in Table 300.

[0180] At time T1, curve 716 begins to transition from logic 1 to logic 0.

[0181] At time T3, curve 716 completes the transition to logic 0, which causes the control signals SLP_VDD and SLP_VDDM to change from logic 0 to logic 1, thereby putting circuit 100 or 600 into sleep mode (e.g., row 2 of Table 300).

[0182] At time T3, curve 712 begins to transition from logic 0 to logic 1, thereby causing power management circuit 100 to switch to power management mode. In some embodiments, the power management mode of power management circuit 100 is a sleep (hold mode) state (e.g., row 4 of Table 300).

[0183] At time T4, curve 712 is in the middle position between logic 0 and logic 1. The change of curve 712 from logic 0 to logic 1 causes latch circuit 602 to latch the previous state of control signal SLP2 (for logic 1) and curve 716 (for logic 0).

[0184] Since curve 716 (e.g., control signal SLPB) changes state at time T3 and within the setup time window Ts (between times T2 and T4), the previous state of curve 716 was logic 0, and the previous state of control signal SLP2 was logic 1. In other words, the states of curve 716 (e.g., logic 0) and control signal SLP2 (e.g., logic 1) between times T2 and T4 correspond to their previous states.

[0185] At time T5, curve 712 is logic 1, which puts the power management circuit 100 into power management mode, thereby putting the memory circuit 104 into sleep (hold) mode (e.g., row 4 of Table 300).

[0186] Between time T5 and T6, memory circuit 104 is in sleep mode (hold) (e.g., row 4 of Table 300).

[0187] At time T7, curve 712 begins to transition from logic 1 to logic 0, thereby causing power management circuit 100 to switch out of power management mode.

[0188] After time T7, curve 712 is logic 0, and power management circuit 100 exits power management mode. In some embodiments, after time T7, curve 716 transitions to logic 1, causing power management circuit 100 to return to normal mode. In some embodiments, the transitions of curves 712 and 716 after time T7 cause control signals SLP_VDD and SLP_VDDM to transition from logic 1 to logic 0, thereby causing memory circuit 104 to enter normal mode. For example, in some embodiments, the transitions of curves 712 and 716 after time T7 correspond to the transitions from row 4 to row 1 of the entries shown in Table 400.

[0189] Figure 7B This is a diagram of waveform 700B of a circuit according to some embodiments. Waveform 700B is an example of power management circuitry 100 and circuitry 600 entering a power management mode, thereby causing memory circuitry 104 to enter a shutdown mode (non-holding state). In some embodiments, waveform 700B illustrates a transition from a normal mode (e.g., row 1 in Table 300) to a shutdown mode (e.g., row 5 in Table 300).

[0190] At time T1, curve 720 represents logic 1, curve 722 represents logic 0, curve 724 represents logic 1, curve 726 represents logic 1, and memory circuit 104 is in normal mode (e.g., Figure 3 (The first row in Table 300). For example, in some embodiments, curves 720, 722, 724, and 726 at time T1 correspond to the first row of the entries shown in Table 300.

[0191] At time T1, curves 724 and 726 begin to transition from logic 1 to logic 0.

[0192] At time T3, curves 724 and 726 complete the transition to logic 0, which causes the control signals SLP_VDD and SLP_VDDM to change from logic 0 to logic 1, thereby putting circuit 100 or 600 into shutdown mode (e.g., row 3 of Table 300).

[0193] At time T3, curve 722 begins to transition from logic 0 to logic 1, thereby causing power management circuit 100 to switch to power management mode. In some embodiments, the power management mode of power management circuit 100 is an off (non-holding mode) state (e.g., row 5 of Table 300).

[0194] At time T4, curve 722 is located midway between logic 0 and logic 1. The change of curve 722 from logic 0 to logic 1 causes latch circuit 602 to latch the control signal SLP2 (logic 1) and the previous state of curve 726 (logic 0), and causes latch circuit 222 to latch the control signal SD2 (logic 1) and the previous state of curve 724 (logic 0). This is at least due to the above... Figure 7A For a similar reason, the state of curve 726 (e.g., logic 0) and control signal SLP2 (e.g., logic 1) between time T2 and T4 correspond to the previous state.

[0195] Since curve 724 (e.g., control signal SDB) changes state at time T3 and within the setup time window Ts (between times T2 and T4), the previous state of curve 724 was logic 0, and the previous state of control signal SD2 was logic 1. In other words, the state of curve 724 (e.g., logic 0) and control signal SD2 (e.g., logic 1) between times T2 and T4 correspond to the previous states.

[0196] At time T5, curve 722 is logic 1, which puts the power management circuit 100 in power management mode, thereby putting the memory circuit 104 in off (non-holding) mode (e.g., row 5 of Table 300).

[0197] Between time T5 and T6, memory circuit 104 is in a shutdown mode (non-holding) (e.g., row 5 of Table 300).

[0198] At time T7, curve 722 begins to transition from logic 1 to logic 0, thereby causing power management circuit 100 to switch out of power management mode.

[0199] After time T7, curve 722 is logic 0, and power management circuit 100 exits power management mode. In some embodiments, after time T7, curves 724 and 726 transition to logic 1, causing power management circuit 100 to return to normal mode. In some embodiments, the transitions of curves 722, 724, and 726 after time T7 cause control signals SD_VDDM, SLP_VDD, and SLP_VDDM to transition from logic 1 to logic 0, thereby causing memory circuit 104 to enter normal mode. For example, in some embodiments, the transitions of curves 722, 724, and 726 after time T7 correspond to the transitions from row 5 to row 1 of the entries shown in Table 400.

[0200] circuit

[0201] Figure 8 This is a circuit diagram of circuit 800 according to some embodiments.

[0202] Circuit 800 is Figure 2 A variation of circuit 200 is used, therefore a similar detailed description is omitted. (And...) Figure 2 Compared to circuit 200, circuit 800 does not include the control signal SDB, and Figure 2 The function of the control signal SDB is implemented in circuit 800 by using the control signal PISO.

[0203] In some embodiments, by removing the control signal SDB, Figure 2 The function of the control signal SDB is implemented in circuit 800 using the control signal PISO. For example, in some embodiments, when PISO is enabled or is logic 1, the control signal PISO makes the control signals SLP_VDD and SLP_VDDM logic 1, thereby putting the memory circuit 104 into sleep mode (hold mode).

[0204] and Figure 2 Compared to circuit 200, circuit 800 does not include level shifter circuit 112. Figure 2 Compared to circuit 200, Figure 8 Inverter 108 replaces inverter 108 and NAND logic gate 110. Figure 8 NOR logic gate 804 replaces NOR logic gate 224a, and NAND logic gate 806 replaces inverter 244; therefore, a similar detailed description is omitted. Circuit 800 is... Figure 1 An embodiment of the control circuit 102a.

[0205] Inverter 802 is coupled through node N3 to at least level shifter circuit 114, NOR logic gate 226a, or header circuit 116. Inverter 802 is configured to generate control signal SLP3 in response to control signal SLPB. In some embodiments, control signal SLP3 has a first voltage swing. In some embodiments, control signal SLP3 is inverted from control signal SLPB. Input terminals of inverter 802 are configured to receive control signal SLPB. Output terminals of inverter 802 are coupled to the input of level shifter circuit 114 and the second input terminal of NOR logic gate 226a. Output terminals of inverter 802 are configured to output control signal SLP3 to the input of level shifter circuit 114 and the second input terminal of NOR logic gate 226a. Voltage supply node of inverter 802 is coupled to node N3 and configured to receive a first supply voltage VDD1. In some embodiments, inverter 802 is coupled through node N3 to the drain of PMOS transistor 118.

[0206] Figure 8The NOR logic gate 226a is configured to generate a control signal SLP_VDDB in response to control signals SLP3 and PISO1. In some embodiments, the control signal SLP3 is similar to... Figure 2 The control signal SLP1, therefore Figure 8 The operation of the NOR logic gate 226a is similar to Figure 2 The operation of the NOR logic gate 226a is described, therefore a similar detailed description is omitted. Figure 8 The inverter 226b is configured to generate the control signal SLP_VDD in response to the control signal SLP_VDDB.

[0207] Figure 8 The level shifter circuit 114 is configured to generate a control signal SLP4 in response to a control signal SLP3. In some embodiments, the control signal SLP4 has a second voltage swing. In some embodiments, the control signal SLP3 is similar to... Figure 2 The control signals SD1 and SLP4 are similar to... Figure 2 The control signal SD2 in the middle, therefore Figure 8 The operation of the level shifter circuit 114 is similar to Figure 1-2 The operation of the level shifter circuit 114 is described in detail, therefore a similar detailed description is omitted.

[0208] Figure 8 The latch circuit 122 is configured to generate a control signal SD_VDDM1 in response to the control signal PISO and the control signal SLP4. In some embodiments, the control signal SLP4 is similar to... Figure 2 The control signal SD2, therefore Figure 8 The operation of latch circuit 122 is similar to Figure 1-2 The operation of the latch circuit 122 is omitted here, so a similar detailed description is omitted.

[0209] NOR logic gate 804 is coupled between inverter 224b and level shifter circuit 114. NOR logic gate 804 is configured to generate control signal PISOB2 in response to control signals PISO and SLP4. In some embodiments, control signal PISOB2 has a second voltage swing. In some embodiments, control signal PISOB2 is inverted from control signal PISO. In some embodiments, control signal PISOB2 is equal to control signal PISOB. The input terminal of NOR logic gate 804 is configured to receive control signal PISOB. The input terminal of NOR logic gate 804 is coupled to the output terminal of level shifter circuit 114 and is configured to receive control signal SLP4. The output terminal of NOR logic gate 804 is coupled to... Figure 8The input terminal of inverter 224b is configured to output the control signal PISOB2 to the input terminal of inverter 224b. The voltage supply node (unlabeled) of NOR logic gate 804 is configured to receive the second supply voltage VDDM1.

[0210] NAND logic gate 806 is coupled between latch circuit 122 and inverter 246. NAND logic gate 806 is configured to generate a control signal SD_VDDM1B' in response to control signal PISO and control signal SD_VDDM1. In some embodiments, control signal SD_VDDM1B' has a second voltage swing. The input terminal of NAND logic gate 806 is configured to receive control signal PISO. The input terminal of NAND logic gate 806 is coupled to the output terminal of latch circuit 122 and is configured to receive control signal SD_VDDM1. The output terminal of NAND logic gate 806 is coupled to... Figure 8 The input terminal of inverter 246 is configured to output the control signal SD_VDDM1B' to the input terminal of inverter 246. The voltage supply node (unlabeled) of NAND logic gate 806 is configured to receive the second supply voltage VDDM1.

[0211] Figure 8 The inverter 224b is configured to generate a control signal SLP_VDDM in response to the control signal PISOB2. In some embodiments, the control signal SLP_VDDM is inverted from the control signal PISOB2. In some embodiments, the control signal SLP_VDDM is a delayed version of the control signal PISOB2. In some embodiments, the control signal PISOB2 is similar to... Figure 2 The control signal SLP_VDDMB, therefore Figure 8 The operation of the inverter 224b is similar to Figure 2 The operation of the inverter 224b is described in detail, therefore a similar detailed description is omitted.

[0212] Truth table

[0213] Figure 9 According to some embodiments Figure 1 Circuit 100, or Figure 8 Truth table 900 for circuit 800. Values ​​and formats of table 900 are provided as examples, and other values ​​and / or formats of table 900 are within the scope of this disclosure.

[0214] like Figure 9As shown in the first row of the truth table 900, if the control signal PISO is logic 0 and the control signal SLPB is logic 1, then the power management circuit 102 or the circuit 800 sets the control signals SLP_VDD, SLP_VDDM and SD_VDDM to logic 0 respectively, thereby putting the memory circuit 104 into normal mode.

[0215] like Figure 9 As shown in the second row of the truth table 900, if the control signal PISO is logic 0 and the control signal SLPB is logic 0, then the power management circuit 102 or the circuit 800 sets the control signals SLP_VDD and SLP_VDDM to logic 1 and the control signal SD_VDDM to logic 0, thereby putting the memory circuit 104 into sleep mode (hold mode).

[0216] like Figure 9 As shown in rows 3 and 4 of the truth table 900, when the control signal PISO is logic 1, the memory circuit 104 is automatically put into sleep mode (hold mode) or off mode (non-hold mode), thereby reducing the power consumption of at least circuit 100 or 800.

[0217] like Figure 9 As shown in row 3 of truth table 900, if control signal PISO is logic 1 and control signal SLPB is logic 1, then power management circuit 102 or circuit 800 sets control signals SLP_VDD and SLP_VDDM to logic 1 respectively, and control signal SD_VDDM to logic 0, thereby putting memory circuit 104 into sleep mode (hold mode). In some embodiments, at least for row 3 of truth table 900, when signal SD2 is... Figure 8 The latching circuit 122 latches and the first supply voltage VDD1 is controlled by the control circuit 1200. Figure 12 After being turned off, the control signal SLPB is in a floating or high-impedance state (Z*), thereby at least making Figure 8 The level shifter circuit 114 in the middle is disabled.

[0218] like Figure 9 As shown in row 4 of truth table 900, if control signal PISO is logic 1 and control signal SDB is logic 0, then power management circuit 102 or circuit 800 sets each of control signals SLP_VDD, SLP_VDDM, and SD_VDDM to logic 1, thereby putting memory circuit 104 in a shutdown mode (non-holding mode). In some embodiments, at least for row 4 of truth table 900, when signal SD2 is... Figure 8 The latching circuit 122 latches and the first supply voltage VDD1 is controlled by the control circuit 1200. Figure 12After being turned off, the control signal SLPB is in a floating or high-impedance state (Z*), thereby... Figure 8 The level shifter circuit 114 in the middle is disabled.

[0219] waveform

[0220] Figures 10A-10B This is a diagram of waveforms 1000A-1000B of a circuit according to some embodiments. In some embodiments, waveforms 1000A-1000B correspond to... Figure 1 Circuit 100, or Figure 8 The waveform of circuit 800.

[0221] Waveform 1000A includes curves 1010, 1012, and 1016 of the signal in circuit 100 or 800 for sleep mode (hold).

[0222] In some embodiments, at least curve 1010 or 1020 represents Figure 1 and Figure 8 The first supply voltage VDD1; at least curve 1012 or 1022 indicates Figure 1 and Figure 8 The control signal PISO; and at least curve 1016 or 1026 representing Figure 1 and Figure 8 The control signal SLPB.

[0223] At time T1, curve 1014 represents logic 1, and curve 1012 represents logic 0.

[0224] At time T3, curve 1012 transitions from logic 0 to logic 1, which causes control signals SLP_VDD and SLP_VDDM to transition from logic 0 to logic 1, thereby putting memory circuit 104 into sleep mode (hold). For example, in some embodiments, this transition of curve 1012 corresponds to the transition from row 1 to row 3 of the entries shown in Table 900.

[0225] At time T5, curve 1012 represents logic 1.

[0226] Between time T5 and T6, memory circuit 104 is in sleep mode (hold).

[0227] At time T7, curve 1012 transitions from logic 1 to logic 0. In some embodiments, the transition of curve 1012 from logic 1 to logic 0 causes control signals SLP_VDD and SLP_VDDM to transition from logic 1 to logic 0, thereby causing memory circuit 104 to enter normal mode. For example, in some embodiments, this transition of curve 1012 corresponds to the transition from row 3 to row 1 of the entries shown in Table 900.

[0228] After time T7, curve 1012 is logic 0.

[0229] Waveform 1000B includes curves 1020, 1022, and 1026 for signals in circuit 100 or 800 in off mode (non-holding).

[0230] At time T1, curve 1022 is logic 0, and curve 1024 changes from logic 1 to logic 0.

[0231] At time T3, curve 1024 is logic 0, and curve 1022 transitions from logic 0 to logic 1. This causes the control signals SLP_VDD, SLP_VDDM, and SD_VDDM to transition from logic 0 to logic 1, thereby putting memory circuit 104 into a shutdown mode (non-holding). For example, in some embodiments, this transition of curves 1022 and 1024 corresponds to the transitions from row 1 to row 4 of the entries shown in Table 900.

[0232] At time T5, curve 1022 represents logic 1.

[0233] Between time T5 and T6, memory circuit 104 is in the off mode (non-retained).

[0234] At time T7, curve 1022 transitions from logic 1 to logic 0. In some embodiments, the transition of curve 1022 from logic 1 to logic 0 causes control signals SLP_VDD and SLP_VDDM to transition from logic 1 to logic 0, thereby causing memory circuit 104 to enter a normal mode. For example, in some embodiments, this transition of curve 1022 corresponds to the transition from row 4 to row 1 of the entries shown in Table 900. In some embodiments, the transition of curve 1022 from logic 1 to logic 0 and the transition of curve 1026 from logic 0 to logic 1 cause control signal SD_VDDM to transition from logic 1 to logic 0, thereby causing memory circuit 104 to enter a sleep mode. For example, in some embodiments, this transition of curve 1022 corresponds to the transition from row 4 to row 2 of the entries shown in Table 900.

[0235] After time T7, curve 1022 is logic 0.

[0236] Horizontal shifter circuit

[0237] Figure 11 This is a circuit diagram of a level shifter circuit 1100 according to some embodiments.

[0238] The level shifter circuit 1100 is an embodiment of at least level shifter circuits 106, 112, 114, 206 or 506, and similar detailed descriptions are omitted.

[0239] The level shifter circuit 1100 is configured to receive the signal LSin and generate the signal LSout. The level shifter circuit 1100 is a level shifter circuit configured to shift the signal from a first voltage domain VXX using a supply voltage VXX1 to a second voltage domain VYY using a supply voltage VYY1.

[0240] In some embodiments, the first voltage domain VXX is the voltage domain VDD, the supply voltage VXX1 is the supply voltage VDD1, the second voltage domain VYY is the voltage domain VDDM, and the supply voltage VYY1 is the supply voltage VDDM1. The level shifter circuit 1100 is configured to shift a signal from the voltage domain VDD using the supply voltage VDD1 to the voltage domain VDDM using the supply voltage VDDM1. For example, in these embodiments, the level shifter circuit 1100 is at least an embodiment of level shifter circuit 112 or 114, and similar detailed descriptions are omitted. For example, in these embodiments, when the level shifter circuit 1100 is an embodiment of level shifter circuit 112, the signal LSin corresponds at least to the control signal SLP1, and the signal LSout corresponds at least to the control signal SLP2. For example, in these embodiments, when the level shifter circuit 1100 is an embodiment of level shifter circuit 114, the signal LSin corresponds at least to the control signal SD1 or SLP3, and the signal LSout corresponds at least to the control signal SD2 or SLP4.

[0241] In some embodiments, the first voltage domain VXX is the voltage domain VDDM, the supply voltage VXX1 is the supply voltage VDDM1, the second voltage domain VYY is the voltage domain VDD, and the supply voltage VYY1 is the supply voltage VDD1. The level shifter circuit 1100 is configured to shift a signal from the voltage domain VDDM using the supply voltage VDDM1 to the voltage domain VDD using the supply voltage VDD1. For example, in these embodiments, the level shifter circuit 1100 is at least an embodiment of level shifter circuit 106, 206, or 506, and similar detailed descriptions are omitted. For example, in these embodiments, when the level shifter circuit 1100 is an embodiment of level shifter circuit 106, the signal LSin corresponds at least to the control signal PISO, and the signal LSout corresponds at least to the control signal PISO1. For example, in these embodiments, when the level shifter circuit 1100 is an embodiment of level shifter circuit 206, the signal LSin corresponds at least to the control signal PISOB, and the signal LSout corresponds at least to the control signal PISOB1. For example, in these embodiments, when the level shifter circuit 1100 is an embodiment of the level shifter circuit 506, the signal LSin corresponds at least to the signal preQ, and the signal LSout corresponds at least to the control signal QBvdd.

[0242] Level shifter circuit 1100 is configured to receive signal LSin at an input terminal (unlabeled) and output signal LSout at an output terminal (unlabeled). Signal LSin corresponds to the input signal of level shifter circuit 1100, and signal LSout corresponds to the output signal of level shifter circuit 1100. Level shifter circuit 1100 is configured to generate signal LSout based on signal LSin.

[0243] The signal LSout corresponds to a level-shifted version of the signal LSin. In some embodiments, the voltage level of the signal LSin of the level shifter circuit 1100 is less than the voltage level of the signal LSout of the level shifter circuit 1100. In some embodiments, the voltage level of the signal LSin of the level shifter circuit 1100 is greater than the voltage level of the signal LSout of the level shifter circuit 1100.

[0244] The level shifter circuit 1100 includes an inverter 1102, an NMOS transistor 1104, a PMOS transistor 1106, a PMOS transistor 1108, a PMOS transistor 1110, a PMOS transistor 1112, an NMOS transistor 1114, and an inverter 1116.

[0245] The input terminal of inverter 1102 is configured to receive the signal LSin. Each of the input terminal of inverter 1102, the gate terminal of PMOS transistor 1106, and the gate terminal of NMOS transistor 1104 is coupled to each other. The output terminal of inverter 1102 is configured to output the signal LSBin. In some embodiments, the signal LSBin is the inverted form of the signal LSin. Inverter 1102 is configured to generate the signal LSBin based on the signal CKPI. Inverter 1102 is coupled to a voltage supply VXX. In some embodiments, inverter 1102 is a CMOS inverter type coupled to both the voltage supply VXX and a reference voltage supply VSS.

[0246] The gate terminal of NMOS transistor 1104 is configured to receive the signal LSin. The source terminal of NMOS transistor 1104 is coupled to the reference voltage supply VSS. Each of the drain terminal of NMOS transistor 1104, the drain terminal of PMOS transistor 1106, the gate terminal of PMOS transistor 1110, and the input terminal of inverter 1116 is coupled together at node 11-N1.

[0247] The gate terminal of PMOS transistor 1106 is configured to receive the signal LSin. The source terminal of PMOS transistor 1106 is coupled to the drain terminal of PMOS transistor 1108.

[0248] The source terminal of PMOS transistor 1108 is coupled to a voltage supply VYY. Each of the gate terminal of PMOS transistor 1108, the drain terminal of NMOS transistor 1114, and the drain terminal of PMOS transistor 1112 is coupled to each other at nodes 11-N2. The gate terminal of PMOS transistor 1108 is configured to receive the voltage at nodes 11-N2. In some embodiments, PMOS transistor 1108 is turned on or off based on the voltage at nodes 11-N2.

[0249] NMOS transistor 1104, PMOS transistor 1106, and PMOS transistor 1108 are configured to set the voltage at node 11-N1 corresponding to the signal LSBout. For example, in some embodiments, if NMOS transistor 1104 is turned on, it is configured to pull node 11-N1 towards a reference voltage VSS. For example, in some embodiments, if PMOS transistors 1106 and 1108 are turned on, they are configured to pull node 11-N1 towards a supply voltage VYY1.

[0250] The source terminal of PMOS transistor 1110 is coupled to a voltage supply VYY. The drain terminal of PMOS transistor 1110 is coupled to the source terminal of PMOS transistor 1112. The gate terminal of PMOS transistor 1110 is coupled to at least nodes 11-N1. The voltage at nodes 11-N1 corresponds to the signal LSBout. The gate terminal of PMOS transistor 1110 is configured to receive the signal LSBout. In some embodiments, PMOS transistor 1110 is turned on or off based on the voltage at nodes 11-N1 corresponding to the signal LSBout.

[0251] The gate terminal of PMOS transistor 1112 is configured to receive the signal LSBin from inverter 1102. Each of the gate terminals of PMOS transistor 1112, NMOS transistor 1114, and inverter 1102 is coupled to each other.

[0252] The gate terminal of NMOS transistor 1114 is configured to receive the signal LSBin from inverter 1102. The source terminal of NMOS transistor 1114 is coupled to the reference voltage supply VSS.

[0253] NMOS transistor 1114, PMOS transistor 1110, and PMOS transistor 1112 are configured to set the voltage at node 11-N1 corresponding to the signal LSBout. For example, in some embodiments, if NMOS transistor 1114 is turned on, it is configured to pull node 11-N2 towards a reference voltage VSS. For example, in some embodiments, if PMOS transistors 1110 and 1112 are turned on, they are configured to pull node 11-N2 towards a supply voltage VYY1.

[0254] The input terminal of inverter 1116 is configured to receive the signal LSBout from node 11-N1. The output terminal of inverter 1116 is configured to output the signal LSout. In some embodiments, the signal LSout is an inverted version of the signal LSBout. Inverter 1116 is configured to generate the signal LSout based on the signal LSBout. Inverter 1116 is coupled to a voltage supply VYY. In some embodiments, inverter 1116 is a CMOS inverter type coupled to the voltage supply VYY and a reference voltage VSS. The signal LSout corresponds to the output signal of level shifter circuit 1100. The signal LSout is a level-shifted version of the signal LSin.

[0255] Other configurations and types of level shifters for the level shifter circuit 1100 are within the scope of this disclosure.

[0256] Figure 12 This is a circuit diagram of circuit 1200 according to some embodiments.

[0257] Circuit 1200 is configured to turn off or on the supply voltage VDD provided to circuits 100, 200, 500, 600, 800 and 1100.

[0258] Circuit 1200 includes a PMOS transistor 1202 coupled to node N9. In some embodiments, PMOS transistor 1202 is configured to provide a supply voltage VDD1 to node N9 when turned on or enabled by a control signal CS. In some embodiments, PMOS transistor 1202 is configured not to provide the supply voltage VDD1 to node N9 when turned off or disabled by the control signal CS. In some embodiments, the control signal CS is a control signal PISO. In some embodiments, the control signal CS is a delayed version of the control signal PISO.

[0259] For example, in some embodiments, if the control signal CS is logic 0, the PMOS transistor 1202 is turned on and pulls node N9 to the supply voltage VSS1. In some embodiments, when the control signal PISO is logic 0, the control signal is logic 0, thereby causing the power management circuit 100 to be out of power management mode.

[0260] For example, in some embodiments, if the control signal CS is logic 1, the PMOS transistor 1202 is turned off, and the PMOS transistor 1202 does not supply the supply voltage VSS to node N9. In some embodiments, when the control signal PISO is logic 1, the control signal is logic 1, thereby putting the power management circuit 100 into power management mode.

[0261] The source terminal of PMOS transistor 1202 is configured as a voltage supply node to receive a supply voltage VDD1 from a voltage supply VDD. The gate terminal of PMOS transistor 1202 is configured to receive a control signal CS. In some embodiments, the control signal CS turns PMOS transistor 1202 on or off.

[0262] The drain terminal of PMOS transistor 1202 is coupled to node N9. In some embodiments, the drain terminal of PMOS transistor 1202 is coupled to... Figure 1-2 , Figure 5-6 and Figure 8 Nodes N1 and N7 in the diagram. In some embodiments, the drain terminal of PMOS transistor 1202 is coupled to at least the voltage supply node of OR logic gate 126, inverter 242, inverter 226b, NOR logic gate 226a, level shifter circuit 106, level shifter circuit 206, level shifter circuit 506, or level shifter circuit 1100.

[0263] method

[0264] Figure 13 This is a flowchart of a method for operating circuitry according to some embodiments, such as corresponding ones. Figure 1 , Figure 2 , Figure 5-6 , Figure 8 or Figure 11-12 Circuits of 100-200, 500-600, 800, or 1100-1200. It should be understood that... Figure 13 Additional operations are performed before, during, and / or after method 1300 as described herein, and some other processing may be described only briefly. It should be understood that method 1300 utilizes the corresponding... Figure 1-2 , Figure 5-6 , Figure 8 or Figure 11-12The characteristics of one or more of the circuits 100-200, 500-600, 800, or 1100-1200, or the corresponding Figure 3 or Figure 9 One or more features of truth table 300 or 900, or the corresponding Figures 4A-4D , Figures 7A-7B or Figures 10A-10B One or more characteristics of the waveform 400A-400D, 700A-700B or 1000A-1000B.

[0265] In operation 1302 of method 1300, at least a first control signal (PISO), a second control signal (SLPB), or a third control signal (SDB) is received by a power control circuit (circuit 100, 102, or 102a). In some embodiments, the power control circuit of method 1300 is coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage.

[0266] In operation 1304 of method 1300, the first output control signal (SD_VDDM), the second output control signal (SLP_VDDM), and the third output control signal (SLP_VDD) are generated by the power control circuit in response to at least the first control signal (PISO), the second control signal (SLPB), or the third control signal (SDB). In some embodiments, at least the first voltage (VDDM1) or the first control signal (PISO) has a first voltage swing (VDDM), and at least the second voltage (VDD1), the second control signal (SLPB), or the third control signal (SDB) has a second voltage swing (VDD) different from the first voltage swing.

[0267] In operation 1306 of method 1300, at least a first supply voltage (VDDAI), a second supply voltage (VDDMH), or a third supply voltage (VDDH) is provided by the head circuit in response to at least a first output control signal, a second output control signal, or a third output control signal.

[0268] In operation 1308 of method 1300, the power control circuit enters a power management mode in response to a first value (1) of the first control signal (PISO). In some embodiments, the power management mode has a first power reduction state and a second power reduction state. In some embodiments, operation 1308 of entering the power management mode includes: at least in response to a first supply voltage (VDDAI) or the first control signal (PISO), shutting off the second voltage supply (VDD) and placing the memory circuit in the first power reduction state or the second power reduction state. In some embodiments, the memory circuit is coupled to the power control circuit and the first header circuit.

[0269] In some embodiments, the memory circuit is placed in a first reduced power state or a second reduced power state in response to at least a first supply voltage (VDDAI) or a first control signal (PISO). This includes placing the memory circuit in a second reduced power state in response to a first output control signal (SD_VDDM) having a first logic value (1), or placing the memory circuit in a first reduced power state in response to a first output control signal (SD_VDDM) having a second logic value (0). In some embodiments, the second reduced power state corresponds to a shutdown mode of the memory circuit, the first reduced power state corresponds to a sleep mode of the memory circuit, and the first logic value is different from the second logic value.

[0270] In operation 1310 of method 1300, the power control circuit exits the power management mode and enters a normal mode in response to a second value (0) of the first control signal (PISO). The power management mode has a normal power state, a first reduced power state, and a second reduced power state, the second value being the opposite of the first value. In some embodiments, operation 1310 of exiting the power management mode includes turning on the second voltage supply (VDD).

[0271] In some embodiments, the operation 1310 of exiting the power management mode of the power control circuit further includes: causing the memory circuit to be in a first reduced power state in response to the third output control signal (SLP_VDD) and the second output control signal (SLP_VDDM) having a first logic value (1) and the first control signal (PISO) and the first output control signal (SD_VDDM) having a second logic value (0); causing the memory circuit to be in a second reduced power state in response to the first control signal (PISO) having a second logic value (0) and the first output control signal (SD_VDDM), the second output control signal (SLP_VDDM) and the third output control signal (SLP_VDD) having a first logic value (1); or causing the memory circuit to be in a normal power state in response to the first control signal (PISO), the first output control signal (SD_VDDM), the second output control signal (SLP_VDDM) and the third output control signal (SLP_VDD) having a second logic value (0).

[0272] In some embodiments, a normal power state corresponds to a normal power mode of the memory circuit. In some embodiments, a first reduced power state corresponds to a sleep mode of the memory circuit, and a first logic value differs from a second logic value. In some embodiments, a second reduced power state corresponds to a shutdown mode of the memory circuit.

[0273] In some embodiments, the first logical value is logical high. In some embodiments, the first logical value is logical low.

[0274] In some embodiments, one or more operations of method 1300 are not performed. Despite the above references Figure 1-2 Method 1300 has been described, but it should be understood that method 1300 utilizes... Figure 3-12 Features of one or more of them. In some of these embodiments, it will be with Figure 3-12 The circuits 300-1200 are described and operated in accordance with the other operations of method 1300.

[0275] Furthermore, for illustrative purposes, Figure 1-13 The various PMOS or NMOS transistors shown have specific dopant types (e.g., N-type or P-type). The embodiments of this disclosure are not limited to specific transistor types, and... Figure 1-13 One or more of the PMOS or NMOS transistors shown may be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. Embodiments of this disclosure are not limited to specific logic values ​​at which signals are activated and / or deactivated. Different logic values ​​are chosen within the scope of various embodiments.

[0276] Different numbers of inverters are selected in circuits or methods 100-1200 within the range of various embodiments. Different numbers of circuit elements are selected in circuits or methods 100-1200 within the range of various embodiments.

[0277] One aspect of this specification relates to a circuit. The circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to provide a first supply voltage, a second supply voltage, and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit and is in either the first state or the second state, at least in response to the first supply voltage provided by the power management circuit.

[0278] Another aspect of this specification relates to a circuit. The circuit includes a power control circuit and a first head circuit. The power control circuit is coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage. The power control circuit is configured to generate a first output control signal, a second output control signal, and a third output control signal in response to at least a first control signal, a second control signal, or a third control signal. At least the first voltage or the first control signal has a first voltage swing, and at least the second voltage, the second control signal, or the third control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power control circuit to enter a power management mode having a first reduced power state and a second reduced power state. The first head circuit is coupled to the power control circuit and is configured to provide at least a first supply voltage, a second supply voltage, or a third supply voltage in response to at least the first output control signal, the second output control signal, or the third output control signal. In some embodiments, the power management mode includes the second voltage supply being turned off.

[0279] Another aspect of this specification relates to a method of operating a circuit. The method includes receiving at least a first control signal, a second control signal, or a third control signal by a power control circuit coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage. The method further includes generating a first output control signal, a second output control signal, and a third output control signal by the power control circuit in response to at least the first control signal, the second control signal, or the third control signal, wherein at least the first voltage or the first control signal has a first voltage swing, and at least the second voltage, the second control signal, or the third control signal has a second voltage swing different from the first voltage swing. The method also includes providing at least a first supply voltage, a second supply voltage, or a third supply voltage by a head circuit in response to at least the first output control signal, the second output control signal, or the third output control signal. The method further includes causing the power control circuit to enter a power management mode in response to a first value of the first control signal, the power management mode having a first power reduction state and a second power reduction state. In some embodiments, putting the power control circuit into a power management mode includes shutting off the second voltage supply; and putting the memory circuit into a first reduced power state or a second reduced power state in response to at least the first supply voltage or the first control signal, the memory circuit being coupled to the power control circuit and the first head circuit.

[0280] Several embodiments have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of this disclosure. For example, various transistors (e.g., N-type or P-type metal-oxide-semiconductor (NMOS or PMOS)) shown as having specific dopant types are for illustrative purposes. Embodiments of this disclosure are not limited to specific types. Different dopant types are selected for specific transistors within the scope of various embodiments. The low or high logic values ​​of various signals used in the above description are also for illustrative purposes. Various embodiments are not limited to specific logic values ​​when signals are activated and / or deactivated. Different logic values ​​are selected within the scope of various embodiments. In various embodiments, the transistor is used as a switch. Switching circuits used instead of transistors are within the scope of various embodiments. In various embodiments, the source of the transistor can be configured as the drain, and the drain can be configured as the source. Thus, the terms source and drain are used interchangeably. Various signals are generated by corresponding circuits, but for simplicity, the circuits are not shown.

[0281] The accompanying figures illustrate capacitive circuits using discrete capacitors. Equivalent circuits can be used. For example, capacitive devices, circuits, or networks (e.g., combinations of capacitors, capacitive elements, devices, circuits, etc.) can be used instead of discrete capacitors. The illustrations above include exemplary steps, but these steps are not necessarily performed in the order shown. Steps may be added, substituted, ordered, and / or eliminated as appropriate, according to the spirit and scope of the disclosed embodiments.

[0282] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0283] Example 1. A circuit comprising: a power management circuit configured to receive a first control signal and a second control signal, and to provide a first supply voltage, a second supply voltage, and a third supply voltage, the first control signal having a first voltage swing, and the second control signal having a second voltage swing different from the first voltage swing, the first control signal causing the power management circuit to enter a power management mode having a first state and a second state; and a memory circuit coupled to the power management circuit and being in either the first state or the second state at least in response to the first supply voltage provided by the power management circuit.

[0284] Example 2. The circuit according to Example 1, wherein the power management circuit further includes: a control circuit configured to generate a first output control signal, a second output control signal, and a third output control signal in response to the first control signal and the second control signal, the first output control signal and the second output control signal having the first voltage swing, and the third output control signal having the second voltage swing; and a first header circuit coupled to the control circuit and the memory circuit, and configured to adjust at least the first supply voltage, the second supply voltage, or the third supply voltage in response to at least the first output control signal, the second output control signal, or the third output control signal.

[0285] Example 3. The circuit according to Example 2, wherein the control circuit includes: a first level shifter circuit coupled to a first voltage supply having a first supply voltage and a second voltage supply having a second supply voltage, the second voltage supply being different from the first voltage supply, and configured to receive the first control signal and generate at least a first level shift signal having the second voltage swing, at least in response to the first control signal; and a second head circuit coupled to at least the level shifter circuit, the first voltage supply and the second voltage supply, and configured to provide the first supply voltage of the first voltage supply to a first voltage supply node in response to the first control signal, and to provide the second supply voltage of the second voltage supply to a second voltage supply node in response to the first level shift signal.

[0286] Example 4. The circuit according to Example 3, wherein the control circuit further includes: a NAND logic gate coupled at least to the second head circuit via the second voltage supply node, the NAND logic gate being configured to generate a NAND control signal in response to the second control signal and the third control signal, the NAND control signal and the third control signal having the second voltage swing, the NAND logic gate including: a first NAND input terminal configured to receive the third control signal; a second NAND input terminal configured to receive the second control signal; and a NAND output terminal configured to output the NAND control signal.

[0287] Example 5. The circuit according to Example 4, wherein the control circuit further includes: a first OR logic gate configured to generate the third output control signal in response to the first level shift signal and the NAND control signal, the first OR logic gate including: a first OR input terminal coupled to the output of the first level shifter circuit and configured to receive the first level shift signal; a second OR input terminal coupled to the NAND output terminal and configured to receive the NAND control signal; and a first OR output terminal configured to output the third output control signal.

[0288] Example 6. The circuit according to Example 5, wherein the control circuit further comprises: a second level shifter circuit coupled to the first voltage supply through the first voltage supply node and coupled to the second voltage supply through the second voltage supply node, the second level shifter circuit being configured to receive the NAND control signal and generate at least a fourth control signal in response to the NAND control signal, the fourth control signal having the first voltage swing; and a second OR logic gate configured to generate a second output control signal in response to the first control signal and the fourth control signal, the second OR logic gate comprising: a third OR input terminal configured to receive the first control signal; a fourth OR input terminal coupled to the output of the second level shifter circuit and configured to receive the fourth control signal; and a second OR output terminal configured to output the second output control signal.

[0289] Example 7. The circuit according to Example 3, wherein the control circuit further includes: an inverter, the inverter being coupled at least to the second head circuit via the second voltage supply node, the inverter being configured to receive a third control signal and generate a fourth control signal in response to the third control signal, the fourth control signal and the third control signal having the second voltage swing, the inverter including: an input terminal of the inverter configured to receive the third control signal; and an output terminal of the inverter configured to output the fourth control signal.

[0290] Example 8. The circuit according to Example 7, wherein the control circuit further includes: a second level shifter circuit coupled to the first voltage supply through the first voltage supply node and coupled to the second voltage supply through the second voltage supply node, the second level shifter circuit being configured to receive the fourth control signal and to generate at least a fifth control signal in response to the fourth control signal, the fifth control signal having the first voltage swing.

[0291] Example 9. The circuit according to Example 8, wherein the control circuit further includes: a latch circuit coupled to the output of the second level shifter circuit and configured to generate the first output control signal in response to the first control signal and the fourth control signal, the latch circuit including: a first latch input terminal coupled to the output of the second level shifter circuit and configured to receive the fourth control signal; a second latch input terminal configured to receive the first control signal; and a latch output terminal configured to output the first output control signal, the first output control signal corresponding to a previous state of the fourth control signal.

[0292] Example 10. A circuit comprising: a power control circuit coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage, the power control circuit being configured to generate a first output control signal, a second output control signal, and a third output control signal in response to at least a first control signal, a second control signal, or a third control signal, wherein at least the first voltage or the first control signal has a first voltage swing, and at least the second voltage, the second control signal, or the third control signal has a second voltage swing different from the first voltage swing, the first control signal causing the power control circuit to enter a power management mode having a first power reduction state and a second power reduction state; and a first header circuit coupled to the power control circuit and configured to provide at least a first supply voltage, a second supply voltage, or a third supply voltage in response to at least the first output control signal, the second output control signal, or the third output control signal, wherein the power management mode includes the second voltage supply being turned off.

[0293] Example 11. The circuit according to Example 10 further includes: a memory circuit coupled to the power control circuit and the first header circuit, and at least in response to the first supply voltage or the power control circuit entering the power management mode, being in the first reduced power state or the second reduced power state.

[0294] Example 12. The circuit according to Example 11, wherein the first head circuit comprises: a first P-type transistor having a source coupled to the first voltage supply, the gate of the first P-type transistor being configured to receive the first output control signal, and the drain of the first P-type transistor being coupled to the memory circuit via a first node, the first P-type transistor being configured to provide the first supply voltage to the memory circuit; a second P-type transistor having a source coupled to the second voltage supply, the gate of the second P-type transistor being configured to receive the second output control signal, and the drain of the second P-type transistor being coupled to the memory circuit via a second node, the second P-type transistor being configured to provide the second supply voltage to the memory circuit; and a third P-type transistor having a source coupled to the second voltage supply, the gate of the third P-type transistor being configured to receive the third output control signal, and the drain of the third P-type transistor being coupled to the memory circuit via a third node, the third P-type transistor being configured to provide the third supply voltage to the memory circuit.

[0295] Example 13. The circuit according to Example 12, wherein the memory circuit includes: a memory cell array coupled to the first P-type transistor via the first node, configured to store data and configured to receive the first supply voltage from the first node; a first peripheral circuit coupled to the memory cell array and the second P-type transistor and configured to receive the second supply voltage from the second node; and a second peripheral circuit coupled to the memory cell array and the third P-type transistor and configured to receive the third supply voltage from the third node.

[0296] Example 14. The circuit according to Example 13 further includes: an output circuit coupled to the memory cell array and the control circuit, and configured to clamp a first data signal on a fourth node, the first data signal having a second voltage swing in response to the first output control signal, the first output control signal having the first voltage swing.

[0297] Example 15. The circuit according to Example 14, wherein the output circuit includes: a buffer circuit coupled to the memory cell array and configured to receive a second data signal and output a third data signal; and a NOR logic gate including: a first NOR input terminal coupled to the output of the buffer circuit and configured to receive the third data signal; a second NOR input terminal coupled to the power control circuit and configured to receive the second output control signal; and a first NOR output terminal configured to output a fourth data signal (preQ).

[0298] Example 16. The circuit according to Example 15, wherein the output circuit further includes: a level shifter circuit coupled to the first voltage supply and the second voltage supply and configured to receive the fourth data signal and generate at least an inverted first data signal having the second voltage swing, at least in response to the fourth data signal; and an inverter including: an input terminal of the inverter coupled to the output of the level shifter circuit and configured to receive the inverted first data signal; and an output terminal of the inverter configured to generate the first data signal.

[0299] Example 17. The circuit according to Example 16, wherein the output circuit further includes: an N-type transistor having a source coupled to a reference voltage supply, the gate of the N-type transistor being coupled to the power control circuit and configured to receive the second output control signal, and the drain of the N-type transistor being coupled to the output terminal of the inverter through the fourth node.

[0300] Example 18. A method of operating a circuit, the method comprising: receiving at least a first control signal, a second control signal, or a third control signal by a power control circuit, the power control circuit being coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage; generating a first output control signal, a second output control signal, and a third output control signal by the power control circuit in response at least to the first control signal, the second control signal, or the third control signal, wherein at least the first voltage or the first control signal has a first voltage swing, and at least the second voltage, the second control signal, or the third control signal has a second voltage swing different from the first voltage swing; and at least by a head circuit... In response to the first output control signal, the second output control signal, or the third output control signal, at least a first supply voltage, a second supply voltage, or a third supply voltage is provided; the power control circuit is caused to enter a power management mode in response to a first value of the first control signal, the power management mode having a first power reduction state and a second power reduction state, wherein causing the power control circuit to enter the power management mode includes: shutting off the second voltage supply; and causing a memory circuit to be in the first power reduction state or the second power reduction state in response to at least the first supply voltage or the first control signal, the memory circuit being coupled to the power control circuit and the head circuit.

[0301] Example 19. The method according to Example 18 further includes: causing the power control circuit to exit the power management mode and enter a normal mode in response to a second value of the first control signal, the power management mode having a normal power state, a first reduced power state, and a second reduced power state, the second value being the opposite of the first value, wherein causing the power control circuit to exit the power management mode includes: turning on the second voltage supply; causing the memory circuit to be in the first reduced power state in response to the third output control signal and the second output control signal having a first logic value, and the first control signal and the first output control signal having a second logic value, the first reduced power state corresponding to a sleep mode of the memory circuit, and the first logic value being different from the second logic value; causing the memory circuit to be in the second reduced power state in response to the first control signal having the second logic value, and the first output control signal, the second output control signal, and the third output control signal having the first logic value, the second reduced power state corresponding to a shutdown mode of the memory circuit; or causing the memory circuit to be in the normal power state in response to the first control signal, the first output control signal, the second output control signal, and the third output control signal having the second logic value, the normal power state corresponding to a normal power mode of the memory circuit.

[0302] Example 20. The method according to Example 18, wherein causing the memory circuit to be in the first reduced power state or the second reduced power state in response to at least the first supply voltage or the first control signal comprises: causing the memory circuit to be in the second reduced power state in response to the first output control signal having a first logic value, the second reduced power state corresponding to a shutdown mode of the memory circuit; or causing the memory circuit to be in the first reduced power state in response to the first output control signal having a second logic value, the first reduced power state corresponding to a sleep mode of the memory circuit, and the first logic value being different from the second logic value.

Claims

1. An integrated circuit comprising: a power management circuit configured to receive a first control signal and a second control signal, and to provide a first supply voltage, a second supply voltage, and a third supply voltage, the first control signal having a first voltage swing, and the second control signal having a second voltage swing different from the first voltage swing, the first control signal causing the power management circuit to enter a power management mode having a first state and a second state; and a memory circuit coupled to the power management circuit, and in the first state or the second state responsive at least to the first supply voltage provided by the power management circuit; wherein the power management circuit comprises a control circuit configured to generate a first output control signal, a second output control signal, and a third output control signal responsive to the first control signal and the second control signal, wherein the control circuit comprises: a first level shifter circuit; and a first head circuit coupled at least to the first level shifter circuit, the first voltage supply, and the second voltage supply, and configured to provide the first supply voltage of the first voltage supply to a first voltage supply node responsive to the first control signal, and to provide the second supply voltage of the second voltage supply to a second voltage supply node responsive to a first level shifted signal, the first level shifted signal being a level shifted version of the first control signal.

2. The circuit of claim 1, wherein, the first output control signal and the second output control signal having the first voltage swing, and the third output control signal having the second voltage swing; and the power management circuit further comprising: a second head circuit coupled to the control circuit and the memory circuit, and configured to adjust at least the first supply voltage, the second supply voltage, or the third supply voltage responsive at least to the first output control signal, the second output control signal, or the third output control signal.

3. The circuit of claim 2, wherein, the first level shifter circuit coupled to the first voltage supply having the first supply voltage, and the second voltage supply having the second supply voltage, the second voltage supply different from the first voltage supply, and configured to receive the first control signal, and to generate at least a first level shifted signal responsive at least to the first control signal, the first level shifted signal having the second voltage swing; and wherein the first head circuit is coupled at least to the first level shifter circuit.

4. The circuit of claim 3, wherein, the control circuit further comprising: a NAND logic gate coupled at least to the first head circuit through the second voltage supply node, the NAND logic gate configured to generate a NAND control signal responsive to the second control signal and a third control signal, the NAND control signal and the third control signal having the second voltage swing, the NAND logic gate comprising: a first NAND input terminal configured to receive the third control signal; a second NAND input terminal configured to receive the second control signal; and a NAND output terminal configured to output the NAND control signal.

5. The circuit of claim 4, wherein, The control circuit further comprises: a first OR logic gate configured to generate the third output control signal in response to the first level shifter signal and the NAND control signal, the first OR logic gate comprising: a first OR input terminal coupled to an output of the first level shifter circuit and configured to receive the first level shifter signal; a second OR input terminal coupled to the NAND output terminal and configured to receive the NAND control signal; and a first OR output terminal configured to output the third output control signal.

6. The circuit of claim 5, wherein, The control circuit further comprises: a second level shifter circuit coupled to the first voltage supply through the first voltage supply node and to the second voltage supply through the second voltage supply node, the second level shifter circuit configured to receive the NAND control signal and to generate at least a fourth control signal in response to at least the NAND control signal, the fourth control signal having the first voltage swing; and a second OR logic gate configured to generate the second output control signal in response to the first control signal and the fourth control signal, the second OR logic gate comprising: a third OR input terminal configured to receive the first control signal; a fourth OR input terminal coupled to an output of the second level shifter circuit and configured to receive the fourth control signal; and a second OR output terminal configured to output the second output control signal.

7. The circuit of claim 3, wherein, The control circuit further comprises: an inverter coupled to at least the first head circuit through the second voltage supply node, the inverter configured to receive a third control signal and to generate a fourth control signal in response to the third control signal, the fourth control signal and the third control signal having the second voltage swing, the inverter comprising: an input terminal of the inverter configured to receive the third control signal; and an output terminal of the inverter configured to output the fourth control signal.

8. The circuit of claim 7, wherein, The control circuit further comprises: a second level shifter circuit coupled to the first voltage supply through the first voltage supply node and to the second voltage supply through the second voltage supply node, the second level shifter circuit configured to receive the fourth control signal and to generate at least a fifth control signal in response to at least the fourth control signal, the fifth control signal having the first voltage swing.

9. The circuit of claim 8, wherein, The control circuit further comprises: a latch circuit coupled to an output of the second level shifter circuit and configured to generate the first output control signal in response to the first control signal and the fourth control signal, The latch circuit includes: a first latch input terminal coupled to an output of the second level shifter circuit and configured to receive the fourth control signal; a second latch input terminal configured to receive the first control signal; and a latch output terminal configured to output the first output control signal, the first output control signal corresponding to a previous state of the fourth control signal.

10. An integrated circuit comprising: a power control circuit coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage, the power control circuit configured to generate a first output control signal, a second output control signal, and a third output control signal in response to at least a first control signal, a second control signal, or a third control signal, at least the first voltage or the first control signal having a first voltage swing, and at least the second voltage, the second control signal, or the third control signal having a second voltage swing different from the first voltage swing, the first control signal causing the power control circuit to enter a power management mode having a first reduced power state and a second reduced power state; and a first head circuit coupled to the power control circuit and configured to provide at least a first supply voltage, a second supply voltage, or a third supply voltage in response to at least the first output control signal, the second output control signal, or the third output control signal, wherein the power management mode includes the second voltage supply being turned off; and wherein the power control circuit includes: a first level shifter circuit; and a second head circuit coupled to at least the first level shifter circuit, the first voltage supply, and the second voltage supply and configured to provide the first supply voltage of the first voltage supply to a first voltage supply node in response to the first control signal and to provide the second supply voltage of the second voltage supply to a second voltage supply node in response to a first level shifted signal, the first level shifted signal being a level shifted version of the first control signal.

11. The circuit of claim 10, further comprising: a memory circuit coupled to the power control circuit and the first head circuit and in at least the first reduced power state or the second reduced power state in response to at least the first supply voltage, or the power control circuit entering the power management mode.

12. The circuit of claim 11, wherein, the first head circuit includes: a first P-type transistor having a source coupled to the first voltage supply, a gate of the first P-type transistor configured to receive the first output control signal, and a drain of the first P-type transistor coupled to the memory circuit through a first node, the first P-type transistor configured to provide the first supply voltage to the memory circuit; a second P-type transistor having a source coupled to the second voltage supply, a gate of the second P-type transistor configured to receive the second output control signal, and a drain of the second P-type transistor coupled to the memory circuit through a second node, the second P-type transistor configured to provide the second supply voltage to the memory circuit; and a third P-type transistor having a source coupled to the third voltage supply, a gate of the third P-type transistor configured to receive the third output control signal, and a drain of the third P-type transistor coupled to the memory circuit through a third node, the third P-type transistor configured to provide the third supply voltage to the memory circuit.

13. The circuit of claim 12, wherein, the memory circuit includes: a memory cell array coupled to the first P-type transistor through the first node, configured to store data, and configured to receive the first supply voltage from the first node; a first peripheral circuit coupled to the memory cell array and the second P-type transistor, and configured to receive the second supply voltage from the second node; and a second peripheral circuit coupled to the memory cell array and the third P-type transistor, and configured to receive the third supply voltage from the third node.

14. The circuit of claim 13, further comprising: an output circuit coupled to the memory cell array and the power control circuit, and configured to clamp a first data signal on a fourth node, the first data signal having the second voltage swing in response to the first output control signal, the first output control signal having the first voltage swing.

15. The circuit of claim 14, wherein, the output circuit includes: a buffer circuit coupled to the memory cell array, configured to receive a second data signal and output a third data signal; and a NOR logic gate including: a first NOR input terminal coupled to an output of the buffer circuit and configured to receive the third data signal; a second NOR input terminal coupled to the power control circuit and configured to receive the second output control signal; and a first NOR output terminal configured to output a fourth data signal (preQ).

16. The circuit of claim 15, wherein, the output circuit further includes: a second level shifter circuit coupled to the first voltage supply and the second voltage supply, and configured to receive the fourth data signal, and to generate at least an inverted first data signal in response to at least the fourth data signal, the inverted first data signal having the second voltage swing; and an inverter including: an input terminal of the inverter coupled to an output of the level shifter circuit, and configured to receive the inverted first data signal; and an output terminal of the inverter configured to generate the first data signal.

17. The circuit of claim 16, wherein, the output circuit further includes: an N-type transistor having a source coupled to a reference voltage supply, a gate of the N-type transistor coupled to the power control circuit and configured to receive the second output control signal, and a drain of the N-type transistor coupled to an output terminal of the inverter through the fourth node.

18. A method of operating a circuit, the method comprising: receiving, by a power control circuit, at least a first control signal, a second control signal, or a third control signal, the power control circuit coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage; generating, by the power control circuit, at least in response to the first control signal, the second control signal, or the third control signal, a first output control signal, a second output control signal, and a third output control signal, at least the first voltage or the first control signal having a first voltage swing, and at least the second voltage, the second control signal, or the third control signal having a second voltage swing different from the first voltage swing; providing, by a first head circuit, at least in response to the first output control signal, the second output control signal, or the third output control signal, at least a first supply voltage, a second supply voltage, or a third supply voltage; providing, by a second head circuit, the first supply voltage of the first voltage supply to a first voltage supply node in response to the first control signal and the second supply voltage of the second voltage supply to a second voltage supply node in response to a first level shift signal, the first level shift signal being a level shifted version of the first control signal, wherein the second head circuit is coupled to at least a first level shifter circuit; entering, by the power control circuit, a power management mode in response to a first value of the first control signal, the power management mode having a first reduced power state and a second reduced power state, wherein entering, by the power control circuit, the power management mode comprises: turning off the second voltage supply; and entering, by a memory circuit, at least in response to the first supply voltage or the first control signal, the first reduced power state or the second reduced power state, the memory circuit coupled to the power control circuit and the first head circuit.

19. The method of claim 18, further comprising: exiting, by the power control circuit, the power management mode into a normal mode in response to a second value of the first control signal, the power management mode having a normal power state, the first reduced power state, and the second reduced power state, the second value opposite the first value, wherein exiting, by the power control circuit, the power management mode comprises: turning on the second voltage supply; causing the memory circuit to be in the first reduced power state in response to the third output control signal and the second output control signal having a first logic value, and the first control signal and the first output control signal having a second logic value, the first reduced power state corresponding to a sleep mode of the memory circuit, and the first logic value being different than the second logic value; causing the memory circuit to be in the second reduced power state in response to the first control signal having the second logic value, and the first output control signal, the second output control signal, and the third output control signal having the first logic value, the second reduced power state corresponding to an off mode of the memory circuit; or causing the memory circuit to be in the normal power state in response to the first control signal, the first output control signal, the second output control signal, and the third output control signal having the second logic value, the normal power state corresponding to a normal power mode of the memory circuit.

20. The method of claim 18, wherein, causing the memory circuit to be in the first reduced power state or the second reduced power state in response to at least the first supply voltage or the first control signal includes: causing the memory circuit to be in the second reduced power state in response to the first output control signal having a first logic value, the second reduced power state corresponding to an off mode of the memory circuit; or causing the memory circuit to be in the first reduced power state in response to the first output control signal having a second logic value, the first reduced power state corresponding to a sleep mode of the memory circuit, and the first logic value being different than the second logic value.

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