Precise tuning of programming of analog neural memories in deep learning artificial neural networks

Abstract

The present invention discloses multiple embodiments of a precision-tuned algorithm and apparatus for accurately and quickly depositing the correct amount of charge on the floating gates of nonvolatile memory cells within a vector-matrix multiplication (VMM) array in an artificial neural network. Thus, a selected cell can be very accurately programmed to hold one of N different values.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. Patent Application No. 16 / 576,533, filed on September 19, 2019, and entitled “PRECISION TUNING FOR THE PROGRAMMING OF ANALOGNEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK.” Technical Field

[0003] The present invention discloses multiple embodiments of a precision-tuned algorithm and apparatus for accurately and quickly depositing the correct amount of charge on the floating gates of nonvolatile memory cells within a vector-matrix multiplication (VMM) array in an artificial neural network. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] Figure 1 An artificial neural network is shown, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the input and be able to learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from the synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e. very high computational parallelism. In principle, such complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used for artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicant previously disclosed an artificial (simulated) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, which is incorporated herein by reference. The non-volatile memory array operates as an analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a spaced-apart source region and a drain region formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed over a second portion of the channel region and insulated from the second portion. Each of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Each nonvolatile memory cell used in an analog neuromorphic memory system must be erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0009] One challenge in a VMM system is being able to program a selected cell with the precision and granularity required for different values ​​of N. For example, if a selected cell can include one of 64 different values, extreme precision is required in the programming operation.

[0010] What are needed are improved programming systems and methods suitable for use with a VMM in an emulated neuromorphic memory system. Summary of the invention

[0011] The present invention discloses multiple embodiments of a precision-tuned algorithm and apparatus for accurately and rapidly depositing the correct amount of charge on the floating gates of nonvolatile memory cells within a vector-matrix multiplication (VMM) array in an artificial neural network. Thus, a selected cell can be very accurately programmed to hold one of N different values. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG. 1 is a schematic diagram showing an artificial neural network of the prior art.

[0013] Figure 2 A prior art split gate flash memory cell is shown.

[0014] Figure 3 Another prior art split gate flash memory cell is shown.

[0015] Figure 4 Another prior art split gate flash memory cell is shown.

[0016] Figure 5 Another prior art split gate flash memory cell is shown.

[0017] Figure 6 Another prior art split gate flash memory cell is shown.

[0018] Figure 7 A prior art stacked gate flash memory cell is shown.

[0019] Figure 8 A schematic diagram showing different levels of an exemplary artificial neural network using one or more non-volatile memory arrays.

[0020] Fig. 9 is a block diagram showing a vector-matrix multiplication system.

[0021] Fig.10 is a block diagram illustrating an exemplary artificial neural network using one or more vector-matrix multiplication systems.

[0022] Fig.11 Another embodiment of a vector-matrix multiplication system is shown.

[0023] Fig.12 Another embodiment of a vector-matrix multiplication system is shown.

[0024] Fig.13 Another embodiment of a vector-matrix multiplication system is shown.

[0025] Fig.14 Another embodiment of a vector-matrix multiplication system is shown.

[0026] Fig.15 Another embodiment of a vector-matrix multiplication system is shown.

[0027] Fig.16 Another embodiment of a vector-matrix multiplication system is shown.

[0028] Fig.17 Another embodiment of a vector-matrix multiplication system is shown.

[0029] Fig.18 Another embodiment of a vector-matrix multiplication system is shown.

[0030] Fig.19 Another embodiment of a vector-matrix multiplication system is shown.

[0031] Fig. 20 Another embodiment of a vector-matrix multiplication system is shown.

[0032] Fig.21 Another embodiment of a vector-matrix multiplication system is shown.

[0033] Fig. 22 Another embodiment of a vector-matrix multiplication system is shown.

[0034] Fig.23 Another embodiment of a vector-matrix multiplication system is shown.

[0035] Fig.24 Another embodiment of a vector-matrix multiplication system is shown.

[0036] Fig.25 A prior art long short term memory system is shown.

[0037] Fig.26 An exemplary cell for use in a long short term memory system is shown.

[0038] Fig. 27 Show Fig.26 An embodiment of an exemplary unit of.

[0039] Fig.28 Show Fig.26 Another embodiment of an exemplary unit of .

[0040] Fig.29 A prior art gate-controlled recursive cell system is shown.

[0041] Fig.30 An exemplary cell for use in a gate-controlled recursive cell system is shown.

[0042] Fig.31 Show Fig.30 An embodiment of an exemplary unit of.

[0043] Fig.32 Show Fig.30 Another embodiment of an exemplary unit of .

[0044] Fig.33A An embodiment of a method of programming a non-volatile memory cell is shown.

[0045] Fig.33B Another embodiment of a method of programming a non-volatile memory cell is shown.

[0046] Fig.34 One implementation of a coarse programming method is shown.

[0047] Fig.35 Exemplary pulses used in programming of nonvolatile memory cells are shown.

[0048] Fig.36 Exemplary pulses used in programming of nonvolatile memory cells are shown.

[0049] Fig.37 A calibration algorithm for programming a non-volatile memory cell is shown that adjusts programming parameters based on the slope characteristics of the cell.

[0050] Fig.38 Shown in Fig.37 The circuit used in the calibration algorithm.

[0051] Fig.39 A calibration algorithm for programming non-volatile memory cells is shown.

[0052] Fig.40 A calibration algorithm for programming non-volatile memory cells is shown.

[0053] Fig.41 Shown in Fig.41 The circuit used in the calibration algorithm.

[0054] Fig.42 An exemplary progression of voltages applied to the control gates of nonvolatile memory cells during a programming operation is shown.

[0055] Fig.43 An exemplary progression of voltages applied to the control gates of nonvolatile memory cells during a programming operation is shown.

[0056] Fig.44 A system for applying programming voltages during programming of nonvolatile memory cells within a vector-multiplication matrix system is shown.

[0057] Fig.45 A vector-matrix multiplication system is shown having an output module including a modulator, an analog-to-digital converter, and a summer.

[0058] Fig.46 A charge summer circuit is shown.

[0059] Fig.47 A current summer circuit is shown.

[0060] Fig.48 A digital summer circuit is shown.

[0061] Fig.49A One implementation of an integrating analog-to-digital converter for neuron output is shown.

[0062] Fig.49BShow Show Fig.49A A graph showing the voltage output of an integrating analog-to-digital converter changing over time.

[0063] Fig.49C Another implementation of an integrating analog-to-digital converter for neuron output is shown.

[0064] Fig.49D Show Show Fig.49C A graph showing the voltage output of an integrating analog-to-digital converter changing over time.

[0065] Fig.49E Another implementation of an integrating analog-to-digital converter for neuron output is shown.

[0066] Fig.49F Another implementation of an integrating analog-to-digital converter for neuron output is shown.

[0067] Fig.50A and Fig.50B A successive approximation analog-to-digital converter is shown for the neuron output.

[0068] Fig.51 One implementation of a Σ-Δ type analog-to-digital converter is shown.

[0069] Fig.52A , Fig.52B and Fig.52C An implementation of a ramp-type analog-to-digital converter is shown.

[0070] Fig.53 One implementation of an algorithmic analog-to-digital converter is shown. DETAILED DESCRIPTION

[0071] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0072] Non-volatile memory cell

[0073] Digital non-volatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0074] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on word line terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim tunneling from floating gate 20 to word line terminal 22.

[0075] The memory cell 210 is programmed by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14 (where electrons are placed on the floating gate). Electron current will flow from the source region 14 (source line terminal) to the drain region 16. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide onto the floating gate 20.

[0076] The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through the channel region 18, which is sensed as a programmed state or a "0" state.

[0077] Table 1 shows typical voltage ranges that may be applied to the terminals of the memory cell 110 for performing read operations, erase operations, and program operations:

[0078] Table 1: Figure 2 Operation of the flash memory unit 210

[0079]

[0080] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0081] Figure 3 A memory cell 310 is shown, which is connected to Figure 2 The memory cell 210 is similar to the memory cell 210 of FIG. 1 , but with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, at a low voltage or negative voltage (e.g., 0v / -8V) during erasing, and at a low voltage or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are similar to Figure 2 That's biased.

[0082] Figure 4 A quad-gate memory cell 410 is shown, which includes a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0083] Table 2 shows typical voltage ranges that may be applied to the terminals of the memory cell 410 for performing read operations, erase operations, and program operations:

[0084] Table 2: Figure 4 Operation of the flash memory unit 410

[0085]

[0086] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0087] Figure 5 Memory cell 510 is shown, except that the erase gate EG terminal is not included. Memory cell 510 is similar to Figure 4 Erasing is performed by biasing the substrate 18 to a high voltage and biasing the control gate CG terminal 28 to a low or negative voltage. Alternatively, erasing is performed by biasing the word line terminal 22 to a positive voltage and biasing the control gate terminal 28 to a negative voltage. Programming and reading are similar to Figure 4 Like that.

[0088] Figure 6 6 is another type of flash memory cell. Figure 4 The memory cell 410 is the same as the memory cell 610 except that the memory cell 610 does not have a separate control gate terminal. Except that no control gate bias is applied, the erase operation (erasing by using the erase gate terminal) and the read operation are similar to Figure 4 The programming operation is also completed without a control gate bias, and as a result, a higher voltage must be applied on the source line terminal during the programming operation to compensate for the lack of control gate bias.

[0089] Table 3 shows typical voltage ranges that may be applied to the terminals of the memory cell 610 for performing read operations, erase operations, and program operations:

[0090] Table 3: Figure 6 Operation of the flash memory unit 610

[0091]

[0092] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0093] Figure 7 7 is another type of flash memory cell. Figure 2 1 is similar to the memory cell 210 of 1, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (which here will be coupled to the word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, program and read operations operate in a similar manner as previously described for the memory cell 210.

[0094] Table 4 shows typical voltage ranges that may be applied to the terminals of the memory cell 710 and the substrate 12 for performing read, erase, and program operations:

[0095] Table 4: Figure 7 Operation of the flash memory unit 710

[0096] CG BL SL Substrate Read 1 0V-5V 0.1V–2V 0V-2V 0V Read 2 0.5V-2V 0V-2V 2V-0.1V 0V Erase -8V to -10V / 0V FLT FLT 8V-10V / 15V-20V programming 8V-12V 3V-5V / 0V 0V / 3V-5V 0V

[0097] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to a row of memory cells or two adjacent rows of memory cells. That is, the source line terminal can be shared by memory cells in adjacent rows.

[0098] In order to utilize a memory array comprising one of the above-described types of non-volatile memory cells in an artificial neural network, two modifications are made. First, the circuitry is configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

[0099] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all cells in the memory array, and this makes the memory array ideal for storing and fine-tuning the synaptic weights of a neural network.

[0100] The methods and apparatus described herein can be applied to other non-volatile memory technologies, such as but not limited to SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (two-layer or multi-layer one-time programmable), and CeRAM (correlated electron ram), etc. The methods and apparatus described herein can be applied to volatile memory technologies for neural networks, such as but not limited to SRAM, DRAM, and / or volatile synaptic cells.

[0101] Neural Network Using Non-Volatile Memory Cell Array

[0102] Figure 8 A non-limiting example of a neural network using a non-volatile memory array of the present embodiment is conceptually illustrated. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a neural network based on a non-volatile memory array.

[0103] For this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5 bits of precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of this multiplication, a single output value is determined and provided by the first synapse of CB1 for use in generating a feature map for one of the pixels of layer C1. The 3x3 filter is then shifted right by one pixel within the input layer S0 (i.e., a column of three pixels on the right is added, and a column of three pixels on the left is released), whereby the 9 pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image of the input layer S0. The process is then repeated using different sets of weights to generate different feature maps for C1 until all feature maps for layer C1 are calculated.

[0104] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 consists of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary identification. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0105] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function is to average neighboring positions (or a max function can also be used) to, for example, reduce the dependency of edge positions and reduce the data size before entering the next stage. At layer S1, there are 16 15x15 feature maps (i.e., sixteen different arrays of 15x15 pixels per feature map). The synapse CB2 from layer S1 to layer C2 scans the map in S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12x12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse of CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, i.e., each neuron in layer C3 is connected to each neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, the output may indicate recognition or classification of the content of the original image.

[0106] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0107] Fig. 9 is a block diagram of a system that can be used for this purpose. The vector-matrix multiplication (VMM) system 32 includes a non-volatile memory unit and serves as a synapse between one layer and the next layer (such as Figure 6 CB1, CB2, CB3 and CB4 in FIG. 3 ). Specifically, the VMM system 32 includes a VMM array 33 (including non-volatile memory cells arranged in rows and columns), an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36 and a source line decoder 37, which decode the corresponding inputs of the non-volatile memory cell array 33. The input to the VMM array 33 may come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 may decode the output of the VMM array 33.

[0108] The VMM array 33 serves two purposes. First, it stores weights to be used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs with the weights stored in the VMM array 33 and each output line (source line or bit line) adds them together to produce an output that will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory calculations.

[0109] The output of the VMM array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive weight input and the negative weight input to output a single value.

[0110] The output values ​​of the difference summer 38 are then summed and provided to the activation function circuit 39, which corrects the output. The activation function circuit 39 can provide a sigmoid, tanh, ReLU function or any other nonlinear function. The corrected output value of the activation function circuit 39 becomes the next layer (for example, Figure 8 The elements of the feature map of layer C1 in the image are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summer 38 and activation function circuit 39 constitute a plurality of neurons.

[0111] Fig. 9 The inputs to the VMM system 32 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to suitable input analog levels), or digital bits (in which case a DAC is provided to convert the digital bits to suitable input analog levels); the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels into digital bits).

[0112] Fig.10 2 is a block diagram illustrating the use of multiple layers of VMM systems 32 (here labeled VMM systems 32a, 32b, 32c, 32d, and 32e). Fig.10As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first level of input D / A conversion can be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert the external analog input into a mapped analog input to the input VMM system 32a. The input conversion can also be accomplished by a digital-to-digital pulse (D / P) converter to convert the external digital input into one or more digital pulses mapped to the input VMM system 32a.

[0113] The output generated by the input VMM system 32a is provided as an input to the next VMM system (hidden level 1) 32b, which in turn generates an output provided as an input to the next VMM system (hidden level 2) 32c, and so on. The layers of the VMM system 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be an independent physical system including a corresponding non-volatile memory array, or multiple VMM systems can utilize different parts of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping parts of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time-division multiplexed for different parts of its array or neurons. Fig.10 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c) and two fully connected layers (32d, 32e). Those of ordinary skill in the art will appreciate that this is merely exemplary and that, on the contrary, the system may include more than two hidden layers and more than two fully connected layers.

[0114] VMM Array

[0115] Fig.11 A neuron VMM array 1100 is shown, which is particularly suitable for Figure 3 The memory cells 310 shown are used as synapses and components of neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of nonvolatile memory cells and a reference array 1102 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0116] In the VMM array 1100, control gate lines (such as control gate line 1103) extend in the vertical direction (so reference array 1102 is orthogonal to control gate line 1103 in the row direction), and erase gate lines (such as erase gate line 1104) extend in the horizontal direction. Here, the inputs of the VMM array 1100 are set on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all currents from the memory cells connected to that particular source line.

[0117] As described herein for neural networks, the non-volatile memory cells of VMM array 1100 (ie, the flash memory of VMM array 1100) are preferably configured to operate in a sub-threshold region.

[0118] Biasing the nonvolatile reference memory cell and the nonvolatile memory cell described herein in weak inversion:

[0119] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0120] where w = e (-Vth) / nVt

[0121] Where Ids is the drain to source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is related to (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0122] For an I to V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg:

[0123] Vg=n*Vt*log[Ids / wp*Io]

[0124] Here, wp is w of a reference memory cell or a peripheral memory cell.

[0125] For an I to V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg:

[0126] Vg=n*Vt*log[Ids / wp*Io]

[0127] Here, wp is w of a reference memory cell or a peripheral memory cell.

[0128] For a memory array used as a vector matrix multiplier VMM array, the output current is:

[0129] Iout=wa*Io*e (Vg) / nVt ,Right now

[0130] Iout=(wa / wp)*Iin=W*Iin

[0131] W=e (Vthp-Vtha) / nVt

[0132] Iin=wp*Io*e (Vg) / nVt

[0133] Here, wa = w for each memory cell in the memory array.

[0134] The word line or control gate may be used as the input of the memory cell for the input voltage.

[0135] Alternatively, the non-volatile memory cells of the VMM array described herein may be configured to operate in the linear region:

[0136] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L,

[0137] Wα(Vgs-Vth),

[0138] This means that the weight W in the linear region is proportional to (Vgs-Vth)

[0139] The word line or control gate or bit line or source line can be used as the input of the memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0140] For an I to V linear converter, a memory cell (eg, a reference memory cell or a peripheral memory cell) or a transistor or a resistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0141] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0142] Ids=1 / 2*β*(Vgs-Vth)2 ; β=u*Cox*Wt / L

[0143] Wα(Vgs-Vth) 2 , which means weight W and (Vgs-Vth) 2 Proportional

[0144] The word line, control gate, or erase gate can be used as the input of the memory cell operating in the saturation region. The bit line or source line can be used as the output of the output neuron.

[0145] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or a combination thereof (subthreshold, linear, or saturation regions).

[0146] U.S. Patent Application No. 15 / 826,345 describes Fig. 9 Other embodiments of the VMM array 33 of , which is incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0147] Fig.12 A neuron VMM array 1200 is shown, which is particularly suitable for Figure 2 1 and 2. The memory cell 210 shown in FIG. 1 is a memory cell 210 of FIG. 1 , and serves as a synapse between an input layer and a next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 arranged along the column direction of the array are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1214 (only partially shown), in which the current input flows. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0148] The memory array 1203 serves two purposes. First, it stores the weights that the VMM array 1200 will use on its corresponding memory cells. Second, the memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided in the terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert into input voltages to provide to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array 1203 eliminates the need for separate multiplication logic circuits and addition logic circuits, and is also highly power-efficient. Here, the voltage inputs are provided on the word lines (WL0, WL1, WL2, and WL3), and the outputs appear on the corresponding bit lines (BL0-BLN) during the read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0149] Table 5 shows the operating voltages for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell, where FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations.

[0150] Table 5: Fig.12 Operation of the VMM array 1200

[0151]

[0152] Fig.13 A neuron VMM array 1300 is shown, which is particularly suitable for Figure 2The memory cell 210 shown in FIG. 1 is a memory cell 210, and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that in the VMM array 1300, the word lines extend in the vertical direction. Here, the input is set on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output appears on the source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0153] Table 6 shows the operating voltages for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0154] Table 6: Fig.13 Operation of the VMM array 1300

[0155]

[0156] Fig.14 A neuron VMM array 1400 is shown, which is particularly suitable for Figure 3 The memory cell 310 shown is used as a synapse and component of the neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of nonvolatile memory cells, a reference array 1401 of a first nonvolatile reference memory cell, and a reference array 1402 of a second nonvolatile reference memory cell. The reference arrays 1401 and 1402 are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1412 (only partially shown), wherein the current input flows into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1412 each include a respective multiplexer 1405 and cascode transistor 1404 to ensure a constant voltage on a bit line (such as BLR0) of each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0157] The memory array 1403 serves two purposes. First, it stores weights to be used by the VMM array 1400. Second, the memory array 1403 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted by reference arrays 1401 and 1402 into input voltages to be provided to control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output, which appears in BL0-BLN and will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0–BLN) during a read operation. The current placed on each bit line performs a summing function of all currents from the memory cells connected to that particular bit line.

[0158] The VMM array 1400 implements unidirectional tuning for the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (causing the wrong value to be stored in the cell), the cell must be erased and the sequence of partial programming operations must be restarted. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0159] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0160] Table 7: Fig.14 Operation of the VMM array 1400

[0161]

[0162] Fig.15 A neuron VMM array 1500 is shown, which is particularly suitable for Figure 3The memory cell 310 shown is used as a synapse and component of the neurons between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of nonvolatile memory cells, a reference array 1501 of a first nonvolatile reference memory cell, and a reference array 1502 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired amount of charge on the floating gate due to the use of a separate EG line. As shown, reference arrays 1501 and 1502 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of the reference cells connected via the diodes of multiplexer 1514). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bit line.

[0163] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0164] Table 8: Fig.15 Operation of the VMM Array 1500

[0165]

[0166] Fig.16 A neuron VMM array 1600 is shown, which is particularly suitable for Figure 2 The memory cell 210 shown in FIG. 1 is used as a synapse and component of neurons between the input layer and the next layer. In the VMM array 1600, the input INPUT0 ..., INPUT N On bit lines BL0, BL N The signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0167] Fig.17 A neuron VMM array 1700 is shown, which is particularly suitable for Figure 2 The memory cell 210 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2 and INPUT3 are received on source lines SL0, SL1, SL2 and SL3, respectively, and outputs OUTPUT0, ... OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0168] Fig.18 A neuron VMM array 1800 is shown, which is particularly suitable for Figure 2 The memory unit 210 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0,…,WL M is received and output OUTPUT0, ...OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0169] Fig.19 A neuron VMM array 1900 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0,…,WL M is received and output OUTPUT0, ...OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0170] Fig. 20 A neuron VMM array 2000 is shown, which is particularly suitable for Figure 4 The memory unit 410 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the input INPUT0, ..., INPUT n On the vertical control gate lines CG0,...,CG N The signals are received on the source lines SL0 and SL1, and outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0171] Fig.21 A neuron VMM array 2100 is shown, which is particularly suitable for Figure 4 The memory unit 410 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the input INPUT0, ..., INPUT N are received at the gates of bit line control gates 2901-1, 2901-2, ..., 2901-(N-1), and 2901-N, which are respectively coupled to bit lines BL0, ..., BL N Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0172] Fig. 22 A neuron VMM array 2200 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M are received and output OUTPUT0,…,OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0173] Fig.23 A neuron VMM array 2300 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0,…,CG M The outputs OUTPUT0,…,OUTPUT N On the vertical source lines SL0, ..., SL N Each source line SL i The source line coupled to all memory cells in column i.

[0174] Fig.24 A neuron VMM array 2400 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7The memory unit 710 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0,…,CG M The outputs OUTPUT0,…,OUTPUT N On the vertical bit lines BL0, ..., BL N On generation, each bit line BL i The bit line coupled to all memory cells in column i.

[0175] Long Short-Term Memory

[0176] Prior art includes a concept called long short-term memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows a neural network to remember information for a predetermined arbitrary time interval and use the information in subsequent operations. A conventional LSTM cell includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval at which information is remembered in the LSTM. VMMs are particularly useful in LSTM cells.

[0177] Fig.25 An exemplary LSTM 2500 is shown. The LSTM 2500 in this example includes units 2501, 2502, 2503, and 2504. Unit 2501 receives an input vector x0 and generates an output vector h0 and a unit state vector c0. Unit 2502 receives an input vector x1, an output vector (hidden state) h0 from unit 2501, and a unit state c0 from unit 2501, and generates an output vector h1 and a unit state vector c1. Unit 2503 receives an input vector x2, an output vector (hidden state) h1 from unit 2502, and a unit state c1 from unit 2502, and generates an output vector h2 and a unit state vector c2. Unit 2504 receives an input vector x3, an output vector (hidden state) h2 from unit 2503, and a unit state c2 from unit 2503, and generates an output vector h3. Additional units may be used, and an LSTM with four units is merely an example.

[0178] Fig.26 Shown can be used for Fig.25 2501, 2502, 2503, and 2504 in LSTM cell 2600. LSTM cell 2600 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and generates a cell state vector c(t) and an output vector h(t).

[0179] LSTM cell 2600 includes sigmoid function devices 2601, 2602, and 2603, each of which applies a number between 0 and 1 to control the amount of each component in the input vector that is allowed to pass through to the output vector. LSTM cell 2600 also includes tanh devices 2604 and 2605 for applying a hyperbolic tangent function to the input vector, multiplier devices 2606, 2607, and 2608 for multiplying two vectors together, and an addition device 2609 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

[0180] Fig. 27 LSTM unit 2700 is shown, which is an example of a specific implementation of LSTM unit 2600. For the convenience of readers, the same numbering as LSTM unit 2600 is used in LSTM unit 2700. Sigmoid function devices 2601, 2602 and 2603 and tanh device 2604 each include multiple VMM arrays 2701 and activation circuit blocks 2702. Therefore, it can be seen that the VMM array is particularly useful in LSTM units used in certain neural network systems.

[0181] An alternative form of LSTM cell 2700 (and another example of a specific implementation of LSTM cell 2600) is Fig.28 In Fig.28 In the example, sigmoid function devices 2601, 2602 and 2603 and tanh device 2604 share the same physical hardware (VMM array 2801 and activation function block 2802) in a time-division multiplexing manner. The LSTM unit 2800 also includes a multiplier device 2803 for multiplying two vectors together, an addition device 2808 for adding two vectors together, a tanh device 2605 (which includes an activation circuit block 2802), a register 2807 for storing the value i(t) when the value i(t) is output from the sigmoid function block 2802, a register 2804 for storing the value f(t)*c(t-1) when it is output from the multiplier device 2803 through the multiplexer 2810, a register 2805 for storing the value i(t)*u(t) when it is output from the multiplier device 2803 through the multiplexer 2810, a register 2806 for storing the value o(t)*c~(t) when it is output from the multiplier device 2803 through the multiplexer 2810, and a multiplexer 2809.

[0182] LSTM unit 2700 includes multiple sets of VMM arrays 2701 and corresponding activation function blocks 2702, while LSTM unit 2800 includes only one set of VMM arrays 2801 and activation function blocks 2802, which are used to represent multiple layers in the implementation of LSTM unit 2800. LSTM unit 2800 will require less space than LSTM 2700 because LSTM unit 2800 only needs 1 / 4 of its space for VMM and activation function blocks compared to LSTM unit 2700.

[0183] It will also be appreciated that an LSTM cell will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM arrays (such as summer and activation circuit blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM arrays themselves.

[0184] Gate Controlled Recursive Unit

[0185] The specific implementation of the simulated VMM can be used for a gated recurrent unit (GRU) system. GRU is a gate mechanism in a recurrent neural network. GRU is similar to LSTM, except that a GRU unit generally contains fewer components than an LSTM unit.

[0186] Fig.29 An exemplary GRU 2900 is shown. The GRU 2900 in this example includes units 2901, 2902, 2903, and 2904. Unit 2901 receives an input vector x0 and generates an output vector h0. Unit 2902 receives an input vector x1, an output vector h0 from unit 2901, and generates an output vector h1. Unit 2903 receives an input vector x2 and an output vector (hidden state) h1 from unit 2902, and generates an output vector h2. Unit 2904 receives an input vector x3 and an output vector (hidden state) h2 from unit 2903, and generates an output vector h3. Additional units may be used, and a GRU with four units is merely an example.

[0187] Fig.30 Shown can be used for Fig.29An exemplary implementation of a GRU unit 3000 of units 2901, 2902, 2903 and 2904. The GRU unit 3000 receives an input vector x(t) and an output vector h(t-1) from a previous GRU unit and generates an output vector h(t). The GRU unit 3000 includes sigmoid function devices 3001 and 3002, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). The GRU unit 3000 also includes a tanh device 3003 for applying a hyperbolic tangent function to an input vector, a plurality of multiplier devices 3004, 3005 and 3006 for multiplying two vectors together, an addition device 3007 for adding two vectors together, and a complement device 3008 for subtracting the input from 1 to generate an output.

[0188] Fig.31 3100 is shown, which is an example of a specific implementation of the GRU unit 3000. For the convenience of the reader, the same numbering is used in the GRU unit 3100 as in the GRU unit 3000. Fig.31 As shown, the sigmoid function devices 3001 and 3002 and the tanh device 3003 each include a plurality of VMM arrays 3101 and an activation function block 3102. Therefore, it can be seen that the VMM array is particularly useful in the GRU unit used in some neural network systems.

[0189] An alternative form of GRU unit 3100 (and another example of a specific implementation of GRU unit 3000) is Fig.32 In Fig.32 In , the GRU unit 3200 utilizes a VMM array 3201 and an activation function block 3202, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. Fig.32In the example, sigmoid function devices 3001 and 3002 and tanh device 3003 share the same physical hardware (VMM array 3201 and activation function block 3202) in a time-division multiplexing manner. The GRU unit 3200 also includes a multiplier device 3203 that multiplies two vectors together, an addition device 3205 that adds two vectors together, a complement device 3209 that subtracts the input from 1 to generate an output, a multiplexer 3204, a register 3206 that holds the value h(t-1)*r(t) when it is output from the multiplier device 3203 through the multiplexer 3204, a register 3207 that holds the value h(t-1)*z(t) when it is output from the multiplier device 3203 through the multiplexer 3204, and a register 3208 that holds the value h^(t)*(1-z(t)) when it is output from the multiplier device 3203 through the multiplexer 3204.

[0190] The GRU unit 3100 includes multiple sets of VMM arrays 3101 and activation function blocks 3102, while the GRU unit 3200 includes only one set of VMM arrays 3201 and activation function blocks 3202, which are used to represent multiple layers in the implementation of the GRU unit 3200. The GRU unit 3200 will require less space than the GRU unit 3100 because the GRU unit 3200 only needs 1 / 3 of its space for VMM and activation function blocks compared to the GRU unit 3100.

[0191] It will also be appreciated that a GRU system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summer and activation circuit blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0192] The inputs to the VMM array can be analog levels, binary levels, timing pulses, or digital bits, and the outputs can be analog levels, binary levels, timing pulses, or digital bits (in this case, an output ADC is required to convert the output analog level current or voltage into digital bits).

[0193] For each memory cell in the VMM array, each weight w can be implemented by a single memory cell or by a differential cell or by two hybrid memory cells (average of 2 or more cells). In the case of a differential cell, two memory cells are required to implement the weight w as a differential weight (w = w + - w -). In two hybrid memory cells, two memory cells are required to implement the weight w as the average of the two cells.

[0194] Implementation for accurate programming of cells in a VMM

[0195] Fig.33A A programming method 3300 is shown. First, the method starts (step 3301), which typically occurs in response to receiving a program command. Next, a bulk programming operation programs all cells to a "0" state (step 3302). Then, a soft erase operation erases all cells to an intermediate weak erase level so that each cell will consume, for example, approximately 3μA-5μA of current during a read operation (step 3303). This is in contrast to a deep erase level, in which each cell will consume approximately 20μA-30μA of current during a read operation. Then, hard programming is performed on all unselected cells to a very deep programmed state to add electrons to the floating gate of the cell (step 3304) to ensure that those cells are truly "off," meaning that those cells will consume a negligible amount of current during a read operation.

[0196] A coarse programming method is then performed on the selected cells (to bring the cells closer to the target, e.g., 2X-100 times the target) (step 3305), followed by a fine programming method (step 3306) to program the precise value desired for each selected cell.

[0197] Fig.33B Another programming method 3310 is shown that is similar to the programming method 3300. However, instead of Fig.33A After the method starts (step 3301), an erase operation is used to erase all cells to the "1" state (step 3312). Then a soft programming operation (step 3313) is used to program all cells to an intermediate state (level) so that each cell will consume approximately 3uA-5uA of current during a read operation. Thereafter, the rough and precise programming methods will be as follows Fig.33A shown. Fig.33B A variation of the implementation would remove the soft programming method (step 3313) entirely.

[0198] Fig.34 A first implementation of a coarse programming method 3305 is shown, which is a search and execute method 3400. First, a lookup table search is performed to determine a coarse target current value (I CT )(Step 3401). For example, the table is created by silicon characterization or wafer test calibration. Assume that the selected cell can be programmed to store one of N possible values ​​(e.g., 128, 64, 32, etc.). Each of the N values ​​will correspond to a different expected current value (I DIn one embodiment, the lookup table may contain M possible current values ​​to be used as a rough target current value I for the selected cell during the search and execution of method 3400. CT , where M is an integer less than N. For example, if N is 8, then M can be 4, which means that there are 8 possible values ​​that the selected cell can store, and one of the 4 rough target current values ​​will be selected for the rough target of the search and execution method 3400. That is, the search and execution method 3400 (which is also an embodiment of the rough programming method 3305) aims to quickly program the selected cell to a certain degree of closeness to the desired value (I D ) value (I CT ), then the precision programming method 3306 aims to program the selected cell more precisely to be extremely close to the desired value (I D ).

[0199] For a simple example of N=8 and M=4, examples of cell values, desired current values, and rough target current values ​​are shown in Tables 9 and 10:

[0200] Table 9: Example of N expected current values ​​when N = 8

[0201] The value stored in the selected cell <![CDATA[Desired current value ( I D )]]> 000 100pA 001 200pA 010 300pA 011 400pA 100 500pA 101 600pA 110 700pA 111 800pA

[0202] Table 10: Example of M target current values ​​when M = 4

[0203] <![CDATA[Rough target current value (I CT )]]> Associated cell value <![CDATA[800pA+ I CTOFFSET1 ]]> 000,001 <![CDATA[1600pA+ I CTOFFSET2 ]]> 010,011 <![CDATA[2400pA+ I CTOFFSET3 ]]> 100,101 <![CDATA[3200pA+ I CTOFFSET4 ]]> 110,111

[0204] Offset value I CTOFFSETx Used to prevent the desired current value from being exceeded during coarse adjustment.

[0205] Once the rough target current value I is selected CT , the selected cell is programmed by applying voltage v0 to the appropriate terminals of the selected cell based on the cell architecture type of the selected cell (e.g., memory cell 210, 310, 410, or 510) (step 3402). Figure 3 If the memory cell 310 is of the type 20, the voltage v0 will be applied to the control gate terminal 28, and according to the rough target current value I CT , v0 can be 5V-7V. The value of V0 can be optionally obtained by storing a voltage lookup table of v0 and a rough target current value I CT Sure.

[0206] Next, by applying a voltage v i =v i-1 +v increment Program the selected cell, where i starts at 1 and increments each time the step is repeated, and v incrementis a small fine voltage that will result in a degree of programming appropriate for the desired granularity of change (step 3403). Thus, the first time step 3403 is performed, i=1, and v1 will be v0+v increment A verify operation then occurs (step 3404), in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell ). If I cell Less than or equal to I CT (here the first threshold), the search and execution method 3400 is complete, and the precise programming method 3306 can begin. cell Not less than or equal to I CT , then repeat step 3403, and i is incremented.

[0207] Therefore, at the moment when the coarse programming method 3305 ends and the fine programming method 3306 begins, the voltage v i will be the final voltage used to program the selected cell, and the selected cell will store the value corresponding to the rough target current I CT The purpose of the precise programming method 3306 is to program the selected cell to a value that consumes current I during a read operation. D (plus or minus an acceptable tolerance, such as + / -50 pA or + / -30% or less), the current I D is the desired current value associated with the value intended to be stored in the selected cell.

[0208] Fig.35 Examples of different voltage progressions that may be applied to the control gates of selected memory cells during coarse and / or fine programming methods 3306 are shown.

[0209] In the first method, increasing voltages are applied to the control gate in a progressive manner to further program the selected memory cell. The starting point is v i , which is the final voltage applied during the coarse programming method 3305. The increment v p1 Add to v1, then use the voltage v1+v p1 The selected cell (indicated by the second pulse from the left in progressive 3501) is programmed. p1 is less than v increment (the voltage increment used during the coarse programming method 3305). After each programming voltage is applied, a verification step (similar to step 3404) is performed, in which the I cell Is it less than or equal to I PT1 (which is the first precise target current value and here is the second threshold value), where I PT1 =I D +IPT1OFFSET , where I PT1OFFSET is the offset value added to prevent programming overshoot. If not, another increment v p1 is added to the previously applied programming voltage and the process is repeated. cell Less than or equal to I PT1 Optionally, if I PT1 Equal to I D or sufficiently accurately equal to I D , the selected memory cell has been successfully programmed.

[0210] If I PT1 Not close enough D , further programming of smaller granularity can be performed. Here, step 3502 is now used. The starting point of step 3502 is the final voltage used for programming under step 3501. p2 (It is less than v p1 ) is added to this voltage, and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, a verification step (similar to step 3404) is performed, in which the I cell Is it less than or equal to I PT2 (which is the second precise target current value and here is the third threshold value), where I PT2 =I D +I PT2OFFSET , where I PT2OFFSET is the offset value added to prevent programming overshoot. If not, another increment v p2 is added to the previously applied programming voltage and the process is repeated. cell Less than or equal to I PT2 , then that part of the programming sequence stops. Here, it is assumed that I PT2 Equal to I D or close enough to I D , so that programming can stop because the target value has been achieved with sufficient accuracy. It will be appreciated by one of ordinary skill in the art that additional progression can be applied by using smaller and smaller programming increments. For example, in Fig.36 In , three progressions (3601, 3602, and 3603) are applied instead of just two.

[0211] The second method is shown in step 3503. Here, instead of increasing the voltage applied during programming of the selected memory cell, the same voltage is applied for the duration of the increment cycle. Instead of adding an incremental voltage such as v in step 3501, p1 And add v in progressive 3503 p2 , but the additional time increment tp1 added to the programming pulses so that each pulse applied is longer than the previously applied pulse by t p1 After each programming pulse is applied, the same verification steps as previously described for progression 3501 are performed. Optionally, additional progressions may be applied where the additional time increments added to the programming pulses are of shorter duration than the previously used schedule. Although only one time progression is shown, one of ordinary skill in the art will appreciate that any number of different time progressions may be applied.

[0212] Additional details for two additional implementations of the coarse programming method 3305 will now be provided.

[0213] Fig.37 A second embodiment of the coarse programming method 3305 is shown, which is an adaptive calibration method 3700. The method starts (step 3701). The cell is programmed with a default starting value v0 (step 3702). Unlike in the search and execute method 3400, here v0 is not derived from a lookup table, but can be a relatively small initial value. The control gate voltage of the cell is measured at a first current value IR1 (e.g., 100 nA) and a second current value IR2 (e.g., 10 nA), and the subthreshold slope is determined based on these measurements (e.g., 360 mV / dec) and stored (step 3703).

[0214] Determine the new desired voltage v i The first time this step is performed, i=1, and v1 is determined based on the stored subthreshold slope value and the current target and offset values ​​using a subthreshold formula, such as the following:

[0215] Vi=Vi-1+Vincrement,

[0216] Vincrement is proportional to the slope of Vg

[0217] Vg=n*Vt*log[Ids / wa*Io]

[0218] Here, wa is the w of the memory cell and Ids is the current target value plus the offset value.

[0219] If the stored slope value is relatively steep, a relatively small current offset value may be used. If the stored slope value is relatively flat, a relatively high current offset value may be used. Thus, determining the slope information will allow the selection of a current offset value that is customized for the particular cell under consideration. This will ultimately make the programming process shorter. As this step is repeated, i is incremented and v is incremented. i =v i-1 +v increment . Then use vi to program. incrementCan be stored by v increment The value is determined by a lookup table with the target current value.

[0220] Then, a verification operation is performed, in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell )(Step 3705). If I cell Less than or equal to I CT (here it is a rough target threshold), where I CT Set to =I D +I CTOFFSET , where I CTOFFSET is the offset value added to prevent programming overshoot, then the adaptive calibration method 3700 is complete and the precise programming method 2206 can begin. cell Not less than or equal to I CT , then repeat steps 3704 to 3705, and i is incremented.

[0221] Fig.38 Aspects of the adaptive calibration method 3700 are shown. During step 3803, current source 3801 is used to apply exemplary current values ​​IR1 and IR2 to the selected cell (here memory cell 3802), and then the voltage at the control gate of memory cell 3802 is measured (CGR1 for IR1 and CGR2 for IR2). The slope will be (CGR2-CGR1) / dec.

[0222] Fig.39 A second embodiment of a programming method 3305 is shown, which is an adaptive calibration method 3900. The method starts (step 3901). The cell is programmed with a default starting value v0 (step 3902). V0 is derived from a lookup table, such as created from silicon characteristics, whose values ​​are offset so as not to exceed the programming target.

[0223] In the next step 3903, an IV slope parameter is created for predicting the next programming voltage, and the first control gate read voltage V CGR1 is applied to the selected cell and the resulting cell current IR1 is measured. Then, the second control gate read voltage V CGR2 is applied to the selected cell and the resulting cell current IR2 is measured. The slope is determined based on these measurements and is stored, for example, according to the equation in the subthreshold region (a cell operating in subthreshold):

[0224] Slope = (V CGR1 –V CGR2 ) / (LOG(IR1)–LOG(IR2))

[0225] (Step 3903).CGR1 and V CGR2 Examples of values ​​of are 1.5V and 1.3V respectively.

[0226] Determining the slope information allows the selection of a V tailored to the particular cell in question. increment This will ultimately make the programming process shorter.

[0227] When step 3904 is repeated, i is incremented and the new desired programming voltage V is determined based on the stored slope value and the current target and offset values ​​using the following equation: i :

[0228] V i =V i-1 +V increment ,

[0229] Among them, for i-1, V increment =α*slope*(LOG(IR1)-LOG(ICT)),

[0230] Among them, I CT is the target current, and α is a predetermined constant <1 (programming offset value) to prevent overshoot, for example, 0.9. For example, Vi is VSLP or VCGP, the source line or control gate programming voltage.

[0231] Then use Vi to program the unit. (Step 3904)

[0232] Then, a verification operation is performed, in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell )(Step 3906). If I cell Less than or equal to I CT (here it is a rough target threshold), where I CT Set to =I D +I CTOFFSET , where I CTOFFSET If i is the offset value added to prevent programming overshoot, the process proceeds to step 3907. If not, the process returns to step 390 and i is incremented.

[0233] In step 3907, I cell and less than I CT Threshold CT2 The purpose of this is to see whether overshoot has occurred. That is, although the goal is to make I cell Below I CT But if it is much lower than I CT , then an overshoot has occurred and the stored value may actually correspond to an erroneous value. cell Not less than or equal to ICT2 , then no overshoot occurs and the adaptive calibration method 3900 has been completed, at which point the process proceeds to the precise programming method 3306. cell Less than or equal to I CT2 , then overshoot has occurred. The selected cell is then erased (step 3908), and the programming process restarts at step 3902. Optionally, if step 3908 is performed more than a predetermined number of times, the selected cell may be considered a bad cell that should not be used.

[0234] Precise programming method 3306 such as consists of multiple verify cycles and programming cycles, where the programming voltage consists of constant fine voltage increments with fixed pulse width, or where the programming voltage is fixed and the programming pulse width is either variable or constant from one pulse to the next.

[0235] Optionally, the step of determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value can be performed by: applying a fixed bias to the terminals of the non-volatile memory cell; measuring and digitizing the current consumed by the selected non-volatile memory cell to generate a digital output bit; and comparing the digital output bit to a digital bit representing the first threshold current.

[0236] Optionally, the step of determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value can be performed by: applying a fixed bias to the terminals of the non-volatile memory cell; measuring and digitizing the current consumed by the selected non-volatile memory cell to generate a digital output bit; and comparing the digital output bit to a digital bit representing the first threshold current.

[0237] Optionally, the step of determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value can be performed by applying an input to a terminal of the non-volatile memory cell; modulating the current consumed by the selected non-volatile memory cell with an output pulse to generate a modulated output; digitizing the modulated output to generate a digital output bit; and comparing the digital output bit to a digital bit representing the first threshold current.

[0238] Fig.40A third embodiment of a programming method 3305 is shown, which is an absolute calibration method 4000. The method starts (step 4001). A cell is programmed with a default starting value v0 (step 4002). The control gate voltage (VCGRx) of the cell is measured at a current value Itarget and stored (step 4003). A new desired voltage v1 is determined based on the stored control gate voltage and the current target value and offset value Ioffset+Itarget (step 4004). For example, the new desired voltage v1 can be calculated as follows: v1=v0+(VCGBIAS-stored VCGR), where VCGBIAS is approximately equal to 1.5V, which is the default read control gate voltage at the maximum target current, and the stored VCGR is the read control gate voltage measured in step 4003.

[0239] Then use v i Program the cell. When i=1, use the voltage v1 from step 4004. When i>=2, use the voltage v i =v i-1 +V inclument .v inclument Available from storage v increment The current consumed by the selected cell (I cell )(Step 4006). If I cell Less than or equal to I CT (where it is a threshold), then the absolute calibration method 4000 is complete and the precise programming method 3306 can begin. cell Not less than or equal to I CT , then repeat steps 4005 to 4006, and i is incremented.

[0240] Fig.41Illustrated is a circuit 4100 for implementing step 4003 of the absolute calibration method 4000. A voltage source (not shown) generates a VCGR that ramps up from an initial voltage. Here, n + 1 different current sources 4101 (4101-0, 4101-1, 4101-2, …, 4101-n) generate different currents IO0, IO1, IO2, … IOn with increasing amplitudes. Each current source 4101 is connected to an inverter 4102 (4102-0, 4102-1, 4102-2, …, 4102-n) and a memory cell 4103 (4103-0, 4103-1, 4103-2, …, 4103-n). As the VCGR ramps up, each memory cell 4103 consumes an increasing amount of current, and the input voltage to each inverter 4102 decreases. Since IO0 < IO1 < IO2 < … < IOn, the output of inverter 4102-0 will first switch from low to high as the VCGR increases. Next, the output of inverter 4102-1 will switch from low to high, then the output of inverter 4102-2 will switch, and so on, until the output of inverter 4102-n switches from low to high. Each inverter 4102 controls a switch 4104 (4104-0, 4104-1, 4104-2, …, 4104-n) such that when the output of the inverter 4102 is high, the switch 4104 closes, which causes the VCGR to be sampled by a capacitor 4105 (4105-0, 4105-1, 4105-2, …, 4105-n). Thus, the switches 4104 and the capacitors 4105 can form a sample-and-hold circuit. In Fig.40 the absolute calibration method 4000, the values of IO0, IO1, IO2, …, IOn are used as possible values of Itarget, and the corresponding sampled voltages are used as the associated values VCGRx. A graph 4106 shows the VCGR ramping up over time, and the outputs of inverters 4102-0, 4102-1, and 4102-n switching from low to high at different times.

[0241] Fig.42 Illustrated is an exemplary progression 4200 for programming selected cells during an adaptive calibration method 3700 or an absolute calibration method 4000. In one embodiment, a voltage Vcgp is applied to the control gates of the memory cells in the selected row. The number of selected memory cells in the selected row is, for example, = 32 cells. Thus, up to 32 memory cells in the selected row can be programmed in parallel. Each memory cell is allowed to be coupled to a programming current Iprog through a bit line enable signal. If the bit line enable signal is inactive (meaning a positive voltage is applied to the selected bit line), the memory cell is inhibited (not programmed). As Fig.42As shown, the bit line enable signal En_blx (where x varies between 1 and n, where n is the number of bit lines) is enabled at different times to have the Vcgp voltage level required for the bit line (and thus the selected memory on the bit line). In another embodiment, the enable signal on the bit line can be used to control the voltage applied to the control gate of the selected cell. Each bit line enable signal enables the desired voltage (such as Fig.40 vi) as Vcgp. The bit line enable signal can also control the programming current flowing into the bit line. In this example, each subsequent control gate voltage Vcgp is higher than the previous voltage. Alternatively, each subsequent control gate voltage may be lower or higher than the previous voltage. Each subsequent increment of Vcgp may be equal to or different from the previous increment.

[0242] Fig.43 An exemplary progression 4300 for programming selected cells during the adaptive calibration method 3700 or the absolute calibration method 4000 is shown. In one embodiment, the bit line enable signal enables the selected bit line (meaning the selected memory cell in the bit line) to be programmed with the corresponding VCGP voltage level. In another embodiment, the bit line enable signal can be used to control the voltage applied to the incremental ramp control gate of the selected cell. Each bit line enable signal enables the desired voltage corresponding to the bit line (such as Fig.40 vi) described in is applied to the control gate voltage. In this example, each subsequent increment is equal to the previous increment.

[0243] Fig.44 A system for implementing input and output methods for reading or verifying using a VMM array is shown. Input function circuit 4401 receives digital bit values ​​and converts these digital values ​​into analog signals, which are then used to apply voltages to the control gates of selected cells in array 4404, which are determined by control gate decoder 4402. At the same time, word line decoder 4403 is also used to select the row where the selected cell is located. Output neuron circuit block 4405 performs output actions for each column (neuron) of cells in array 4404. Output circuit block 4405 can be implemented using an integrating analog-to-digital converter (ADC), a successive approximation register (SAR) ADC, a Σ-Δ ADC, or any other ADC scheme.

[0244] In one embodiment, for example, the digital value provided to the input function circuit 4401 includes four bits (DIN3, DIN2, DIN1, and DIN0), and different bit values ​​correspond to different numbers of input pulses applied to the control gate. A larger number of pulses will result in a larger output value (current) of the cell. Examples of bit values ​​and pulse values ​​are shown in Table 11:

[0245] Table 11: Digital bit input and generated pulses

[0246] DIN3 DIN2 DIN1 DIN0 Generated input pulse 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15

[0247] In the above example, there are a maximum of 15 pulses for a 4-bit digital value to read out the cell value. Each pulse is equal to one unit of the cell value (current). For example, if Icell unit = 1nA, then for DIN[3-0] = 0001, Icell = 1*1nA = 1nA; and for DIN[3-0] = 1111, Icell = 15*1nA = 15nA.

[0248] In another embodiment, the digital bit input uses digital bit position summation to read out the cell value or neuron value (e.g., the value on the bit line output), as shown in Table 12. Here, only 4 pulses or 4 fixed identical bias inputs (e.g., inputs on the word line or control gate) are required to evaluate the 4-bit digital value. For example, DIN0 is evaluated using a first pulse or a first fixed bias, DIN1 is evaluated using a second pulse or a second fixed bias having the same value as the first pulse or the second fixed bias, DIN2 is evaluated using a third pulse or a third fixed bias having the same value as the first pulse or the second fixed bias, and DIN3 is evaluated using a fourth pulse or a fourth fixed bias having the same value as the first pulse or the fourth fixed bias. The results of the four pulses are then added according to the bit position, where each output result is multiplied (reduced) by a multiplier, namely 2^n, where n is the digital bit position, as shown in Table 13. The implemented digital bit summation formula is as follows: Output = 2^0*DIN0+2^1*DIN1+2^2*DIN2+2^3*DIN3)*Icell units.

[0249] For example, if Icell unit = 1nA, then for DIN[3-0] = 0001, Icell total = 0+0+0+1*1nA = 1nA; and for DIN[3-0] = 1111, Icell total = 0+0+0+1*1nA = 1nA. cell Total = 8*1nA+4*1nA+2*1nA+1*1nA=26nA.

[0250] Table 12: Digital bit input summation

[0251] 2^3*DIN3 2^2*DIN2 2^1*DIN1 2^0*DIN0 Total value 0 0 0 0 0 0 0 0 1 1 0 0 2 0 2 0 0 2 1 3 0 4 0 0 4 0 4 0 1 5 0 4 2 0 6 0 4 2 1 7 8 0 0 0 8 8 0 0 1 9 8 0 2 0 10 8 0 2 1 11 8 4 0 0 12 8 4 0 1 13 8 4 2 0 14 8 4 2 1 15

[0252] Table 13: Summation of digital input bits Dn with 2^n output multiplication factor

[0253] DIN3 DIN2 DIN1 DIN0 Output X Factor Y X1 Y X2 Y X4 Y X8

[0254] Another embodiment of a mixed input with multiple digital input pulse ranges and a sum of input digital ranges for an exemplary 4-bit digital input is shown in Table 14. In this embodiment, DINn-0 can be divided into m different groups, where each group is evaluated and the output is scaled by a factor multiplied by the group binary position. For example, for a 4-bit DIN3-0, the groups can be DIN3-2 and DIN1-0, where the output for DIN1-0 is scaled by 1 (X1) and the output for DIN3-2 is scaled by 4 (X4).

[0255] Table 14: Mixed Input-Output Summing with Multiple Input Ranges

[0256] DIN3 DIN2 DIN1 DIN0 Input pulse (or equivalent pulse width) Output X Factor 0 0 0 X1 0 1 1 X1 1 0 2 X1 1 1 3 X1 0 0 0 X4 0 1 1 X4 1 0 2 X4 1 1 3 X4

[0257] Another embodiment combines a hybrid input range with a hybrid supercell. The hybrid supercell includes multiple physical x-bit cells to implement a logical n-bit cell, where the x-bit output is scaled by 2^n binary positions. For example, to implement an 8-bit logical cell, two 4-bit cells (cell 1, cell 0) are used. Other combinations of physical x-cells to implement an n-bit logical cell are possible, such as two 2-bit physical cells and one 4-bit physical cell to implement an 8-bit logical cell, with the output for cell 0 scaled by 1 (x1) and the output for cell 1 scaled by 4 (x, 2^2).

[0258] Fig.45 Shows something like Fig.44Another embodiment of the system, except that the digital bit input uses the digital bit position summation to read the current of the cell or neuron modulated by the modulator 4510 (e.g., the value on the bit line output), where the output pulse width is designed based on the digital input bit position (e.g., converting the current into an output voltage V = current * pulse width / capacitance). For example, a first bias (applied on an input such as a word line or control gate) is used to evaluate DIN0, and the current (cell or neuron) output is modulated by the modulator 4510 with a unit pulse width proportional to the DIN0 bit position, which unit pulse width is one (x1) unit, a second input bias is used to evaluate DIN1, and the current output is modulated by the modulator 4510 with a unit pulse width proportional to the DIN1 bit position, which unit pulse width is two (x2) units, a third input bias is used to evaluate DIN2, and the current output is modulated by the modulator 4510 with a pulse width proportional to the DIN2 bit position, which pulse width is four (x4) units, and a fourth input bias is used to evaluate DIN3, and the current output is modulated by the modulator 4510 with a pulse width proportional to the DIN3 bit position, which pulse width is eight (x8) units. Each converted voltage is then converted into a digital bit by an ADC (analog-to-digital converter) 4511 for each digital input bit. The total output is then output by summer 4512 as the sum of the four digital outputs generated from the DIN0-3 inputs.

[0259] Fig.46 An example of a charge summer 4600 is shown, which can be used to sum the VMM outputs during a verification operation or during an output neuron analog-to-digital conversion to obtain a single analog value representing the output, which is then optionally converted to a digital bit value. For example, the charge summer 4600 can be used as the summer 4512. The charge summer 4600 includes a current source 4601 and a sample-and-hold circuit, which includes a switch 4602 and a sample-and-hold (S / H) capacitor 4603. As shown in the example for a 4-bit digital value, there are 4 S / H circuits to hold the values ​​from the 4 evaluation pulses, where the values ​​are added at the end of the process. The S / H capacitor 4603 is selected to have a ratio associated with the 2^n*DINn bit position of the S / H capacitor; for example, C_DIN3=x8 Cu, C_DIN2=x4 Cu, C_DIN1=x2 Cu, DIN0=x1 Cu. The current source 4601 is also scaled accordingly.

[0260] Fig.47A current summer 4700 is described that can be used to sum the VMM outputs during a verification operation or during an output neuron analog-to-digital conversion. The current summer 4700 includes a current source 4701, a switch 4702, switches 4703 and 4704, and a switch 4705. As shown in the example for a 4-bit digital value, there is a current source circuit to hold the values ​​from the 4 evaluation pulses, where the values ​​are added at the end of the process. The current sources are scaled based on the 2^n*DINn bit positions; for example, I_DIN3 = x8 Icell units, I_DIN2 = x4 Icell units, I_DIN1 = x2 Icell units, I_DIN0 = x1 Icell units.

[0261] Fig.48 A digital summer 4800 is shown that receives multiple digital values, sums them and generates an output DOUT representing the sum of the inputs. The digital summer 4800 can be used during a validation operation or during an output neuron analog-to-digital conversion. As shown in the example for a 4-bit digital value, there are digital output bits to hold the values ​​from the 4 evaluation pulses, where the values ​​are added at the end of the process. The digital outputs are digitally scaled based on 2^n*DINn bit positions; for example, DOUT3=x8DOUT0, _DOUT2=x4DOUT1, I_DOUT1=x2DOUT0, I_DOUT0=DOUT0.

[0262] Fig.49A An integrating dual slope ADC 4900 applied to an output neuron to convert a cell current into a digital output bit is shown. An integrator consisting of an integrating operational amplifier 4901 and an integrating capacitor 4902 integrates the cell current ICELL and a reference current IREF. Fig.49B As shown, during a fixed time t1, the cell current is integrated up (Vout rises), and then the reference current is applied down integrated (Vout falls) during time t2. Current Icell = t2 / t1*IREF. For example, for t1, for a 10-bit digital resolution, 1024 cycles are used, and for t2, the number of cycles varies from 0 to 1024 cycles depending on the Icell value.

[0263] Fig.49C An integrating single slope ADC 4960 is shown applied to an output neuron to convert the cell current into a digital output bit. An integrator consisting of an integrating operational amplifier 4961 and an integrating capacitor 4962 integrates the cell current ICELL. Fig.49DAs shown, during time t1, the cell current is integrated up (Vout rises until it reaches Vref2), and during time t2, another cell current is integrated up. Cell current I cell = Cint*Vref2 / t. The pulse counter is used to count the number of pulses (digital output bits) during the integration time t. For example, as shown, the digital output bit of t1 is less than the digital output bit of t2, which means that the cell current during t1 is greater than the cell current during the integration period of t2. An initial calibration is performed to calibrate the integrating capacitor value Cint = Tref*Iref / Vref2 using a reference current and a fixed time.

[0264] Fig.49E An integrating dual slope ADC 4980 is shown applied to an output neuron to convert the cell current into a digital output bit. The integrating dual slope ADC 4980 does not use an integrating operational amplifier. The cell current or reference current is integrated directly against a capacitor 4982. A pulse counter is used to count the pulses (digital output bits) during the integration time. Current Icell = t2 / t1*IREF.

[0265] Fig.49F An integrating single slope ADC 4990 is shown applied to an output neuron to convert the cell current into a digital output bit. The integrating single slope ADC 4980 does not use an integrating operational amplifier. The cell current is integrated directly against a capacitor 4992. A pulse counter is used to count the pulses (digital output bits) during the integration time. The cell current Icell = Cint*Vref2 / t.

[0266] Fig.50A A SAR (Successive Approximation Register) ADC is shown applied to an output neuron to convert the cell current into a digital output bit. The cell current may drop across a resistor for conversion to VCELL. Alternatively, the cell current may charge a S / H capacitor for conversion to VCELL. A binary search is used to calculate the bit starting with the MSB bit (most significant bit). Based on the digital bit from SAR 5001, DAC 5002 is used to set the appropriate analog reference voltage to comparator 5003. The output of comparator 5003 is then fed back to SAR 5001 to select the next analog level. As Fig.50B As shown, for the example of a 4-bit digital output bit, there are 4 evaluation cycles: the first pulse evaluates DOUT3 by setting the analog level in the middle, then the second pulse evaluates DOUT2 by setting the analog level in the middle of the upper half or the middle of the lower half, and so on.

[0267] A modified binary search such as a cyclic (algorithmic) ADC can be used for cell tuning (e.g., programming) verification or output neuron conversion. A modified binary search such as a switched capacitor (SC) charge redistribution ADC can be used for cell tuning (e.g., programming) verification or output neuron conversion.

[0268] Fig.51 A Σ-Δ ADC 5100 is shown applied to an output neuron to convert a cell current into a digital output bit. An integrator consisting of an operational amplifier 5101 and a capacitor 5105 integrates the sum of the current from the selected cell current and the reference current from a 1-bit current DAC 5104. A comparator 5102 compares the integrated output voltage to a reference voltage. A clocked DFF 5103 provides a digital output stream based on the output of the comparator 5102. The digital output stream typically enters a digital filter before being output to a digital output bit.

[0269] Fig.52A A ramp analog-to-digital converter 5200 is shown, which includes a current source 5201 (which represents the received neuron current, Ineu), a switch 5202, a variable configurable capacitor 5203, and a comparator 5204, which receives the voltage (represented as Vneu) formed across the variable configurable capacitor 5203 as a non-inverting input and receives a configurable reference voltage Vreframp as an inverting input and generates an output Cout. Vreframp ramps up at a discrete level with each comparison clock cycle. The comparator 5204 compares Vneu with Vreframp, and therefore when Vneu>Vreframp, the output Cout will be "1", and otherwise it will be "0". Therefore, the output Cout will be a pulse whose width varies in response to Ineu. A larger Ineu will cause Cout to be "1" for a longer period of time, resulting in a wider pulse of the output Cout. The digital counter 5220 converts each pulse of the output Cout into a digital output bit, such as Fig.52B As shown for two different Ineu currents (denoted as OT1A and OT2A). Alternatively, the ramp voltage Vreframp is a continuous ramp voltage 5255, such as Fig.52B As shown in the curve graph 5250. Fig.52C5 shows a multi-slope implementation scheme for reducing conversion time by utilizing a coarse-fine ramp conversion algorithm. A first coarse reference ramp reference voltage 5271 is ramped in a fast manner to find each sub-range of Ineu. Next, a fine reference ramp reference voltage 5272 (i.e., Vreframp1 and Vreframp2) is used for each sub-range to convert the Ineu current within the corresponding sub-range. As shown, there are two sub-ranges of fine reference ramp voltages. More than two coarse / fine steps or more than two sub-ranges are possible.

[0270] Fig.53 An algorithmic analog-to-digital output converter 5300 is shown, which includes a switch 5301, a switch 5302, a sample-and-hold (S / H) circuit 5303, a 1-bit analog-to-digital converter (ADC) 5304, a 1-bit digital-to-analog converter (DAC) 5305, a summer 5306, and the gain of two residual operational amplifiers (2x opamps) 5307. The algorithmic analog-to-digital output converter 5300 generates a converted digital output 5308 in response to an analog input Vin and control signals applied to switches 5301 and 5302. The input received at the analog input Vin (e.g., Vneu in FIG. 52 ) is first sampled by the S / H circuit 5303 through the switch 5302, and then conversion is performed in N clock cycles for N bits. For each conversion clock cycle, the 1-bit ADC 5304 compares the S / H voltage 5309 with a reference voltage (e.g., VREF / 2, where VREF is the full-scale voltage of N bits) and outputs a digital bit (e.g., "0" if the input <= VREF / 2, and "1" if the input > VREF / 2). This digital bit (which is the digital output signal 5308) is then converted by the 1-bit DAC 5305 into an analog voltage (e.g., converted to VREF / 2 or 0V) and fed to the summer 5306 to be subtracted from the S / H voltage 5309. The 2x residue opamp 5307 then amplifies the summer difference voltage output into a conversion residue voltage 5310, which is fed to the S / H circuit 5303 through the switch 5301 for the next clock cycle. Instead of the 1-bit (i.e., 2-level) algorithm ADC, a 1.5-bit (i.e., 3-level) algorithm ADC may be used to reduce the effects of offsets such as from ADC 5304 and residual opamp 5307. A 1.5-bit or 2-bit (i.e., 4-level) DAC is required for a 1.5-bit algorithm ADC.

[0271] In another embodiment, a hybrid ADC may be used. For example, for a 9-bit ADC, the first 4 bits may be generated by a SAR ADC, and the remaining 5 bits may be generated using a slope ADC or a ramp ADC.

[0272] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intermediate material, element, or space is provided between) and "indirectly on" (intermediate material, element, or space is provided between). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space is provided between) and "indirectly adjacent" (intermediate material, element, or space is provided between), "mounted to" includes "directly mounted to" (no intermediate material, element, or space is provided between) and "indirectly mounted to" (intermediate material, element, or space is provided between), and "electrically coupled to" includes "directly electrically coupled to" (no intermediate material or element electrically connecting the elements together between) and "indirectly electrically coupled to" (intermediate material or element electrically connecting the elements together between). For example, forming an element "above a substrate" may include directly forming the element on the substrate without intermediate materials / elements between the two, and indirectly forming the element on the substrate with one or more intermediate materials / elements between the two.

Claims

1. A method of programming a selected non-volatile memory cell to store one of N values, wherein N is an integer greater than 2, the selected non-volatile memory cell comprising a floating gate and a control gate, the method comprising: Perform a rough programming process, including: programming the nonvolatile memory cell with an initial programming voltage; applying a first voltage to the control gate of the selected nonvolatile memory cell and measuring a first current through the selected nonvolatile memory cell; applying a second voltage to the control gate of the selected nonvolatile memory cell and measuring a second current through the selected nonvolatile memory cell; determining a slope value based on the first voltage, the second voltage, the first current, and the second current; determining a next programming voltage based on the slope value; programming the nonvolatile memory cell with the next programming voltage; repeating the steps of determining a next programming voltage and programming the nonvolatile memory cell with the next programming voltage until a current through the selected nonvolatile memory cell during a read or verify operation is less than or equal to a first threshold current value; and A precision programming process is performed until a current through the selected nonvolatile memory cell during a read or verify operation is less than or equal to a second threshold current value.

2. The method according to claim 1, wherein the step of performing a coarse programming process further comprises: When the current through the selected nonvolatile memory cell is less than or equal to a third threshold current value, the selected nonvolatile memory cell is erased and the coarse programming process is repeated.

3. The method according to claim 1, further comprising: A second precision programming process is performed until a current through the selected nonvolatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.

4. The method of claim 1, wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gates of the selected nonvolatile memory cells.

5. The method of claim 1, wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gates of the selected nonvolatile memory cells.

6. The method of claim 1, wherein the selected non-volatile memory cells are split-gate flash memory cells.

7. The method of claim 1, wherein the selected non-volatile memory cell is in a vector-matrix multiplication array in an analog memory deep neural network.

8. The method according to claim 1, further comprising: Before performing the rough programming process described: Programming the selected nonvolatile memory cell to a "0" state; as well as The selected nonvolatile memory cells are erased to a weakly erased level.

9. The method according to claim 1, further comprising: Before performing the rough programming process described: Erasing the selected nonvolatile memory cell to a "1" state; as well as The selected nonvolatile memory cells are programmed to a weak programming level.

10. The method according to claim 1, further comprising: performing a read operation on the selected non-volatile memory cell; as well as The current consumed by the selected nonvolatile memory cell during the read operation is integrated using an integrating analog-to-digital converter to generate a digital bit.

11. The method according to claim 1, further comprising: performing a read operation on the selected non-volatile memory cell; as well as The current consumed by the selected nonvolatile memory cell during the read operation is converted into digital bits using a sigma-delta type analog-to-digital converter.

12. The method according to claim 1, further comprising: performing a read operation on the selected non-volatile memory cell; as well as The current consumed by the selected nonvolatile memory cell during the read operation is converted into digital bits using an algorithmic modulus.

13. The method according to claim 2, further comprising: A second precision programming process is performed until a current through the selected nonvolatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.

14. The method of claim 2, wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gates of the selected nonvolatile memory cells.

15. The method of claim 2, wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gates of the selected nonvolatile memory cells.

16. The method of claim 2, wherein the selected non-volatile memory cells are split-gate flash memory cells.

17. The method of claim 2, wherein the selected non-volatile memory cell is in a vector-matrix multiplication array in an analog memory deep neural network.

18. The method according to claim 2, further comprising: Before performing the rough programming process described: Programming the selected nonvolatile memory cell to a "0" state; as well as The selected nonvolatile memory cells are erased to a weakly erased level.

19. The method according to claim 2, further comprising: Before performing the rough programming process described: Erasing the selected nonvolatile memory cell to a "1" state; as well as The selected nonvolatile memory cells are programmed to a weak programming level.

20. The method according to claim 2, further comprising: performing a read operation on the selected non-volatile memory cell; as well as The current consumed by the selected nonvolatile memory cell during the read operation is integrated using an integrating analog-to-digital converter to generate a digital bit.

21. The method according to claim 2, further comprising: performing a read operation on the selected non-volatile memory cell; as well as The current consumed by the selected nonvolatile memory cell during the read operation is converted into digital bits using a sigma-delta type analog-to-digital converter.

22. The method according to claim 2, further comprising: performing a read operation on the selected non-volatile memory cell; as well as The current consumed by the selected nonvolatile memory cell during the read operation is converted into digital bits using an algorithmic analog-to-digital converter.

23. The method of claim 1, further comprising: Determining whether a current through the selected nonvolatile memory cell during a read or verify operation is less than or equal to the first threshold current value by: applying an input pulse to a terminal of the nonvolatile memory cell; measuring and digitizing the current consumed by the selected non-volatile memory cell to generate a digital output bit; and comparing the digital output bit to a digital bit representing the first threshold current.

24. The method of claim 1, further comprising: Determining whether a current through the selected nonvolatile memory cell during a read or verify operation is less than or equal to the first threshold current value by: applying a fixed bias to a terminal of the nonvolatile memory cell; measuring and digitizing the current consumed by the selected non-volatile memory cell to generate a digital output bit; and comparing the digital output bit to a digital bit representing the first threshold current.

25. The method of claim 1, further comprising: determining whether the current through the selected nonvolatile memory cell during a read or verify operation is less than or equal to the first threshold current value by: applying an input to a terminal of the nonvolatile memory cell; modulating the current consumed by the selected nonvolatile memory cell with an output pulse to generate a modulated output; digitizing the modulated output to generate a digital output bit; and comparing the digital output bit to a digital bit representing the first threshold current.

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