Placing top vias at wire ends by selective growth of via masks from wire-cut dielectric

Abstract

Embodiments of the invention relate to a manufacturing method and resulting structure for placing a self-aligned top via (802) at a line end of an interconnect structure (100). In a non-limiting embodiment of the invention, a line feature (102) is formed in a metallization layer of an interconnect structure (100). The line feature (102) can include a line hardmask (104). A trench (106) is formed in the line feature (102) to expose a line end of the line feature (102). The trench (106) is filled with a bulk material (202), and a growth inhibitor (402) is formed on a first line end of the line feature (102). A via mask (602) is formed on a second line end of the line feature (102). The via mask (602) can selectively grow on an exposed surface of the bulk material (202). A portion of the line feature (102) not covered by the via mask (602) is recessed to define a self-aligned top via (802) at the second line end.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to methods of fabricating semiconductor devices and resulting structures, and more specifically, to methods of fabricating and resulting structures for placing self-aligned top vias at line ends of an interconnect structure by selective growth of via masks from line cuts. BACKGROUND

[0002] The fabrication of very large scale integration (VLSI) or ultra large scale integration (ULSI) circuits requires the fabrication of complex interconnect structures, including metal wiring that connects individual devices in a semiconductor chip to one another. Typically, the wiring interconnect network is composed of two types of features that serve as electrical conductors, namely, line features that span a distance across the chip, and via features that connect lines in different levels. The conductive metal lines and vias are made of conductive materials, such as aluminum or copper, and are electrically insulated by interlayer dielectrics (ILDs). In a multi-level interconnect structure, the metallization layers are referred to as "M" layers (e.g., Ml layer, M2 layer, etc.), while "V" layers represent vias that are located between adjacent M layers (e.g., VI between Ml and M2 layers).

[0003] To increase the number of circuits that can be provided on a chip, the semiconductor industry has repeatedly shrunk the transistor gate length and chip size. As a result, the interconnect structures that form the metal circuitry have also shrunk. As integrated circuit (IC) feature sizes continue to decrease, the aspect ratio (i.e., height / depth to width ratio) of features such as vias typically increases, complicating the fabrication process. Fabricating complex structures of conductive interconnect layers and high aspect ratio vias within increasingly smaller wafer real estate is one of the most process-intensive and cost-sensitive portions of semiconductor IC fabrication. SUMMARY

[0004] Embodiments of the present invention relate to a method for forming a self-aligned top via at a line end of an interconnect structure. A non-limiting example of the method includes forming a line feature in a metallization layer of the interconnect structure. The line feature can include a line hardmask. A trench is formed in the line feature to expose a line end of the line feature. The trench is filled with a bulk material, and a growth inhibitor is formed on a first line end of the line feature. A via mask is formed on a second line end of the line feature. The via mask can selectively grow on an exposed surface of the bulk material. A portion of the line feature that is not covered by the via mask is recessed to define a self-aligned top via at the second line end.

[0005] Embodiments of the invention relate to a method for forming a self-aligned top via at a line end of an interconnect structure. A non-limiting example of the method includes forming a line feature in a metallization layer. The line feature can include two or more line ends. A region between a first line end and a second line end is filled with a matrix material, and a growth inhibitor is formed on the first line end. A via mask is selectively grown on an exposed surface of the bulk material. Portions of the line feature not covered by the via mask are recessed to define a self-aligned top via at the second line end.

[0006] Embodiments of the invention relate to a semiconductor structure. A non-limiting example of the semiconductor device includes a line feature in a metallization layer of an interconnect structure. A plurality of self-aligned top vias are formed at line ends of the line feature. The self-aligned top vias include a same critical dimension. The critical dimension is not affected by lithography variations.

[0007] Embodiments of the invention relate to a semiconductor structure. A non-limiting example of the semiconductor device includes a line feature in a metallization layer of an interconnect structure. The line feature includes a first line end and a second line end. A trench is adjacent to the first line end of the line feature. The trench includes a bulk material. A first top via is formed at the first line end of the line feature. The first top via includes a first critical dimension. A second top via is formed at the second line end of the line feature. The second top via includes the first critical dimension. The first critical dimension is not affected by lithography variations.

[0008] Additional technical features and benefits are realized through the techniques of the invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] The specifics of the exclusive right described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A cross-sectional view of a semiconductor structure after an initial set of processing operations is shown in accordance with one or more embodiments of the invention;

[0011] Figure 2 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the invention;

[0012] Figure 3 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the invention;

[0013] Figure 4A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0014] Figure 5 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0015] Figure 6 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0016] Figure 7 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0017] Figure 8 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0018] Figure 9 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0019] Figure 10 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0020] Figure 11 A cross-sectional view of a semiconductor structure after additional processing operations is shown in accordance with one or more embodiments of the application;

[0021] Figure 12 A flow diagram illustrating a method in accordance with one or more embodiments of the application is depicted; and

[0022] Figure 13 A flow diagram illustrating a method in accordance with one or more embodiments of the application is described.

[0023] The diagrams described herein are illustrative. Many variations to the diagrams or the operations described therein will be apparent to those of ordinary skill in the art. For example, the acts can be performed in a different order than described, or additional, deleted or modified acts can be added to the disclosed diagrams.

[0024] In the drawings and detailed description of the described embodiments of the application that follow, the various elements illustrated in the drawings have two or three digit reference numbers associated with them. The left-most digit of each reference number corresponds to the first digit of the reference number of the element to which it is drawn. DETAILED DESCRIPTION

[0025] It is to be understood that, while example embodiments of the present application are described in connection with a specific transistor architecture, embodiments of the present application are not limited to the specific transistor architecture or materials described in this specification. Rather, embodiments of the present application can be implemented in connection with any other type of transistor architecture or materials now known or later developed.

[0026] For the sake of brevity, conventional techniques related to semiconductor devices and integrated circuit (IC) fabrication can or can not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known and so have not been described in detail herein. Accordingly, the detailed description included herein is not intended to be a complete description of the manufacture of the structure, but rather only a description of one embodiment thereof that is sufficient for understanding the various embodiments of the present application.

[0027] Turning now to a more specific overview of the technology with which aspects of the present application are more closely related, ICs are fabricated in a series of stages, including a front-end-of-line (FEOL) stage, a middle-of-line (MOL) stage, and a back-end-of-line (BEOL) stage. The process flow for fabricating modern ICs is generally determined according to whether the process flow falls in the FEOL stage, the MOL stage, or the BEOL stage. Generally, the FEOL stage is where device elements (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate / wafer. FEOL stage processes include wafer preparation, isolation, gate patterning, and formation of wells, source / drain (S / D) regions, extension junctions, silicide regions, and liners. The MOL stage generally includes process flows for forming contacts (e.g., CAs) and other structures that communicatively couple to active regions (e.g., gates, sources, and drains) of device elements. For example, silicidation of source / drain regions and deposition of metal contacts to connect elements patterned during the FEOL stage can occur during the MOL stage. During the BEOL stage, interconnect layers (e.g., metallization layers) are formed over these logic and functional layers to complete the IC. Most ICs require more than one layer of wiring to form all the necessary connections, and up to 5-12 layers are added in the BEOL process. The various BEOL layers are interconnected by vias that couple from one layer to another.

[0028] Insulating dielectric materials are used in all layers of an IC to perform various functions, including stabilizing the IC structure and providing electrical isolation of IC elements. For example, metal interconnect wires in the BEOL region of an IC are isolated by dielectric layers to prevent the wires from shorting to other metal layers.

[0029] The continued scaling of semiconductor devices has led to challenging manufacturing requirements, particularly when fabricating smaller metallization layers. Advanced masks incorporating phase shifting and optical proximity correction have been employed in an effort to meet these scaling requirements. However, these techniques are susceptible to overlay errors between features in the interconnect structure, which can lead to reliability issues in the final device. Misalignment during the lithography process leads to overlay errors since the mask is always becoming misaligned with the underlying structure. While overlay errors can be mitigated by redoing the lithography operation, some degree of overlay error is unavoidable, resulting in misalignment of features between metallization layers.

[0030] One of the challenges in fabricating advanced metallization layers is the difficulty in forming uniform vias (so-called top vias) at the end of the line without any variation in the via critical dimension (CD). The CD of a feature (interconnect line, contact, via, trench, etc.) refers to the minimum geometric dimension of the feature that can be formed (e.g., for a via, the CD refers to the via width). If lithography is used to accomplish the alignment of the via to the line feature, it is particularly difficult to achieve via CD uniformity due to the lithography limitations discussed earlier. In particular, limited overlay shifts (misalignments) can cause the vias to move away from the target line end or be cut off by the line end, resulting in a reduction in the CD in the via. Since the overlay shifts of the vias to vias are not all identical (some will move away from their respective target line while others will be cut off by different amounts), variations in the via CD are common.

[0031] Turning now to an overview of aspects of the present application, one or more embodiments of the present application address the aforementioned shortcomings of the prior art by providing a new semiconductor structure and a method for placing a self-aligned top via at the end of a line by leveraging a via mask to selectively grow a dielectric from the line cut.

[0032] In some embodiments of the present application, lithography and etching are used to first cut the line feature (metal line and line hardmask). The cut is then filled with a host material selected for a subsequent selective growth process. The host material is further selected to be non-dielectric and wets removable (e.g., TiN or TiOx). As used herein, a "wets removable" material refers to a material that can be removed using a wet etch. A lithographically patterned mask is used to cover the line with a via at one or both line ends, and a growth inhibitor is applied to the line exposed by the mask. The growth inhibitor grafts on the exposed dielectric, but not on the host material (e.g., metal containing cut fill material), leaving the surface of the host material exposed. A selectively grown via mask is formed (deposited) on the exposed host material.

[0033] The via mask can be metal or dielectric (depending on the body material, e.g., TaN, TiN, Ta, Ti, W, etc.) grown using a selected number of growth cycles to target a specific via size. The growth inhibitor will prevent the via mask material from growing at the line ends where no via is desired. The growth inhibitor is removed, and the lines are selectively recessed (e.g., etched) to the via mask to form self-aligned top vias at one or more line ends. The via mask, line hard mask, and body material are then removed and replaced with dielectric.

[0034] Advantageously, the vias formed in this way using selective growth of the via mask can be self-aligned to one or both ends of the metal lines. Variations in via CD that would otherwise result from lithographically aligning the vias to the previously formed lines are avoided. Instead, the via CD at each line end is controlled by the amount of lateral growth of the via mask, which can be well controlled using a precise number of growth cycles to target a specific via size. This greatly improves the manufacturing precision of the top vias, even allowing top vias at the very end of the lines (not possible using conventional lithography). In other words, the present invention provides top vias with an invariant via width (an invariant critical dimension that is not subject to lithographic variations).

[0035] Turning now to a more detailed description of aspects of the invention, Figures 1-11 A cross-sectional view of an interconnect structure 100 after an initial set of manufacturing operations is shown in accordance with one or more embodiments of the present invention. In Figure 1 In the figure, known manufacturing operations have been used to form the interconnect structure 100 so that it includes line features 102, a line hard mask 104, and a trench 106 as shown configured and arranged. Although not shown for ease of discussion, the line features 102 can be one of many lines in a metallization layer of the interconnect structure. The processes described here with respect to the line features 102 can be used to produce self-aligned vias in any of these metallization layers.

[0036] In some embodiments of the application, the line features 102 comprise a conductive material formed or deposited in the trenches of the metallization layer using known BEOL processes. In some embodiments of the application, the line features 102 are overfilled onto the surface of the trenches (not shown), forming an overburden that can be removed using, for example, a chemical mechanical planarization (CMP) process. The line features 102 can be made of any suitable conductive material, such as a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, platinum), an alloy thereof (e.g., AlCu, CuMn, CuTi, etc.), a conductive metal compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, cobalt silicide, nickel silicide), conductive carbon, or any suitable combination of these materials. In some embodiments of the application, the line features 102 are ruthenium lines. The line features 102 can be formed or deposited using, for example, CVD, PECVD, PVD, sputtering, electroplating, chemical solution deposition, and electroless plating.

[0037] In some embodiments of the application, the line hardmask 104 is deposited or formed on the top surface of the line features 102. The line hardmask 104 can be formed using any suitable process, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), atomic layer deposition (ALD), flowable CVD, spin-on dielectric, physical vapor deposition (PVD), molecular beam epitaxy (MBE), chemical solution deposition, spin-on dielectric, or other similar processes. The line hardmask 104 can be made of any suitable dielectric material, such as a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the application, the line hardmask 104 is a silicon nitride or silicon oxide hardmask. In some embodiments of the application, the line hardmask 104 is formed to a thickness of about 10 nm to about 60 nm, such as 30 nm, although other thicknesses are within the contemplation of the application.

[0038] In some embodiments of the application, the line hardmask 104 is formed over multiple line features, including the line features 102. In some embodiments of the application, the line hardmask 104 is formed of the same material over all line features. In some embodiments of the application, even and odd line features can comprise the same or different materials for the line hardmask 104. For example, even lines can comprise SiN and odd lines can comprise SiOx / SoG, or vice versa.

[0039] As Figure 1Further shown, portions of the line features 102 and the line hardmask 104 can be removed (cut or patterned) using a lithographic process to form one or more trenches 106. In some embodiments of the application, portions of the line features 102 and the line hardmask 104 are removed using a wet etch, a dry etch, or a combination of wet and / or dry etching in succession. In some embodiments of the application, portions of the line features 102 and the line hardmask 104 are removed using reactive ion etching (RIE). The positioning of the trenches 106 (line cuts) defines one or more line ends of the line features 102. As used herein, a line end refers to the portion (sidewall) of a line feature that is directly adjacent to a cut (e.g., the trench 106).

[0040] Figure 2 A cross-sectional view of the interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, the trenches 106 are filled with a bulk material 202. As previously described, the bulk material can be selected to provide a suitable surface for a subsequent selective growth process. Figure 6 ).

[0041] In some embodiments of the application, the bulk material 202 is further selected to be non-dielectric and wet-removable. In some embodiments of the application, the bulk material 202 includes TiN, TiOx, TaN, etc. In some embodiments of the application, the bulk material 202 is filled over the surface of the line hardmask 104, thereby forming a cap layer that can be removed using, for example, CMP. The bulk material 202 can be formed or deposited in the trenches 106 using, for example, CVD, PECVD, PVD, sputtering, electroplating, chemical solution deposition, and electroless plating.

[0042] Figure 3 A cross-sectional view of the interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, a lithographically patterned mask 302 is formed over the line hardmask 104. In some embodiments of the application, the lithographically patterned mask 302 is patterned to cover only portions of the line features 102 proximate to the line ends of desired vias.

[0043] Figure 4A cross-sectional view of interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, growth inhibitor 402 is formed on the portion of line hardmask 104 exposed by lithographically patterned mask 302. In some embodiments of the application, the growth inhibitor material is selected such that growth inhibitor 402 forms only on the exposed dielectric. In other words, growth inhibitor 402 can be selectively formed on the exposed portion of line hardmask 104. In some embodiments of the application, bulk material 202 is a non-dielectric material, and growth inhibitor 402 exposes the surface of bulk material 202.

[0044] In some embodiments of the application, growth inhibitor 402 will be grafted onto the surface of line hardmask 104 during a spin-on process. Examples of materials that do not bind to metal surfaces but can deposit onto dielectrics include self-assembled monolayers (e.g., carbon chains C6-C-18) or polymer brush materials designed with hydroxyl or amine functional groups (with molecular weights of 1-10k).

[0045] Figure 5 A cross-sectional view of interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, lithographically patterned mask 302 is removed to expose the surface of line hardmask 104.

[0046] In some embodiments of the application, lithographically patterned mask 302 is removed using a wet etch, a dry etch, a combination of wet and / or dry etching in sequence, or a photolithographic lift-off process. In some embodiments of the application, lithographically patterned mask 302 is selectively removed with respect to growth inhibitor 402, line hardmask 104, and / or bulk material 202.

[0047] Figure 6 A cross-sectional view of interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, via mask 602 is formed (deposited) on the exposed surface of bulk material 202. In some embodiments of the application, via mask 602 can be a metal or dielectric material grown using a precise number of growth cycles selected to target a particular via size.

[0048] In some embodiments of the application, the via mask 602 can comprise a material that will not grow on the growth inhibitor 402. In some embodiments of the application, the via mask 602 can comprise a material selected so that the via mask 602 will grow on the bulk material 202, but not on the growth inhibitor 402. Such materials can include TaN, TiN, Ta, Ti, W, etc., depending on the bulk material 202. In this manner, the growth inhibitor 402 will prevent the via mask 602 from being formed at the line end portions where vias are not desired.

[0049] Figure 7 A cross-sectional view of the interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, the growth inhibitor 402 is removed to expose the surface of the line hard mask 104.

[0050] In some embodiments of the application, the growth inhibitor 402 is removed using a wet etch, a dry etch, a combination of sequential wet and / or dry etching, a lift-off process, or an ashing process. In some embodiments of the application, the growth inhibitor 402 is selectively removed relative to the via mask 602, the line hard mask 104, and / or the bulk material 202. In some embodiments of the application, the growth inhibitor 402 is selectively removed using O2 / N2-H2 ashing.

[0051] Figure 8 A cross-sectional view of the interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, the line features 102 and the portions of the line hard mask 104 not covered by the via mask 602 are recessed to form one or more self-aligned top vias 802 at the line ends where the via mask 602 is allowed to form (i.e., as discussed with reference to Figure 5 and 6 the growth inhibitor 402 blocks.

[0052] Advantageously, by selectively recessing the surface of the line features 102 relative to the via mask 602, the top vias 802 are formed. As a result, top vias of arbitrarily high aspect ratio (defined as height-to-width ratio, or H / W) can be formed at the line ends without causing critical dimension variations. The aspect ratio can range from nearly zero (very wide vias) to 5 or even 10 or more (very high vias to very high vias with relatively small widths).

[0053] Figure 9A cross-sectional view of interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the present application. In some embodiments of the present application, via mask 602 is removed to expose the surface of line hardmask 104 and the surface of bulk material 202. In some embodiments of the present application, via mask 602 is removed using a wet etch, a dry etch, a combination of sequential wet and / or dry etches, a lift-off process, or an ashing process. In some embodiments of the present application, via mask 602 is selectively removed for line hardmask 104, line features 102, and / or bulk material 202.

[0054] Figure 10 A cross-sectional view of interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the present application. In some embodiments of the present application, line hardmask 104 is removed to expose the surface of top via 802. In some embodiments of the present application, line hardmask 104 is removed using a wet etch, a dry etch, a combination of sequential wet and / or dry etches. In some embodiments of the present application, line hardmask 104 is selectively removed for line features 102.

[0055] In some embodiments of the present application, bulk material 202 remains in interconnect structure 100. However, as shown in FIG. 11, in some embodiments of the present application, bulk material 202 is incompatible with the final product and is optionally removed. In some embodiments of the present application, bulk material 202 is removed using a wet etch, a dry etch, a combination of sequential wet and / or dry etches, a lift-off process, or an ashing process. In some embodiments of the present application, bulk material 202 is selectively removed for line features 102. Figure 10

[0056] Figure 11 A cross-sectional view of interconnect structure 100 after a processing operation is shown in accordance with one or more embodiments of the present application. In some embodiments of the present application, interlayer dielectric 1102 can be formed on interconnect structure 100. Interlayer dielectric 1102 serves as an isolation structure for the lines and vias of interconnect structure 100. Interlayer dielectric 1102 can be made of any suitable dielectric material, such as a low-k dielectric (a material with a small dielectric constant relative to silicon dioxide, i.e., less than about 3.9), an ultra-low-k dielectric (a material with a dielectric constant less than 3), a porous silicate, a carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide (SiC), or other dielectric material. Any known means of forming interlayer dielectric 1102 can be used, such as CVD, PECVD, ALD, flowable CVD, spin-on dielectric, or PVD. In some embodiments of the present application, interlayer dielectric 1102 is formed over the top surface of top via 802 and then planarized to the surface of top via 802 using, for example, CMP. ​

[0057] Figure 12 A flowchart 1200 of a method for forming a semiconductor device according to one or more embodiments of the application is described. As shown in block 1202, a line feature is formed in a metallization layer of an interconnect structure. In some embodiments of the application, the line feature includes a line hardmask. In some embodiments of the application, the line feature includes a metal line.

[0058] At block 1204, a trench is formed in the line feature to expose a line end of the line feature. In some embodiments of the application, forming the trench includes removing portions of the line feature using etching.

[0059] At block 1206, the trench is filled with a bulk material. In some embodiments of the application, the bulk material is selected based on the via mask (step 1210) to ensure that the via mask can selectively grow on a surface of the bulk material. In some embodiments of the application, the bulk material is further selected to include a wets removable non-dielectric material. In some embodiments of the application, the bulk material includes titanium nitride or titanium oxide.

[0060] At block 1208, a growth inhibitor is formed on the first line end of the line feature. In some embodiments of the application, the growth inhibitor prevents the via mask from growing on the first line end.

[0061] At block 1210, a via mask is formed on a second line end of the line feature. In some embodiments of the application, the via mask selectively grows on the exposed surface of the bulk material. In some embodiments of the application, the via mask is grown using a selected number of growth cycles in order to target a predetermined top via size.

[0062] At block 1212, portions of the line feature not covered by the via mask are recessed to define a self-aligned top via at the second line end. In some embodiments of the application, the line feature is recessed such that a sidewall of the top via is coplanar with a sidewall of the second line end. In some embodiments of the application, a plurality of top vias are formed on a respective plurality of line ends of the line feature. In some embodiments of the application, each top via includes a sidewall that is coplanar with a respective line end. In some embodiments of the application, one or more top vias are positioned over their respective line ends such that their three planes are coplanar. In other words, two opposing sidewalls and a surface corresponding to an end wall of the top via can be coplanar with the opposing sidewalls and the end wall of the line end.

[0063] The method can further include forming a photoresist mask over the line hardmask. The photoresist mask can be patterned to expose the first line end. In some embodiments of the invention, a growth inhibitor is formed on the exposed first line end. In some embodiments of the invention, the growth inhibitor is grafted to the surface of the line hardmask but not to the surface of the bulk material, thereby exposing the surface of the bulk material.

[0064] In some embodiments of the invention, the via mask, the line hardmask, and the bulk material are replaced with an interlayer dielectric. In some embodiments of the invention, the growth inhibitor is removed prior to recessing portions of the line feature.

[0065] Figure 13 A flowchart 1300 of a method for forming a semiconductor device according to one or more embodiments of the invention is described. As shown in block 1302, a line feature is formed in a metallization layer. In some embodiments of the invention, the line feature includes two or more line ends. At block 1304, a region between a first line end and a second line end is filled with a bulk material.

[0066] At block 1306, a growth inhibitor is formed over the first line end. In some embodiments of the invention, the growth inhibitor includes a self-assembled monolayer. In some embodiments of the invention, the self-assembled monolayer includes a C6-C18 carbon chain. In some embodiments of the invention, the growth inhibitor includes a polymer having a molecular weight of about 1 to about 10,000. In some embodiments of the invention, the polymer includes a hydroxyl or amine functional group.

[0067] At block 1308, a via mask is selectively grown over an exposed surface of the bulk material. At block 1310, portions of the line feature not covered by the via mask are recessed to define a self-aligned top via at the second line end.

[0068] The methods described herein and the resulting structures can be used in the fabrication of IC chips. The fabricator can then integrate the resulting IC chip with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product such as a personal computer, mobile device, and the like.

[0069] Various embodiments of the present application are described herein with reference to the accompanying drawings. Alternative embodiments can be devised without departing from the scope of the present application. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons having ordinary skill in the art will recognize that many of the positional relationships described herein are exemplary. Unless otherwise specified, the connections and / or positional relationships between elements should not be construed as being exclusively direct connections or indirect connections between the elements. Moreover, the described connections and / or positional relationships can be direct connections or indirect connections conveying a communication between the elements. All these variations are contemplated by the inventor unless otherwise specified. Similarly, the term "coupled" and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements in which no other intervening elements are present. All these variations are considered to be part of the specification. For example, a coupling between entities can be a direct coupling or an indirect coupling via one or more intermediary entities. Similarly, a positional relationship between entities can be a direct relationship or an indirect relationship, in which one or more intermediary entities are present between the two entities. Unless otherwise specified, the positional relationship between entities can be direct or indirect. As an example of an indirect positional relationship, a layer "A" formed on a layer "B" includes the possibility of one or more intervening layers (e.g., layer "C") between layer "A" and layer "B" as long as the relevant properties and functions of layer "A" and layer "B" are substantially retained.

[0070] The following definitions and abbreviations are used in the description and the appended claims. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, a process, a method, an article, or an apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0071] In addition, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc. The terms "multiple" and "plurality" are understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc. The term "coupled" can include an indirect "coupling" and a direct "coupling."

[0072] Reference throughout this specification to "one embodiment," "an embodiment," "one example embodiment," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0073] For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figure. The terms “overlying”, “atop”, “on top”, “positioned on” or “positioned on top” mean that the first element (e.g., first structure) is present on the second element (e.g., second structure), wherein intervening elements (e.g., interface structures) can be present between the first element and the second element. The term “direct contact” means that the first element (e.g., first structure) and the second element (e.g., second structure) are connected without any intermediate conductive, insulating or semiconductor layers at the interface of the two elements.

[0074] For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figure. The terms “overlying”, “atop”, “on top”, “positioned on” or “positioned on top” mean that the first element (e.g., first structure) is present on the second element (e.g., second structure), wherein intervening elements (e.g., interface structures) can be present between the first element and the second element. The term “direct contact” means that the first element (e.g., first structure) and the second element (e.g., second structure) are connected without any intermediate conductive, insulating or semiconductor layers at the interface of the two elements.

[0075] The terms “about”, “substantially”, “approximately”, and variations thereof, are intended to include amounts that would be recognized by those of ordinary skill in the art as equivalent in context to the recited specific amount. For example, “about” can include ±8% or ±5% or ±2% of a given value.

[0076] The phrase “selective to”, for example, “a first element is selective to a second element” means that the first element can be etched while the second element can act as an etch stop.

[0077] The term “conformal” (e.g., conformal layer or conformal deposition) means that the thickness of the layer is substantially the same across all surfaces, or the thickness varies by less than 15% of the nominal thickness of the layer.

[0078] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to growing a semiconductor material (crystalline material) on a deposited surface of another semiconductor material (crystalline material), where the grown semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material (seed material) of the deposited surface. In an epitaxial deposition process, the chemical reactants provided by source gases can be controlled and system parameters can be set so that the depositing atoms arrive at the deposited surface of the semiconductor substrate with sufficient energy to move on the surface so that the depositing atoms orient themselves to the crystalline arrangement of the atoms of the deposited surface. The epitaxially grown semiconductor material can have substantially the same crystalline properties as the deposited surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} oriented crystalline surface can exhibit a {100} orientation. In some embodiments of the present application, the epitaxial growth and / or deposition process can be selective to form on a semiconductor surface and can or can not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0079] As previously described herein, for the sake of brevity, conventional techniques related to semiconductor devices and integrated circuit (IC) fabrication can or can not be described in detail herein. However, as background, a more general description of semiconductor device fabrication processes that can be used to implement one or more embodiments of the present application will now be provided. Although the particular fabrication operations used in implementing one or more embodiments of the present application can be individually known, the combination of the operations described and / or the resulting structures of the present application are unique. Thus, the unique combination of operations described in connection with the fabrication of semiconductor devices in accordance with the present application utilizes various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.

[0080] Generally, the various processes used to form the microchips that will be packaged into ICs are divided into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto the wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from the wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), and the like. For example, reactive ion etching (RIE) is a dry etching that uses a chemically reactive plasma to remove material, such as a masked pattern of semiconductor material, by exposing the material to ion bombardment that removes portions of the material from the exposed surface. The plasma is typically generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping is the process of changing electrical properties by doping, such as transistor source and drain, typically by diffusion and / or by ion implantation. These doping processes are followed by furnace anneal or rapid thermal anneal (RTA). Annealing is used to activate the implanted dopants. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to change with the application of voltage. By forming structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate in order to subsequently transfer the pattern to the substrate. In semiconductor lithography, the pattern is formed from a light-sensitive polymer called photoresist. To construct the complex structures that make up the transistors and the many wiring of the millions of transistors that make up the circuit, the lithography and etch pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with the previously formed pattern and slowly builds up the conductors, insulators, and selectively doped regions to form the final device.

[0081] The flow diagrams and block diagrams in the drawings are illustrations of the possible implementations of the methods of manufacturing and / or operating in accordance with various embodiments of the present application. Various functions / operations in the methods are represented by blocks in the flow diagrams. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks noted in succession can in fact be executed substantially concurrently or the blocks can sometimes be executed in reverse order, depending on the functionality involved.

[0082] The description of the various embodiments of the application has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technology found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments being described herein.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a line feature in a metallization layer of an interconnect structure, the line feature comprising a line hardmask; forming a trench in the line feature to expose a line end of the line feature; filling the trench with a bulk material; forming a growth inhibitor on a first one of the line ends of the line feature; forming a via mask on a second one of the line ends of the line feature, the via mask selectively grown on an exposed surface of the bulk material; and recessing a portion of the line feature not covered by the via mask to define a self-aligned top via at the second line end.

2. The method of claim 1, wherein the via mask is grown using a selected number of growth cycles to target a predetermined top via size.

3. The method of claim 1, wherein the growth inhibitor prevents the via mask from growing at the first line end.

4. The method of claim 1, wherein the bulk material is selected based on the via mask to ensure that the via mask can be selectively grown on a surface of the bulk material.

5. The method of claim 4, wherein the bulk material is further selected to comprise a wet-removable non-dielectric material.

6. The method of claim 5, wherein the bulk material comprises titanium nitride, titanium oxide, or tantalum nitride.

7. The method of claim 1, further comprising forming a lithographic mask over the line hardmask, the lithographic mask patterned to expose the first line end.

8. The method of claim 7, wherein the growth inhibitor is formed on the exposed first line end.

9. The method of claim 8, wherein the growth inhibitor is grafted to a surface of the line hardmask but not to a surface of the bulk material, such that the surface of the bulk material is exposed.

10. The method of claim 1, further comprising replacing the via mask, the line hardmask, and the bulk material with an interlayer dielectric.

11. The method of claim 1, wherein forming the trench comprises removing a portion of the line feature using etching.

12. The method of claim 1, wherein the line feature comprises a metal line.

13. The method of claim 1, further comprising removing the growth inhibitor prior to recessing a portion of the line feature.

14. A method for forming an interconnect structure, the method comprising: forming a line feature in a metallization layer, the line feature comprising two or more line ends; filling an area between a first one of the two or more line ends and a second one of the two or more line ends with a bulk material; forming a growth inhibitor over the first line end; selectively growing a via mask on an exposed surface of the bulk material; and recessing a portion of the line feature not covered by the via mask to define a self-aligned top via at the second line end.

15. The method of claim 14, wherein the growth inhibitor comprises a self-assembled monolayer.

16. The method of claim 15, wherein the self-assembled monolayer comprises a C6-C18 carbon chain.

17. The method of claim 14, wherein the growth inhibitor comprises a polymer having a molecular weight of 1 to 10,000.

18. The method of claim 17, wherein the polymer comprises a hydroxyl or amine functional group.

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