Array substrate, manufacturing method thereof and display panel

Abstract

An array substrate, a manufacturing method thereof and a display panel, the manufacturing method comprising: forming scan lines and gate electrodes on a substrate; forming a first insulating layer covering the scan lines and the gate electrodes on the substrate; forming a metal-oxide-semiconductor layer above the first insulating layer; the metal-oxide-semiconductor layer comprising a source electrode, a drain electrode and an active layer; coating a photosensitive material layer on an upper surface of the metal-oxide-semiconductor layer; performing photoetching on the photosensitive material layer from a back surface of the substrate using the first metal layer as a mask to form a channel protection layer; performing a conductorization treatment on the metal-oxide-semiconductor layer so that the source electrode and the drain electrode are conductorized; forming data lines above the first insulating layer; and forming pixel electrodes above the first insulating layer. The channel protection layer is made of photosensitive material, and the performance of the active layer is not affected when the channel protection layer is manufactured. The photosensitive material layer is photoetched from the back surface of the substrate, the process is simple, and the gate electrode and the source / drain electrode have substantially no overlapping area, so that the parasitic capacitance is smaller.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display panel. BACKGROUND

[0002] With the development of display technology, thin and light display panels are favored by consumers, especially thin and light liquid crystal display (LCD) panels.

[0003] A display device in the prior art includes a thin film transistor array substrate (TFT Array Substrate), a color filter substrate (CF Substrate), and liquid crystal molecules filled between the thin film transistor array substrate and the color filter substrate. When the display device is working, a driving voltage is applied to the pixel electrode of the thin film transistor array substrate and the common electrode of the color filter substrate, or a driving voltage is applied to the common electrode and the pixel electrode of the thin film transistor array substrate, respectively, to control the rotation direction of the liquid crystal molecules between the two substrates, so as to refract the backlight provided by the backlight module of the display device, thereby displaying the picture.

[0004] Oxide thin film transistors (TFTs) in the prior art have advantages such as excellent electrical performance, large-area manufacturing uniformity, and low manufacturing cost, and are expected to be applied in various flat panel display products. When applied in an LCD display panel, the gate electrode of the bottom-gate TFT can serve as a light shielding layer, which can avoid the degradation of device characteristics caused by the illumination of the oxide active layer. Commonly used bottom-gate oxide TFTs mainly include back channel etching type (BCE) and etching stop layer type (ESL). The BCE type TFT has a simpler manufacturing process. The ESL type TFT needs to consider the overlay alignment of the gate electrode, source electrode and drain electrode with the ESL layer, so the length of the gate electrode cannot be too short, and the overlap amount of the gate electrode with the source electrode and the drain electrode is larger, and the parasitic capacitance of the device is also larger. However, the ESL layer can protect the active layer, so the device characteristics and stability are better. In addition, the bottom-gate homojunction TFT is another optional structure, and its process complexity, device gate length and BCE are comparable, and the active layer is protected by the channel protection layer, which is more conducive to obtaining good device characteristics and stability. The bottom-gate homojunction TFT is expected to have the advantages of BCE type TFT and ESL type TFT.

[0005] However, the channel protection layer of the bottom-gate homojunction TFT is usually made of silicon oxide (SiOx) or silicon nitride (SiNx), and a separate etching process is required for manufacturing the channel protection layer (PL) of the bottom-gate homojunction TFT, which specifically includes film formation, photolithography, etching, and pattern realization after adhesive removal and cleaning, and the process steps are relatively complex. Moreover, the deposition process of the inorganic PL layer can easily affect the oxide active layer, such as the introduction of excessive hydrogen into the active layer during the PECVD (plasma enhanced chemical vapor deposition) film formation process, and the surface damage caused by ion bombardment during sputtering film formation, thereby affecting the performance of the TFT. In addition, the overlapping area of the gate and the source / drain electrode determines the parasitic capacitance of the device, and the overlapping area is determined by the overlay alignment between the PL and the gate, and it is difficult to reduce the parasitic capacitance. SUMMARY

[0006] In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present application is to provide an array substrate and a manufacturing method, and a display panel, so as to solve the problems that the performance of the active layer is affected when manufacturing the channel protection layer in the prior art, and the parasitic capacitance generated by the gate and the source / drain electrode is large.

[0007] The purpose of the present application is achieved by the following technical solutions:

[0008] The present application provides a manufacturing method of an array substrate, comprising:

[0009] providing a substrate;

[0010] forming a first metal layer above the substrate, etching the first metal layer, the first metal layer forming a patterned scan line and a gate, the gate being electrically connected to the scan line;

[0011] forming a first insulating layer covering the scan line and the gate above the substrate;

[0012] forming a metal oxide semiconductor layer above the first insulating layer;

[0013] etching the metal oxide semiconductor layer, the metal oxide semiconductor layer forming a patterned source electrode, a drain electrode, and an active layer, the source electrode and the drain electrode being conductively connected through the active layer;

[0014] coating a photosensitive material layer on the upper surface of the metal oxide semiconductor layer;

[0015] using the first metal layer as a mask plate, performing photolithography on the photosensitive material layer from the side of the substrate away from the photosensitive material layer, the photosensitive material layer forming a patterned channel protection layer;

[0016] With the channel protection layer as a shield, the metal oxide semiconductor layer is subjected to a conductorization treatment, and the regions of the metal oxide semiconductor layer corresponding to the source and the drain are conductorized;

[0017] A second metal layer is formed above the first insulating layer, the second metal layer is etched and patterned to form a data line, and the data line is in conductive connection with the source;

[0018] A pixel electrode is formed above the first insulating layer, and the pixel electrode is in conductive connection with the drain.

[0019] Further, before etching the metal oxide semiconductor layer, the photosensitive material layer is coated on the upper surface of the metal oxide semiconductor layer;

[0020] The photosensitive material layer is subjected to a first photoetching, and the photosensitive material layer forms an etching barrier layer;

[0021] The metal oxide semiconductor layer is etched with the etching barrier layer as a shield, and the metal oxide semiconductor layer forms the patterned source, drain, and active layer, and the source and the drain are in conductive connection through the active layer;

[0022] With the first metal layer as a shield, the photosensitive material layer is subjected to a second photoetching from the side of the substrate away from the photosensitive material layer, and the photosensitive material layer forms a patterned channel protection layer.

[0023] Further, after forming the metal oxide semiconductor layer above the first insulating layer, the metal oxide semiconductor layer is etched by an etching process, and the metal oxide semiconductor layer forms the patterned source, drain, and active layer, and the source and the drain are in conductive connection through the active layer;

[0024] The photosensitive material layer is coated on the upper surface of the etched metal oxide semiconductor layer, and the photosensitive material layer is subjected to photoetching from the side of the substrate away from the photosensitive material layer with the first metal layer as a mask, and the photosensitive material layer forms a patterned channel protection layer.

[0025] Further, the specific steps of the conductorization treatment of the metal oxide semiconductor layer include:

[0026] The metal oxide semiconductor layer is subjected to a plasma treatment with the channel protection layer as a shield.

[0027] Further, the specific steps of the conductorization treatment of the metal oxide semiconductor layer include:

[0028] After the photoactive material layer forms the patterned channel protection layer, hydrogen is introduced to the exposed area of the metal oxide semiconductor layer and hydrogen doping is performed, and a second insulating layer is formed on the surface of the metal oxide semiconductor layer by a chemical vapor deposition process. During the formation of the second insulating layer, the area of the metal oxide semiconductor layer in contact with the second insulating layer is conductorized.

[0029] Further, the metal oxide semiconductor layer is made of a transparent metal oxide semiconductor material. When the metal oxide semiconductor layer is etched, the metal oxide semiconductor layer also forms a patterned pixel electrode, which is conductively connected to the drain electrode.

[0030] When the metal oxide semiconductor layer is conductorized, the areas of the metal oxide semiconductor layer corresponding to the source electrode, the drain electrode, and the pixel electrode are conductorized.

[0031] Further, the pixel electrode and the metal oxide semiconductor layer are located in different layers.

[0032] Further, before forming the metal oxide semiconductor layer on the top surface of the first insulating layer, the second metal layer is formed on the top surface of the first insulating layer. The second metal layer is etched to form a patterned data line.

[0033] After forming the data line, the metal oxide semiconductor layer is formed on the top surface of the first insulating layer, covering the data line.

[0034] The metal oxide semiconductor layer is etched to form a patterned source electrode, a drain electrode, and an active layer. The source electrode and the drain electrode are conductively connected through the active layer, and the source electrode is conductively connected to the data line.

[0035] Further, after the metal oxide semiconductor layer is conductorized, the second metal layer is formed on the surface of the metal oxide semiconductor layer. The second metal layer is etched to form a patterned data line, which is conductively connected to the source electrode.

[0036] Further, after the metal oxide semiconductor layer is conductorized, a second insulating layer is formed on the top surface of the metal oxide semiconductor layer.

[0037] The second metal layer is formed on the top surface of the second insulating layer. The second metal layer is etched to form a patterned data line, which is conductively connected to the source electrode.

[0038] Further, a transparent conductive layer is formed above the first insulating layer, and the transparent conductive layer is etched to form a common electrode, which is insulated from the pixel electrode.

[0039] Further, the common electrode is above the pixel electrode and has a slit structure.

[0040] The application further provides an array substrate manufactured by the manufacturing method.

[0041] The application further provides a display panel, which comprises the array substrate, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the opposite substrate.

[0042] The application has the advantages that: the channel protection layer is made of a photosensitive material, and the photosensitive material layer is formed by a coating process instead of a chemical vapor deposition process, so that the performance of the active layer is not affected when the photosensitive material layer is coated, and the TFT characteristics and stability are not affected by the environment; and the photosensitive material layer is photoetched from the back of the substrate by using the first metal layer as a mask, so that no additional mask is needed, the manufacturing process is simpler, the gate electrode has no overlapping area with the source electrode and the drain electrode, the parasitic capacitance is smaller, and the impact on the picture display is smaller. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a sectional view of an array substrate in the first embodiment of the application;

[0044] Figures 2a-2h is a sectional view of a manufacturing method of an array substrate in the first embodiment of the application;

[0045] Figures 3a-3f is a plan view of the manufacturing method of the array substrate in the first embodiment of the application;

[0046] Figures 4a-4g is a sectional view of a manufacturing method of an array substrate in the second embodiment of the application;

[0047] Figures 5a-5f is a plan view of the manufacturing method of the array substrate in the second embodiment of the application;

[0048] Figure 6 is a sectional view of an array substrate in the third embodiment of the application;

[0049] Figure 7 is a sectional view of an array substrate in the fourth embodiment of the application;

[0050] Figure 8This is a schematic diagram of the cross-sectional structure of the array substrate in Embodiment 5 of the present invention;

[0051] Figure 9 This is a schematic diagram of the cross-sectional structure of the display panel in this invention. Detailed Implementation

[0052] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the specific implementation methods, structure, features and effects of the present invention are described in detail below with reference to the accompanying drawings and preferred embodiments:

[0053] [Example 1]

[0054] Figure 1 This is a cross-sectional schematic diagram of the array substrate in Embodiment 1 of the present invention. Figures 2a-2h This is a cross-sectional schematic diagram of the method for fabricating the array substrate in Embodiment 1 of the present invention. Figures 3a-3f This is a planar schematic diagram of the method for fabricating the array substrate in Embodiment 1 of the present invention. Figures 1 to 3f As shown, Embodiment 1 of the present invention provides a method for fabricating an array substrate, comprising:

[0055] like Figure 2a and Figure 3a As shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0056] A first metal layer 11 is formed on the substrate 10. Figure 3a The first metal layer 11 is etched to form patterned scan lines 111. Figure 3a The first metal layer 11 consists of a photoresist layer and a gate 112, which is electrically connected to the scan line 111. The specific steps for etching the first metal layer 11 include: applying photoresist, exposure using a photomask, development, etching, and photoresist removal. The first metal layer 11 can be made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of these metals, such as Al / Mo or Cu / Mo.

[0057] A first insulating layer 101 is formed on the substrate 10, covering the scan line 111 and the gate 112. The first insulating layer 101 is a gate insulating layer, and the first insulating layer 101 is disposed on the entire surface of the substrate 10 and covers the gate 112 and the scan line 111. The material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0058] In this embodiment, as Figure 2b As shown, a metal oxide semiconductor layer 12 is formed on the upper surface of the first insulating layer 101. Before etching the metal oxide semiconductor layer 12, a photosensitive material layer 13 is first coated on the upper surface of the metal oxide semiconductor layer 12. That is, after the metal oxide semiconductor layer 12 is formed on the upper surface of the first insulating layer 101, the photosensitive material layer 13 is then coated on the upper surface of the metal oxide semiconductor layer 12. The photosensitive material layer 13 is made of a positive photosensitive polyimide material, such as positive photosensitive polyimide photoresist (PI), and the thickness of the photosensitive material layer 13 is preferably 200 nm to 3000 nm. The coating process differs significantly from chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) processes. The coating process uses rollers, spin coating, or other physical methods to cover the photosensitive material onto the metal oxide semiconductor layer 12, which does not affect the properties of the metal oxide semiconductor layer 12 and is beneficial for the TFT characteristics and stability to be unaffected by the environment.

[0059] In this embodiment, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO). During etching of the metal oxide semiconductor layer 12, patterned pixel electrodes 124 are also formed on the metal oxide semiconductor layer 12. The pixel electrodes 124 are directly conductively connected to the drain electrode 122. That is, in this embodiment, the pixel electrodes 124, the source electrode 121, the drain electrode 122, and the active layer 123 are located on the same layer and are all formed by etching the metal oxide semiconductor layer 12.

[0060] like Figure 2cAs shown, the first photoetching (including exposure and development) is performed on the photosensitive material layer 13, and the photosensitive material layer 13 forms an etching blocking layer 130. The exposure and development are performed on the photosensitive material layer 13 above the mask plate 100, and since the photosensitive material layer 13 is made of a positive photosensitive polyimide material, the first photoetching of the photosensitive material layer 13 only needs to be performed by the exposure and development processes, without additional photoresist coating and photoresist removing processes, thereby simplifying the manufacturing process flow.

[0061] As shown in Figure 2d and 3b the etching blocking layer 130 is used as a shield to etch the metal oxide semiconductor layer 12, and the metal oxide semiconductor layer 12 forms a patterned source electrode 121, a patterned drain electrode 122, and a patterned active layer 123. The source electrode 121 and the drain electrode 122 are conductively connected through the active layer 123. Thus, when the metal oxide semiconductor layer 12 is etched, no additional photoresist coating and photoresist removing processes are needed, thereby simplifying the manufacturing process flow.

[0062] As shown in Figure 2e and 3c the second photoetching (including exposure and development) is performed on the photosensitive material layer 13 from the side of the substrate 10 away from the photosensitive material layer 13 (i.e., the back of the substrate 10) using the gate electrode 112 as a shield, and the photosensitive material layer 13 forms a channel protection layer 131 at the position corresponding to the gate electrode 112. That is, the photosensitive material layer 13 is photoetched from the side of the substrate 10 away from the photosensitive material layer 13 using the gate electrode 112 as a mask, so that the photosensitive material layer 13 forms a patterned channel protection layer 131. After the second photoetching of the photosensitive material layer 13, the photosensitive material layer 13 at the positions corresponding to the source electrode 121, the drain electrode 122, and the pixel electrode 124 is removed, so that the source electrode 121, the drain electrode 122, and the pixel electrode 124 are exposed, but the active layer 123 is covered by the channel protection layer 131. In this embodiment, the gate electrode 112 is used as a mask, thereby saving one mask plate, simplifying the manufacturing process, and also making the gate electrode 112 and the source electrode 121 and the drain electrode 122 have substantially no overlapping area, so that the parasitic capacitance is smaller and the impact on the picture display is smaller. Further, after the channel protection layer 131 is formed, baking is performed on the channel protection layer 131 to accelerate the solidification of the channel protection layer 131.

[0063] As shown in Figure 2f and 3dAs shown, the exposed region of the metal oxide semiconductor layer 12 (i.e. the region not covered by the channel protection layer 131) is subjected to a conductorization process, and the regions of the metal oxide semiconductor layer 12 corresponding to the source 121, the drain 122 and the pixel electrode 124 are conductorized. Specifically, the exposed region of the metal oxide semiconductor layer 12 is subjected to a conductorization process with the channel protection layer 131 as a shield, so that the regions of the metal oxide semiconductor layer 12 corresponding to the source 121, the drain 122 and the pixel electrode 124 are conductorized.

[0064] In this embodiment, the specific steps of the conductorization process of the exposed region of the metal oxide semiconductor layer 12 include: using plasma treatment on the exposed region of the metal oxide semiconductor layer 12 with the channel protection layer 131 as a shield, and making the metal oxide semiconductor layer 12 not covered by the channel protection layer 131 conductorized by ion bombardment or hydrogen doping, that is, making the source 121, the drain 122 and the pixel electrode 124 conductorized.

[0065] Since the active layer 123 is covered by the channel protection layer 131, the channel protection layer 131 has good hydrogen blocking ability, which is conducive to avoiding the introduction of hydrogen into the active layer 123 during the conductorization process of the metal oxide semiconductor layer 12, so as to avoid the conductorization of the active layer 123.

[0066] As shown in FIG. 6, the exposed region of the metal oxide semiconductor layer 12 is subjected to a conductorization process with the channel protection layer 131 as a shield, so that the regions of the metal oxide semiconductor layer 12 corresponding to the source 121, the drain 122 and the pixel electrode 124 are conductorized. Figure 2g and 3eAs shown, after the conductorization treatment of the metal oxide semiconductor layer 12, a second metal layer 14 is formed above the metal oxide semiconductor layer 12, the second metal layer 14 is etched and patterned into data lines 141, which are in electrical connection with the source 121. Specifically, after the conductorization treatment of the metal oxide semiconductor layer 12, a second insulating layer 102 is formed on the first insulating layer 101, covering the channel protection layer 131, the source 121, the drain 122, the pixel electrode 124 and the upper surface of the first insulating layer 101; then the second insulating layer 102 is etched and opened at the positions corresponding to the source 121, so that the second insulating layer 102 forms contact holes 104 at the positions corresponding to the source 121; then a second metal layer 14 is formed on the upper surface of the second insulating layer 102, the second metal layer 14 fills into the contact holes 104 and is in contact with the source 121, the second metal layer 14 is etched and patterned into data lines 141, which are in electrical connection with the source 121. The second metal layer 14 can be made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above-mentioned metals, such as Al / Mo, Cu / Mo, etc.; the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two. The specific steps of etching the second insulating layer 102 and the second metal layer 14 include: coating photoresist (photoresist), using a mask plate for exposure, developing, etching and removing photoresist, etc.

[0067] As Figure 2h and 3fAs shown, a third insulating layer 103 is formed on the upper surface of the second insulating layer 102, the third insulating layer 103 covers the data line 141, and then a transparent conductive layer 15 is formed on the third insulating layer 103. The transparent conductive layer 15 is etched to form a common electrode 151, and the common electrode 151 is insulated from the pixel electrode 124. Specifically, the common electrode 151 is in a comb structure in the region corresponding to the pixel electrode 124, and the common electrode 151 and the pixel electrode 124 are spaced apart from each other by the second insulating layer 102 and the third insulating layer 103, so that the array substrate can be applied to a display in a fringe field switching (FFS) mode. The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two. The transparent conductive layer 15 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO). The specific steps of etching the transparent conductive layer 15 include coating photoresist (photoresist), using a mask plate for exposure, development, etching, and removing photoresist.

[0068] In other embodiments, the common electrode 151 can also be provided on the lower side of the pixel electrode 124. Alternatively, the common electrode 151 can also not be made on the array substrate, so that the array substrate can be applied to a display in a TN or VA mode.

[0069] Wherein, the direction of the substrate 10 towards the first metal layer 11 is the upward direction, and the direction of the substrate 10 away from the first metal layer 11 is the downward direction.

[0070] The embodiment also provides an array substrate made by the above manufacturing method.

[0071] [Embodiment Two]

[0072] Figures 4a-4g is a cross-sectional schematic view of the manufacturing method of the array substrate in the second embodiment of the present application, Figures 5a-5f is a plan view of the manufacturing method of the array substrate in the second embodiment of the present application. As Figures 4a to 5f shown, the manufacturing method of the array substrate provided in the second embodiment of the present application comprises:

[0073] As Figure 4a and Figure 5aAs shown, a substrate 10 is provided, which can be made of glass, quartz, silicon, acrylic or polycarbonate, etc. The substrate 10 can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyether sulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

[0074] A first metal layer 11 is formed on the substrate 10 (as shown in FIG. 1B). Figure 5a The first metal layer 11 is etched to form a patterned scan line 111 and a gate 112 electrically connected to the scan line 111. Figure 5a The specific steps of etching the first metal layer 11 include: coating photoresist (photoresist), using a mask plate for exposure, development, etching, and removing photoresist, etc. The first metal layer 11 can be made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above-mentioned metals, such as Al / Mo, Cu / Mo, etc.

[0075] A first insulating layer 101 covering the scan line 111 and the gate 112 is formed on the substrate 10. The first insulating layer 101 is a gate insulating layer, which is provided on the substrate 10 in a full surface manner and covers the gate 112 and the scan line 111. The material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0076] As shown in FIG. 1C, a metal oxide semiconductor layer 12 is formed on the upper surface of the first insulating layer 101. Figure 4b 5b The metal oxide semiconductor layer 12 is etched to form a patterned source 121, a drain 122, and an active layer 123. The source 121 and the drain 122 are conductively connected through the active layer 123.

[0077] ​In this embodiment, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO). During etching of the metal oxide semiconductor layer 12, patterned pixel electrodes 124 are also formed on the metal oxide semiconductor layer 12. The pixel electrodes 124 are directly conductively connected to the drain electrode 122. That is, in this embodiment, the pixel electrodes 124, the source electrode 121, the drain electrode 122, and the active layer 123 are located on the same layer and are all formed by etching the metal oxide semiconductor layer 12.

[0078] like Figure 4c As shown, a photosensitive material layer 13 is coated on the upper surface of the etched metal oxide semiconductor layer 12. The photosensitive material layer 13 is made of a positive photosensitive polyimide material, such as positive photosensitive polyimide photoresist (PI), and the thickness of the photosensitive material layer 13 is preferably 200 nm to 3000 nm. The coating process differs significantly from chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) processes. The coating process uses rollers, spin coating, or other physical methods to cover the photosensitive material onto the metal oxide semiconductor layer 12, which does not affect the properties of the metal oxide semiconductor layer 12 and is beneficial for the TFT characteristics and stability to be unaffected by the environment.

[0079] like Figure 4d and 5c As shown, using the first metal layer 11 as a mask, photolithography is performed on the photosensitive material layer 13 from the side of the substrate 10 away from the photosensitive material layer 13 (i.e., the back side of the substrate 10), forming a channel protection layer 131 at the position corresponding to the gate 112. That is, using the first metal layer 11 as a mask, photolithography is performed on the photosensitive material layer 13 from the side of the substrate 10 away from the photosensitive material layer 13, forming a patterned channel protection layer 131. After photolithography of the photosensitive material layer 13, the photosensitive material layer 13 corresponding to the positions of the source 121, drain 122, and pixel electrode 124 is removed, exposing the source 121, drain 122, and pixel electrode 124, but the active layer 123 is covered by the channel protection layer 131. In this embodiment, the gate 112 and the scan line 111 are used as a mask, which saves one mask and simplifies the manufacturing process. In addition, the gate 112 has virtually no overlapping area with the source 121 and the drain 122, resulting in smaller parasitic capacitance and less impact on the display.

[0080] like Figure 4e and 5dAs shown, the exposed regions of the metal-oxide semiconductor layer 12 (i.e. the regions not covered by the channel protection layer 131) are subjected to a conductorization process, and the regions of the metal-oxide semiconductor layer 12 corresponding to the source 121, the drain 122 and the pixel electrode 124 are conductorized. Specifically, the exposed regions of the metal-oxide semiconductor layer 12 are subjected to a conductorization process with the channel protection layer 131 as a shield, so that the regions of the metal-oxide semiconductor layer 12 corresponding to the source 121, the drain 122 and the pixel electrode 124 are conductorized.

[0081] In this embodiment, the specific steps of the conductorization process of the exposed regions of the metal-oxide semiconductor layer 12 include: after the photoactive material layer 13 forms the patterned channel protection layer 131, a chemical vapor deposition process (CVD, PECVD, ALD, etc.) is used to form a second insulating layer 102 on the upper surface of the metal-oxide semiconductor layer 12. During the formation of the second insulating layer 102, hydrogen is introduced into the exposed regions of the metal-oxide semiconductor layer 12 for hydrogen doping, so that the metal-oxide semiconductor layer 12 not covered by the channel protection layer 131 is conductorized, i.e. the source 121, the drain 122 and the pixel electrode 124 are conductorized. By conductorizing the source 121, the drain 122 and the pixel electrode 124 during the formation of the second insulating layer 102, the manufacturing process can be simplified.

[0082] In other embodiments, the specific steps of the conductorization process of the exposed regions of the metal-oxide semiconductor layer 12 can refer to the first embodiment described above, and include: using the channel protection layer 131 as a shield, the metal-oxide semiconductor layer 12 is subjected to a plasma treatment, so that the metal-oxide semiconductor layer 12 not covered by the channel protection layer 131 is conductorized, i.e. the source 121, the drain 122 and the pixel electrode 124 are conductorized.

[0083] Since the active layer 123 is covered by the channel protection layer 131, the channel protection layer 131 has good hydrogen blocking ability, which is conducive to avoiding the introduction of hydrogen into the active layer 123 during the conductorization process of the metal-oxide semiconductor layer 12, so that the active layer 123 is conductorized.

[0084] As shown in FIG. 1, the channel protection layer 131 is formed on the upper surface of the metal-oxide semiconductor layer 12, and the channel protection layer 131 is patterned to expose the source 121, the drain 122 and the pixel electrode 124. Figure 4f and 5eAs shown, after the conductorization treatment of the metal oxide semiconductor layer 12, a second metal layer 14 is formed above the metal oxide semiconductor layer 12, the second metal layer 14 is etched and patterned into data lines 141, which are in electrical connection with the source 121. Specifically, after the conductorization treatment of the metal oxide semiconductor layer 12, a second insulating layer 102 is formed on the first insulating layer 101, covering the channel protection layer 131, the source 121, the drain 122, the pixel electrode 124 and the upper surface of the first insulating layer 101; then the second insulating layer 102 is etched and opened at the positions corresponding to the source 121, so that the second insulating layer 102 forms contact holes 104 at the positions corresponding to the source 121; then a second metal layer 14 is formed on the upper surface of the second insulating layer 102, the second metal layer 14 fills into the contact holes 104 and is in contact with the source 121, the second metal layer 14 is etched and patterned into data lines 141, which are in electrical connection with the source 121. The second metal layer 14 can be made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above-mentioned metals, such as Al / Mo, Cu / Mo, etc.; the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two. The specific steps of etching the second insulating layer 102 and the second metal layer 14 include: coating photoresist (photoresist), using a mask plate for exposure, developing, etching and removing photoresist, etc.

[0085] As Figure 4g and 5fAs shown, a third insulating layer 103 is formed on the upper surface of the second insulating layer 102, the third insulating layer 103 covers the data line 141, and then a transparent conductive layer 15 is formed on the third insulating layer 103. The transparent conductive layer 15 is etched to form a common electrode 151, and the common electrode 151 is insulated from the pixel electrode 124. Specifically, the common electrode 151 is in a comb structure in the region corresponding to the pixel electrode 124, and the common electrode 151 and the pixel electrode 124 are spaced apart from each other by the second insulating layer 102 and the third insulating layer 103, so that the array substrate can be applied to a display in a fringe field switching (FFS) mode. The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two. The transparent conductive layer 15 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO). The specific steps of etching the transparent conductive layer 15 include coating photoresist (photoresist), using a mask plate for exposure, development, etching, and removing photoresist.

[0086] In other embodiments, the common electrode 151 can also be provided on the lower side of the pixel electrode 124. Alternatively, the common electrode 151 can also not be formed on the array substrate, so that the array substrate can be applied to a display in a TN or VA mode.

[0087] The embodiment also provides an array substrate made by the above manufacturing method.

[0088] [Embodiment Three]

[0089] Figure 6 is a schematic view of the cross-sectional structure of the array substrate in Embodiment Three of the present application. As shown, the manufacturing method of the array substrate provided in Embodiment Three of the present application is the same as that in Embodiment One ( Figure 6 ) or Embodiment Two ( Figures 1 to 3f ). Figures 4a to 5fThe fabrication method of the array substrate in this embodiment is basically the same as that in the previous embodiment. The difference is that, after the metal oxide semiconductor layer 12 is conductiveized, a second metal layer 14 is formed on top of the metal oxide semiconductor layer 12. The second metal layer 14 is etched to form patterned data lines 141, which are conductively connected to the source electrode 121. Specifically, after the metal oxide semiconductor layer 12 is conductiveized, a second metal layer 14 is formed on the upper surface of the first insulating layer 101. The second metal layer 14 covers the channel protection layer 131, the source electrode 121, the drain electrode 122, the pixel electrode 124, and the upper surface of the first insulating layer 101. The second metal layer 14 is in direct contact with the source electrode 121. The second metal layer 14 is etched to form patterned data lines 141, which are directly conductively connected to the source electrode 121.

[0090] Then, a second insulating layer 102 is formed on the upper surface of the first insulating layer 101, and the second insulating layer 102 covers the upper surface of the channel protection layer 131, the source electrode 121, the drain electrode 122, the pixel electrode 124, the first insulating layer 101, and the data line 141.

[0091] This embodiment also provides an array substrate, which is manufactured using the above-described manufacturing method.

[0092] Compared to Embodiment 1 or Embodiment 2, this embodiment first fabricates the data cable 141 and then covers it with the second insulating layer 102, thus eliminating the need to etch the second insulating layer 102 to form the contact hole 104, and also eliminating the need to cover the second insulating layer 10 with a third insulating layer 103, further simplifying the manufacturing process and saving manufacturing costs.

[0093] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1 or Embodiment 2, and will not be repeated here.

[0094] [Example 4]

[0095] Figure 7 This is a schematic cross-sectional view of the array substrate in Embodiment 4 of the present invention. Figure 7 As shown, the method for fabricating the array substrate provided in Embodiment 4 of the present invention is the same as that in Embodiment 1. Figures 1 to 3f ) or Example 2 ( Figures 4a to 5f The fabrication method of the array substrate in the embodiment is basically the same as that in the embodiment. The difference is that, before forming the metal oxide semiconductor layer 12 on the upper surface of the first insulating layer 101, a second metal layer 14 is first formed on the upper surface of the first insulating layer 101, and the second metal layer 14 is etched to form patterned data lines 141.

[0096] After the data line 141 is formed, a metal-oxide semiconductor layer 12 is formed on the upper surface of the first insulating layer 101, covering the data line 141, and then the metal-oxide semiconductor layer 12 is etched to form a patterned source electrode 121, a drain electrode 122, an active layer 123, and a pixel electrode 124, the source electrode 121 and the drain electrode 122 being electrically connected through the active layer 123, the drain electrode 122 being electrically connected with the pixel electrode 124, and the source electrode 121 being in electrical contact with the data line 141.

[0097] The embodiment also provides an array substrate made by the manufacturing method.

[0098] Compared with the first embodiment or the second embodiment, the data line 141 is formed first in the embodiment, and then the metal-oxide semiconductor layer 12 is formed to cover the data line 141, so that the second insulating layer 102 does not need to be etched to form the contact hole 104, and a third insulating layer 103 does not need to be formed on the second insulating layer 102, thereby further simplifying the manufacturing process and saving manufacturing cost.

[0099] Those skilled in the art should understand that the remaining structure and working principle of the embodiment are the same as those of the first embodiment or the second embodiment, and will not be described here.

[0100] [Embodiment Five]

[0101] Figure 8 is a schematic diagram of the cross-sectional structure of an array substrate in the fifth embodiment of the present application. As shown in the figure, Figure 8 the manufacturing method of the array substrate provided by the fifth embodiment of the present application is basically the same as that in the first embodiment ( Figures 1 to 3f ) or the second embodiment ( Figures 4a to 5f ), and the difference lies in that, in the present embodiment, after the second insulating layer 102 is formed on the first insulating layer 101, the second insulating layer 102 is etched to form an opening at a position corresponding to the drain electrode 122, so that the drain electrode 122 leaks out of the opening.

[0102] A transparent conductive material layer is formed on the upper surface of the second insulating layer 102, and the transparent conductive material layer is etched to form the pixel electrode 124, the pixel electrode 124 being electrically connected with the drain electrode 122 through the opening. The transparent conductive material may be indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0103] The embodiment also provides an array substrate, which is manufactured by the manufacturing method.

[0104] Compared with the first embodiment or the second embodiment, the embodiment additionally sets a transparent conductive material layer and uses the transparent conductive material layer to manufacture the pixel electrode 124. When the metal oxide semiconductor layer 12 is etched, the metal oxide semiconductor layer 12 does not need to form the pixel electrode 124, so that the distance between the pixel electrode 124 and the common electrode 151 is smaller, the driving electric field is more easily formed, and the driving power consumption is saved.

[0105] Those skilled in the art should understand that the remaining structure and working principle of the embodiment are the same as those of the first embodiment or the second embodiment, which will not be described here.

[0106] Figure 9 is a schematic diagram of a cross-sectional structure of a display panel in the embodiment. As shown in Figure 9 The embodiment also provides a display panel, which comprises an array substrate, an opposite substrate 20 arranged opposite to the array substrate, and a liquid crystal layer 30 arranged between the array substrate and the opposite substrate 20, and the array substrate is manufactured by the manufacturing method. An upper polarizer 41 is arranged on the opposite substrate 20, and a lower polarizer 42 is arranged on the array substrate, and the transmission axis of the upper polarizer 41 and the transmission axis of the lower polarizer 42 are perpendicular to each other. In the embodiment, the liquid crystal molecules in the liquid crystal layer 30 are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy), and in the initial state, the positive liquid crystal molecules are in a flat posture, and the alignment direction of the positive liquid crystal molecules close to the opposite substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules 131 close to the array substrate. It can be understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer on the side facing the liquid crystal layer 30, so as to align the positive liquid crystal molecules in the liquid crystal layer 30.

[0107] In the embodiment, the opposite substrate 20 is a color film substrate, the opposite substrate 20 is provided with a black matrix 21 and a color resistance layer 22, the black matrix 21 corresponds to the scan lines 111, the data lines 141, the thin film transistors and the peripheral non-display area, and the black matrix 21 separates the plurality of color resistance layers 22. The color resistance layer 22 comprises color resistance materials of red (R), green (G) and blue (B), and corresponds to form sub-pixels of red (R), green (G) and blue (B).

[0108] In this document, the orientation words such as up, down, left, right, front, back and the like are defined according to the position of the structure in the drawing and the position of the structure relative to each other, only for the purpose of expressing the technical scheme clearly and conveniently. It should be understood that the use of the orientation words should not limit the scope of the application claimed. It should also be understood that the terms "first" and "second" and the like used in this document are only used for name distinction, and do not limit the quantity and order.

[0109] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes or modifications to the above disclosed technical contents without departing from the technical solution of the present application, and the equivalent embodiments with equivalent changes are also included. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application are still within the protection scope of the technical solution of the present application.

Claims

1. A method for fabricating an array substrate, characterized in that, include: Provide a base (10); A first metal layer (11) is formed on the substrate (10), and the first metal layer (11) is etched. The first metal layer (11) forms patterned scan lines (111) and gates (112), and the gates (112) are electrically connected to the scan lines (111). A first insulating layer (101) is formed over the substrate (10) to cover the scan line (111) and the gate (112); A metal oxide semiconductor layer (12) is formed above the first insulating layer (101); Before etching the metal oxide semiconductor layer (12), a photosensitive material layer (13) is first coated on the upper surface of the metal oxide semiconductor layer (12); The photosensitive material layer (13) is subjected to a first photolithography, and the photosensitive material layer (13) forms an etch barrier layer (130); The metal oxide semiconductor layer (12) is etched using the etch barrier layer (130) as a shield. The metal oxide semiconductor layer (12) forms a patterned source (121), drain (122) and active layer (123). The source (121) and drain (122) are electrically connected through the active layer (123). Using the gate (112) as a shield, a second photolithography is performed on the photosensitive material layer (13) from the side of the substrate (10) away from the photosensitive material layer (13), and a patterned channel protection layer (131) is formed on the photosensitive material layer (13). Using the channel protection layer (131) as a shield, the metal oxide semiconductor layer (12) is conductiveized, and the regions of the metal oxide semiconductor layer (12) corresponding to the source (121) and the drain (122) are conductiveized; A second metal layer (14) is formed above the first insulating layer (101), and the second metal layer (14) is etched to form patterned data lines (141), which are electrically connected to the source (121). A pixel electrode (124) is formed above the first insulating layer (101), and the pixel electrode (124) is electrically connected to the drain (122).

2. The method for fabricating an array substrate according to claim 1, characterized in that, The specific steps for conducting the conductor treatment of the metal oxide semiconductor layer (12) include: Using the channel protection layer (131) as a shield, the metal oxide semiconductor layer (12) is subjected to plasma treatment.

3. The method for fabricating an array substrate according to claim 1, characterized in that, The specific steps for conducting the conductor treatment of the metal oxide semiconductor layer (12) include: After the photosensitive material layer (13) forms the patterned channel protection layer (131), hydrogen is introduced into the exposed area of ​​the metal oxide semiconductor layer (12) and hydrogen doping is performed. A second insulating layer (102) is formed on the upper surface of the metal oxide semiconductor layer (12) using a chemical vapor deposition process. During the formation of the second insulating layer (102), the area where the metal oxide semiconductor layer (12) contacts the second insulating layer (102) is made conductive.

4. The method for fabricating an array substrate according to claim 1, characterized in that, The metal oxide semiconductor layer (12) is made of transparent metal oxide semiconductor material. When etching the metal oxide semiconductor layer (12), the metal oxide semiconductor layer (12) also forms patterned pixel electrodes (124), which are electrically connected to the drain electrode (122). When the metal oxide semiconductor layer (12) is subjected to a conductor treatment, the regions of the metal oxide semiconductor layer (12) corresponding to the source (121), the drain (122) and the pixel electrode (124) are conductor-treated.

5. The method for fabricating an array substrate according to claim 1, characterized in that, The pixel electrode (124) and the metal oxide semiconductor layer (12) are located on different layers.

6. The method for fabricating an array substrate according to claim 1, characterized in that, Before forming the metal oxide semiconductor layer (12) above the first insulating layer (101), the second metal layer (14) is first formed on the upper surface of the first insulating layer (101), and the second metal layer (14) is etched to form the patterned data line (141); After the data line (141) is formed, the metal oxide semiconductor layer (12) is formed on the upper surface of the first insulating layer (101), and the metal oxide semiconductor layer (12) covers the data line (141); The metal oxide semiconductor layer (12) is etched to form a patterned source (121), drain (122) and active layer (123). The source (121) and drain (122) are electrically connected through the active layer (123). The source (121) is in conductive contact with the data line (141).

7. The method for fabricating an array substrate according to claim 1, characterized in that, After the metal oxide semiconductor layer (12) is conductively processed, a second metal layer (14) is formed on the upper surface of the metal oxide semiconductor layer (12), and the second metal layer (14) is etched to form the patterned data line (141), which is electrically connected to the source (121).

8. The method for fabricating an array substrate according to claim 1, characterized in that, After the metal oxide semiconductor layer (12) is conductive, a second insulating layer (102) is formed on the upper surface of the metal oxide semiconductor layer (12); A second metal layer (14) is formed on the upper surface of the second insulating layer (102), and the second metal layer (14) is etched to form a patterned data line (141), which is electrically connected to the source (121).

9. The method for fabricating an array substrate according to claim 1, characterized in that, A transparent conductive layer (15) is formed above the first insulating layer (101), and the transparent conductive layer (15) is etched to form a common electrode (151). The common electrode (151) is insulated from the pixel electrode (124).

10. The method for fabricating an array substrate according to claim 9, characterized in that, The common electrode (151) is located above the pixel electrode (124), and the common electrode (151) has a slit structure.

11. The method for fabricating an array substrate according to claim 1, characterized in that, The photosensitive material layer (13) is made of positive photosensitive polyimide.

12. An array substrate, characterized in that, The array substrate is manufactured using the method described in any one of claims 1-11.

13. A display panel, characterized in that, It includes the array substrate as described in claim 12, the opposing substrate (20) disposed opposite to the array substrate, and the liquid crystal layer (30) disposed between the array substrate and the opposing substrate (20).

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