Low-ripple digital LDO circuit without external capacitors

Abstract

The present invention discloses a low-ripple digital LDO circuit without off-chip capacitors, which consists of a control module, a three-way selector, a carry / borrow control module, and MOS transistor arrays of three sizes S, M, and L to form a three-loop structure digital LDO without off-chip capacitors, and a feed-forward minimum LCO maintenance module is introduced. This digital LDO has excellent load driving ability and low output voltage ripple, and can achieve fast load regulation at a clock frequency of dozens of MHz, greatly alleviating the constraint relationship between transient response performance and power consumption. In addition, due to the advantage of the three-loop structure that can implement multiple adjustment modes, and the function of the feed-forward minimum LCO maintenance module to reduce the number of MOS transistors operating in a loop in the steady state, the circuit of this patent only requires a few pF of on-chip capacitors, enabling the implementation of a low-ripple digital LDO circuit with a three-loop fast adjustment structure.

Description

Technical Field

[0001] The present invention relates to the technical field of low dropout voltage regulators (LDOs), and particularly to a low-ripple digital LDO circuit without an external capacitor. Background Art

[0002] Traditional low dropout voltage regulators are analog low dropout voltage regulators (analog LDOs). The analog low dropout voltage regulator uses a high-gain error amplifier to regulate the output voltage. In advanced processes, the power supply voltage of some systems is reduced to the subthreshold region. Due to the very low input voltage and control voltage, it is difficult for the design of an analog LDO centered on a high-gain error amplifier to meet the index requirements. To solve this problem, digital low dropout voltage regulators (digital LDOs) have emerged. The advantages of digital LDOs are that they can operate under low input voltage conditions, are convenient for process upgrade and iteration, and are easy to transplant. However, due to the excellent transient response performance requiring large-sized MOS transistors or extremely high clock frequencies, large-sized MOS transistors mean large output ripple, and high frequencies mean increased power consumption. Therefore, digital LDOs have problems of large output voltage ripple and difficulty in achieving both transient response and power consumption. Although using an nF-level external capacitor can reduce the ripple to a certain extent, it is not conducive to full integration. Summary of the Invention

[0003] The present invention provides a low-ripple digital LDO circuit without an external capacitor to solve the problems of large output voltage ripple and difficulty in achieving both transient response and power consumption existing in existing digital LDOs.

[0004] To solve the above problems, the present invention is implemented through the following technical solutions:

[0005] The low-ripple digital LDO circuit without an external capacitor is composed of a synchronous comparator, two control modules, three multiplexers, two OR gates, three shift registers, two delay modules, two carry control modules, and a MOS transistor array; wherein the MOS transistor array includes a plurality of independent MOS transistors, and these MOS transistors are divided into three groups according to the size, i.e., the width-to-length ratio, namely the small-size group, the medium-size group, and the large-size group; the positive input terminal of the synchronous comparator is connected to the basic reference voltage V REF ; the second input terminal of the first control module is connected to the first reference voltage V REF1 ; the third input terminal of the first control module is connected to the second reference voltage V REF2 ; the second input terminal of the second control module is connected to the third reference voltage V RE3 ; the third input terminal of the second control module is connected to the fourth reference voltage V REF4; The output terminal of the first control module is connected to one of the control terminals of three 1-of-3 selectors, and the output terminal of the second control module is connected to the other control terminal of the three 1-of-3 selectors; the output terminal of the synchronous comparator is connected to one of the input terminals of three shift registers and two carry control modules; the clock control terminal of the synchronous comparator, the clock control terminals of the two control modules, the third input terminal of the first 1-of-3 selector, the second input terminal of the second 1-of-3 selector, and the first input terminal of the third 1-of-3 selector are simultaneously connected to the clock signal CLK; the first input terminal and the second input terminal of the first 1-of-3 selector, the first input terminal and the third input terminal of the second 1-of-3 selector, and the second input terminal and the third input terminal of the third 1-of-3 selector are simultaneously grounded; the output terminal of the first 1-of-3 selector is connected to the other input terminal of the first shift register and the input terminal of the first delay module; the output terminal of the first delay module is connected to the other input terminal of the first carry control module; the output terminal of the second 1-of-3 selector is connected to one of the input terminals of the first OR gate; the output terminal of the first OR gate is connected to the other input terminal of the second shift register and the input terminal of the second delay module; the output terminal of the second delay module is connected to the other input terminal of the second carry control module; the output terminal of the third 1-of-3 selector is connected to one of the input terminals of the second OR gate; the output terminal of the second OR gate is connected to the other input terminal of the third shift register; the output terminal of the first shift register is connected to another input terminal of the first carry control module and the gates of all MOS transistors in the small-size group; the output terminal of the second shift register is connected to another input terminal of the second carry control module and the gates of all MOS transistors in the medium-size group; the output terminal of the third shift register is connected to the gates of all MOS transistors in the large-size group; the first output terminal of the first carry control module is connected to the other input terminal of the first OR gate, and the second output terminal of the first carry control module is connected to the reset terminal of the first shift register; the first output terminal of the second carry control module is connected to the other input terminal of the second OR gate, and the second output terminal of the second carry control module is connected to the reset terminal of the second shift register; the sources of all MOS transistors in the small-size group, medium-size group, and large-size group are connected to the high-level VDD; the negative input terminal of the synchronous comparator, the first input terminal of the first control module, the first input terminal of the second control module, and the drains of all MOS transistors in the small-size group, medium-size group, and large-size group jointly form the voltage output terminal of the digital LDO circuit.

[0006] As an improvement, the low-ripple digital LDO circuit without external capacitors further includes a feedforward minimum finite cycle oscillation maintenance module; the feedforward minimum finite cycle oscillation maintenance module includes more than one independent MOS transistor, the gates of these MOS transistors are connected to the output terminal of the synchronous comparator, the sources are connected to the high-level VDD, and the drains are connected to the voltage output terminal of the digital LDO circuit.

[0007] In the above solution, the sizes of all MOS transistors in the feed-forward minimum LCO maintenance module are the same as those of the MOS transistors in the small-size group.

[0008] As an improvement, the low-ripple digital LDO circuit without off-chip capacitors further includes a capacitor; one end of the capacitor is grounded, and the other end is connected to the voltage output terminal of the digital LDO circuit.

[0009] In the above solution, the number of bits of the first shift register is the same as the number of MOS transistors in the small-size group, the number of bits of the second shift register is the same as the number of MOS transistors in the medium-size group, and the number of bits of the third shift register is the same as the number of MOS transistors in the large-size group.

[0010] In the above solution, the sizes of all MOS transistors in the same group of the MOS transistor array are exactly the same, and the sizes of the MOS transistors in the small-size group are smaller than those in the medium-size group, and the sizes of the MOS transistors in the medium-size group are smaller than those in the large-size group.

[0011] In the above solution, the ratio of the sizes of the MOS transistors in the small-size group, the medium-size group, and the large-size group is 256:16:1.

[0012] Compared with the prior art, the present invention has the following characteristics:

[0013] 1. Using a three-loop structure, only a control clock with a frequency of dozens of MHz is required, which can greatly relieve the restrictive relationship among transient response performance, output voltage ripple, load-carrying capacity, and power consumption.

[0014] 2. Having 2 control modules and 3 multiplexers, it can control the alternating operation of the MOS transistor arrays of S, M, and L sizes, improve the transient response performance and load-carrying capacity of the digital LDO, and reduce the steady-state output voltage ripple.

[0015] 3. Having 2 carry / borrow control modules, when the shift register reaches the minimum count or the maximum count, it can perform a reset "1" or reset "0" operation on it, and send a clock edge signal to the previous-level shift register to make it perform a shift operation, realizing a smooth transition and reducing the voltage ripple caused by small changes in the output current.

[0016] 4. Having a feed-forward minimum LCO maintenance module and on-chip capacitors of several pF to replace large off-chip capacitors, so that the number of cycles of the MOS transistors turned off or on in the steady state is maintained at "1", thereby realizing a small steady-state output voltage ripple.

[0017] 5. Most of the circuits of this digital LDO are digital circuits, and only the synchronous comparator and the control module are analog circuits, which is simple and effective, convenient for process upgrading, and easy to transplant. Description of the Drawings

[0018] Figure 1 It is a system block diagram of a low-ripple digital LDO circuit without external capacitors.

[0019] Figure 2 It is a control flow block diagram of the second carry / borrow control module.

[0020] Figure 3 It is a control flow block diagram of the first carry / borrow control module. Detailed Implementation Manner

[0021] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific examples.

[0022] See Figure 1 , a low-ripple digital LDO circuit without external capacitors mainly consists of a synchronous comparator, two control modules, three multiplexers, two OR gates, three shift registers, two delay modules, two carry / borrow control modules, a MOS transistor array, a feedforward minimum LCO (Limit Cycle Oscillation) maintenance module, and a capacitor.

[0023] The synchronous comparator, its positive input terminal is connected to the basic reference voltage V REF , its negative input terminal is connected to the voltage output terminal of the digital LDO circuit, and its clock control terminal is connected to the clock signal CLK, and the comparison result is output when the clock edge arrives.

[0024] The first control module, its first input terminal is connected to the voltage output terminal of the digital LDO circuit, and its second and third input terminals are respectively connected to the first reference voltage V REF1 and the second reference voltage V REF2 , and its clock control terminal is simultaneously connected to the clock signal CLK, and it operates and outputs a result when the clock edge arrives.

[0025] The second control module, its first input terminal is connected to the voltage output terminal of the digital LDO circuit, and its second and third input terminals are respectively connected to the fourth reference voltage V REF3 and the fifth reference voltage V REF4 , and its clock control terminal is simultaneously connected to the clock signal CLK, and it operates and outputs a result when the clock edge arrives.

[0026] The first multiplexer, its first input terminal '00' and second input terminal '01' are grounded, its third input terminal '1x' is connected to the clock signal CLK, and its control terminals S1 and S0 are respectively connected to the output terminals of the first control module and the second control module.

[0027] The second three - way selector, its first input terminal '00' and the third input terminal '1x' are grounded, the second input terminal '01' is connected to the clock signal CLK, and the control terminals S1 and S0 are respectively connected to the output terminals of the first control module and the second control module.

[0028] The third three - way selector, its second input terminal '01' and the third input terminal '1x' are grounded, the first input terminal '00' is connected to the clock signal, and the control terminals S1 and S0 are respectively connected to the output terminals of the first control module and the second control module.

[0029] The first input terminal of the first OR gate is connected to the first output terminal A1 of the first carry - control module, and the second input terminal is connected to the output terminal of the second three - way selector.

[0030] The first input terminal of the second OR gate is connected to the first output terminal A2 of the second carry - control module, and the second input terminal is connected to the output terminal of the third three - way selector.

[0031] The input terminal of the first delay module is connected to the output terminal of the first three - way selector, and the output terminal of the first delay module is connected to the third input terminal of the first carry - control module.

[0032] The input terminal of the second delay module is connected to the output terminal of the first OR gate, and the output terminal of the second delay module is connected to the third input terminal of the second carry - control module.

[0033] The first shift register, its first input terminal is connected to the output terminal CMP of the synchronous comparator, the second input terminal is connected to the output terminal of the first three - way selector, the reset terminal RESET is connected to the second output terminal B1 of the first carry - control module, and it can be reset to S<31:0> = 0000_0000_0000_0000_1111_1111_1111_1111 under the corresponding control signal. The number of bits of the first shift register is the same as the number of MOS transistors in the small - size group. In this embodiment, the first shift register is a 32 - bit shift register.

[0034] The second shift register, its first input terminal is connected to the output terminal CMP of the synchronous comparator, the second input terminal is connected to the output terminal of the first OR gate, the reset terminal RESET is connected to the second output terminal B2 of the second carry - control module, and it can be reset to M<15:0> = 0000_0000_0000_0000 or 1111_1111_1111_1111 under the corresponding control signal. The number of bits of the second shift register is the same as the number of MOS transistors in the medium - size group. In this embodiment, the second shift register is a 16 - bit shift register.

[0035] A third shift register, whose first input terminal is connected to the output terminal CMP of the synchronous comparator, and whose second input terminal is connected to the output terminal of the second OR gate. The number of bits of the third shift register is the same as the number of MOS transistors in the large-size group. In this embodiment, the third shift register is a 20-bit shift register.

[0036] A first carry / borrow control module, whose first input terminal is connected to the output terminal of a 32-bit shift register, second input terminal is connected to the output terminal CMP of the synchronous comparator, and third input terminal is connected to the output terminal of the first delay module, and outputs a control signal when a clock edge arrives.

[0037] A second carry / borrow control module, whose first input terminal is connected to the output terminal of a 16-bit shift register, second input terminal is connected to the output terminal CMP of the synchronous comparator, and third input terminal is connected to the output terminal of the second delay module, and outputs a control signal when a clock edge arrives.

[0038] A MOS transistor array includes a plurality of independent MOS transistors, and these MOS transistors are divided into three groups according to the size, i.e., the width-to-length ratio, namely a small-size group (S), a medium-size group (M), and a large-size group (L). All MOS transistors in the same group have exactly the same size. The size of the MOS transistors in the small-size group is smaller than that of the MOS transistors in the medium-size group, and the size of the MOS transistors in the medium-size group is smaller than that of the MOS transistors in the large-size group. In a preferred embodiment of the present invention, the size ratio between each group is S:M:L = 256:16:1. For the shift register, outputting a "1" means turning on a MOS transistor, and outputting a "0" means turning off a MOS transistor. All shift registers in the circuit are serially input and parallelly output. The output terminal of the first shift register is connected to the gates of all MOS transistors in the small-size group; the output terminal of the second shift register is connected to the gates of all MOS transistors in the medium-size group; the output terminal of the third shift register is connected to the gates of all MOS transistors in the large-size group. The sources of all MOS transistors in the small-size group, medium-size group, and large-size group are connected to the high-level VDD. The drains of all MOS transistors in the small-size group, medium-size group, and large-size group are connected to the voltage output terminal of the digital LDO circuit.

[0039] A feed-forward minimum LCO maintenance module includes more than one (including 1) independent MOS transistor, and the gates of these MOS transistors are connected to the output terminal of the synchronous comparator, the sources are connected to the high-level VDD, and the drains are connected to the voltage output terminal of the digital LDO circuit. In a preferred embodiment of the present invention, the feed-forward minimum LCO maintenance module includes 2 MOS transistors, and the sizes of these 2 MOS transistors are the same as those of the MOS transistors in the small-size group.

[0040] A capacitor, one end of which is grounded and the other end is connected to the voltage output terminal of the digital LDO circuit.

[0041] The present invention adopts a three-ring structure and can realize the regulation of three sizes of MOS tube arrays (L, M, S) without external capacitors. The synchronous comparator is a clock-controlled dynamic comparator, which and two control modules, three shift registers, and two carry-back control modules only work at the clock edge. When the clock edge arrives, the synchronous comparator and the control module output signals, and the two control modules jointly control three three-selection selectors, so that one of the three three-selection selectors outputs a clock signal, and the shift register that receives the clock signal controls the number of MOS tubes turned on in the corresponding MOS tube array, thereby controlling the size of the output current at the output end, thereby realizing the output voltage regulation and stabilization of the digital LDO circuit. When the clock edge arrives, the carry-back control module detects whether the corresponding shift register reaches the maximum or minimum output bit number, and when the shift register output overflows, sends a carry or back operation signal to the next-level shift register, and sends a reset signal to the current-level shift register. Two control modules, three three-choice selectors and two advance and retreat control modules form a complete control loop, allowing the circuit to smoothly switch between three adjustment modes of medium speed, fastest speed and minimum ripple to cope with different load changes, so that the circuit has extremely low output voltage ripple, good transient response performance, strong load capacity and low power consumption. The present invention achieves the reduction of output voltage ripple in steady state, the enhancement of transient response performance when the load changes, and can provide a sufficiently large output current to meet the current demand of the load.

[0042] There are two situations for the output of the synchronous comparator. The first one is V out >V REF When the output is CMP = "1", the second is V out <V REF When the output CMP = "0", ideally, the steady-state V out =V REF In reality, this situation does not exist.

[0043] The first control module and the second control module output a voltage V according to the digital LDO out In the interval, its output S1 and S0 have three output combinations (S1S0) "00", "01" and "11", corresponding to the fastest speed regulation mode, medium speed regulation mode, and minimum ripple regulation mode respectively. Each time the three three-in-one selectors receive a combination of S1 and S0, one of the three-in-one selectors will output a clock signal, and the other two selectors will output "0", thereby realizing the operation mode of one ring working and two rings holding (maintaining the output after the previous clock signal is input) of the three-ring structure. For the shift register in the working loop, when the clock edge arrives, if the synchronous comparator output result CMP = "1" received at its first input end, the overall shift is moved one bit to the highest bit and "1" is counted in the lowest bit, that is, V out >VREF Turn off a MOS transistor when [condition]; if the output result CMP of the synchronous comparator received at the first input terminal is "0", then shift the whole one bit to the lowest bit and enter "0" at the highest bit, that is, V REF >V out Turn on a MOS transistor when [condition]. In addition, when the current shift register outputs all "1"s or all "0"s and it is necessary to continue writing "1" or "0", the carry / borrow control module will be triggered to issue reset and carry signals.

[0044] When the output voltage in the current cycle is in the voltage range of the fastest speed regulation mode (i.e., S1 = 0, S0 = 0), after several cycles of regulation, the output voltage will enter the voltage range of the medium speed regulation mode (i.e., S1 = 0, S0 = 1), then after several more cycles of regulation, it will enter the voltage range of the minimum ripple regulation mode, and after several cycles of regulation, the system will enter a steady state, that is, a cyclic working state where one MOS transistor in the array S is turned on in one cycle and turned off in the next cycle. At this time, V out will fluctuate very slightly above and below V REF If the output voltage in the current cycle is in the voltage range of the medium speed regulation mode (i.e., S1 = 0, S0 = 1), after several cycles of regulation, the output voltage will enter the voltage range of the minimum ripple regulation mode (i.e., S1 = 1, S0 = 1), and after several cycles of regulation, the system will enter a steady state. If the output voltage in the current cycle is in the voltage range of the minimum ripple regulation mode (i.e., S1 = 1, S0 = 1), then the system will enter a steady state after several cycles of regulation.

[0045] In the voltage range where the output voltage is in the minimum ripple regulation mode (S1 = 1, S0 = 1) in the current cycle, if the output of the 32-bit shift register is S<31:0> = 1111_1111_1111_1111_1111_1111_1111_1111 and CMP = "1", then a high-level signal is output at the first output terminal A1 of the first carry control module, and "1" is output to the RESET terminal of the 32-bit shift register at the second output terminal B1; the 16-bit shift register receives the high-level signal through the first OR gate, and its output signal is shifted one bit to the highest bit as a whole and "1" is written to the lowest bit, turning off the MOS transistors of one M array; the 32-bit shift register is reset to S<31:0> = 0000_0000_0000_0000_1111_1111_1111_1111, and then the output of the 32-bit shift register is shifted one bit to the highest bit as a whole again, and the operation of writing "1" to the lowest bit is performed, and the output becomes S<31:0> = 0000_0000_0000_0001_1111_1111_1111_1111. If the output of the 32-bit shift register is S<31:0> = 0000_0000_0000_0000_0000_0000_0000_0000 and CMP = "0", then a high-level signal is output at the first output terminal A1 of the first carry control module, and "1" is output to the RESET terminal of the 32-bit shift register at the second output terminal B1; the 16-bit shift register receives the high-level signal through the first OR gate, and its output signal is shifted one bit to the lowest bit as a whole, and "0" is written to the highest bit, turning on the MOS transistors of one M array; the 32-bit shift register is reset to S<31:0> = 0000_0000_0000_0000_1111_1111_1111_1111, and then the output of the 32-bit shift register is shifted one bit to the lowest bit as a whole again, and the operation of writing "0" to the highest bit is performed, and the output becomes S<31:0> = 0000_0000_0000_0000_0111_1111_1111_1111.

[0046] In the current cycle, the output voltage is in the voltage range of the medium-speed regulation mode (S1 = 0, S0 = 1). If the output of the 16-bit shift register is M<15:0> = 1111_1111_1111_1111 and CMP = "1", a high-level signal is output from the first output terminal A2 of the second carry control module, and "1" is output from the second output terminal B2 to the RESET terminal of the 16-bit shift register; the 20-bit shift register receives the high-level signal through the second OR gate, its output is shifted one bit to the highest bit as a whole and "1" is written to the lowest bit, and the MOS transistors of one L array are turned off; the 16-bit shift register is reset to M<15:0> = 0000_0000_0000_0000, and then the output of the 16-bit shift register is shifted one bit to the highest bit as a whole again, and the operation of writing "1" to the lowest bit is performed, and the output becomes M<15:0> = 0000_0000_0000_0001. If the output of the 16-bit shift register is M<15:0> = 0000_0000_0000_0000 and CMP = "0", a high-level signal is output from the first output terminal A2 of the second carry control module, and "1" is output from the second output terminal B2 to the RESET terminal of the 16-bit shift register. The 20-bit shift register receives the high-level signal through the second OR gate, its output is shifted one bit to the lowest bit as a whole, and "0" is written to the highest bit, and the MOS transistors of one L array are turned on. The 16-bit shift register is reset to M<15:0> = 1111_1111_1111_1111, and then the output of the 16-bit shift register is shifted one bit to the lowest bit as a whole again, and the operation of writing "0" to the highest bit is performed, and the output becomes M<15:0> = 0111_1111_1111_1111.

[0047] Table 1 Truth table of the control module Control result

[0048] S1 S0 32-bit shift register 16-bit shift register 20-bit shift register 0 0 Hold Hold Run 0 1 Hold Run Hold 1 1 Run Maintain the status quo Hold

[0049] Adopt the logic of the truth table of the control module shown in Table 1 to achieve smooth switching of three different loops in the digital LDO circuit to cope with different load change situations. The load changes are mainly divided into three types, corresponding to the S, M, and L3 MOS transistor arrays. In this circuit, the first control module and the second control module operate simultaneously to output S1 and S0, generating the following three control situations:

[0050] The first situation, that is, V out <V REF4 <V REF2 Or V REF1 <V REF3 <V out, the outputs of the two control modules are S1 = 0 and S0 = 0, and the whole system is in the fastest adjustment mode. It will increase or decrease the number of turned-on MOS transistors in the MOS transistor array L to quickly restore the system to the minimum ripple adjustment mode of S1 = 1 and S0 = 1. Turning on one MOS transistor in the array L is equivalent to turning on 16 MOS transistors in the array M.

[0051] The second case, i.e., V REF4 < V out < V REF2 or V REF1 < V out < V REF3 , the outputs of the two control modules are S1 = 0 and S0 = 1, and the whole system is in the medium-speed adjustment mode. It will increase or decrease the number of turned-on MOS transistors in the MOS transistor array M. After a certain period of adjustment, the system will return to the minimum ripple adjustment mode of S1 = 1 and S0 = 1. Turning on one MOS transistor in the array M is equivalent to turning on 16 MOS transistors in the array S. If all the MOS transistors in the MOS transistor array M have been turned on, but still need to continue writing "0", when the second carry / borrow control module detects this situation, it will control the 16-bit shift register to reset to M<15:0> = 1111_1111_1111_1111 and send a signal to the clock signal terminal of the 20-bit shift register through the second OR gate, thereby turning on one MOS transistor in the array L; if all the MOS transistors in the MOS transistor array M have been turned off, but still need to continue writing "1", when the second carry / borrow control module detects this situation, it will control the 16-bit shift register to reset to M<15:0> = 0000_0000_0000_0000 and output a signal to the clock signal terminal of the 20-bit shift register through the second OR gate, thereby turning off one MOS transistor in the array L. The working process of the second carry / borrow control module is as Figure 2 shown.

[0052] The third case, i.e., V REF4 < V REF2 < V out < V REF1 < V REF3, the outputs of the two control modules are S1 = 1 and S0 = 1. The entire system is in the minimum ripple regulation mode, which will increase or decrease the number of turned-on MOSFETs in the MOSFET array S. When in the steady state and when the output changes very slowly, the entire circuit operates in this mode. If all the MOSFETs in the MOSFET array S have been turned on, but still need to continue writing "0", when the first carry / borrow control module detects this situation, it will control the 32-bit shift register to reset to S<31:0> = 0000_0000_0000_0000_1111_1111_1111_1111, and send a signal to the clock signal terminal of the 16-bit shift register through the first OR gate, thereby turning off one MOSFET in the array M. If all the MOSFETs in the MOSFET array S have been turned off, but still need to continue writing "1", when the first carry / borrow control module detects this situation, it will control the 32-bit shift register to reset to S<31:0> = 0000_0000_0000_0000_1111_1111_1111_1111, and send a signal to the clock signal terminal of the 16-bit shift register through the first OR gate, thereby turning on one MOSFET in the array M. The working process of the first carry / borrow control module is as Figure 3 shown.

[0053] According to the proportional relationship of the MOSFET array in this embodiment, assuming that at V out = V REF , the minimum current that the digital LDO can provide is I out , then the maximum current that can be provided is 5408 times that of I out (i.e., I out * 32 + I out * 16 * 16 + I out * 16 * 16 * 20 = 5408 * I out ). If the current required by the load is 60 times that of I out , at this time, the output current of the digital LDO is 100 times that of I out . The excess current will cause V out to rise, that is, the output voltage V out must be greater than V REF . The synchronous comparator outputs CMP = "1"; the output voltage should be located in the range of V REF1 < V out < V REF3 . The outputs of the two control modules are S1 = 0 and S0 = 1. At this time, the control mode of the digital LDO should be the medium-speed regulation mode; the 16-bit shift register is in the operating state, and one MOSFET in the MOSFET array M is turned off when the clock edge arrives, and V out will decrease; after X clock edges, the output voltage V out is adjusted to V REF4 < VREF2 <Vout<V REF1 <V REF3 Interval, the outputs of the two control modules are S1 = 1 and S0 = 1. At this time, the control mode of the digital LDO should be the minimum ripple regulation mode, and the 32-bit shift register is in the operating state. Then, after experiencing N clock edges, the digital LDO enters the steady state mode. Due to the function of the feedforward minimum LCO maintenance module, in the steady state, only one MOS transistor in the MOS transistor array S of the digital LDO cycles on and off. Since the MOS transistors in the MOS transistor array S are extremely small in size, the on and off of the MOS transistors will only cause a slight change in the output current. Therefore, the change in the output voltage is also very weak, thus realizing the reduction of the output voltage ripple.

[0054] The feedforward minimum LCO maintenance module responds to the output result of the synchronous comparator in advance, and cooperates with a few pF capacitor at the output end, so that the number of cycles of turning on and off the MOS transistors in the S array in the steady state is only 1.

[0055] The present invention constitutes a three-loop structure of a capacitorless digital LDO through a control module, a three-way selector, a carry control module, and MOS transistor arrays of three sizes S, M, and L, and introduces a feedforward minimum LCO maintenance module. This digital LDO has excellent load-carrying capacity and low output voltage ripple. It can achieve fast load regulation at a clock frequency of dozens of MHz, greatly alleviating the restrictive relationship between transient response performance and power consumption. In addition, due to the advantage of the three-loop structure that can achieve multiple regulation modes, and the function of the feedforward minimum LCO maintenance module to reduce the number of MOS transistors operating in cycles in the steady state, the circuit of this patent only requires a few pF of on-chip capacitors, thus realizing a low-ripple capacitorless digital LDO circuit with a three-loop fast regulation structure.

[0056] It should be noted that although the embodiments described above of the present invention are illustrative, this is not a limitation of the present invention. Therefore, the present invention is not limited to the above specific embodiments. Without departing from the principle of the present invention, any other embodiments obtained by those skilled in the art under the inspiration of the present invention are deemed to be within the protection scope of the present invention.

Claims

1. A low-ripple digital LDO circuit without external capacitors, characterized by being composed of It is composed of a synchronous comparator, a feed-forward minimum finite period oscillation maintenance module, two control modules, three multiplexers, two OR gates, three shift registers, two delay modules, two carry control modules, and a MOS transistor array. The MOS transistor array includes a plurality of independent MOS transistors, which are divided into three groups according to their sizes, i.e., the width-to-length ratio, namely the small-size group, the medium-size group, and the large-size group. The ratio of the sizes of the MOS transistors in the small-size group, the medium-size group, and the large-size group is 256:16:

1. The positive input terminal of the synchronous comparator is connected to the basic reference voltage V REF ; the second input terminal of the first control module is connected to the first reference voltage V REF1 , and the third input terminal of the first control module is connected to the second reference voltage V REF2 ; the second input terminal of the second control module is connected to the third reference voltage V RE3 , and the third input terminal of the second control module is connected to the fourth reference voltage V REF4 ; The feed-forward minimum finite period oscillation maintenance module includes more than one independent MOS transistor. The gates of these MOS transistors are connected to the output terminal of the synchronous comparator, the sources are connected to the high-level VDD, and the drains are connected to the voltage output terminal of the digital LDO circuit. The output terminal of the first control module is connected to one of the control terminals of the three multiplexers, and the output terminal of the second control module is connected to the other control terminal of the three multiplexers. The output terminal of the synchronous comparator is connected to one of the input terminals of the three shift registers and the two carry control modules. The clock control terminal of the synchronous comparator, the clock control terminals of the two control modules, the third input terminal of the first multiplexer, the second input terminal of the second multiplexer, and the first input terminal of the third multiplexer are simultaneously connected to the clock signal CLK. The first input terminal and the second input terminal of the first multiplexer, the first input terminal and the third input terminal of the second multiplexer, and the second input terminal and the third input terminal of the third multiplexer are simultaneously grounded. The output terminal of the first multiplexer is connected to the other input terminal of the first shift register and the input terminal of the first delay module. The output terminal of the first delay module is connected to the other input terminal of the first carry control module. The output terminal of the second multiplexer is connected to one of the input terminals of the first OR gate. The output terminal of the first OR gate is connected to the other input terminal of the second shift register and the input terminal of the second delay module. The output terminal of the second delay module is connected to the other input terminal of the second carry control module. The output terminal of the third multiplexer is connected to one of the input terminals of the second OR gate. The output terminal of the second OR gate is connected to the other input terminal of the third shift register. The output terminal of the first shift register is connected to another input terminal of the first carry control module and the gates of all the MOS transistors in the small-size group. The output terminal of the second shift register is connected to another input terminal of the second carry control module and the gates of all the MOS transistors in the medium-size group. The output terminal of the third shift register is connected to the gates of all the MOS transistors in the large-size group. The first output terminal of the first carry control module is connected to the other input terminal of the first OR gate, and the second output terminal of the first carry control module is connected to the reset terminal of the first shift register. The first output terminal of the second carry control module is connected to the other input terminal of the second OR gate, and the second output terminal of the second carry control module is connected to the reset terminal of the second shift register. The sources of all MOS transistors in the small-size group, medium-size group, and large-size group are connected to the high-level VDD; the negative input terminal of the synchronous comparator, the first input terminal of the first control module, the first input terminal of the second control module, and the drains of all MOS transistors in the small-size group, medium-size group, and large-size group together form the voltage output terminal of the digital LDO circuit.

2. The low-ripple capacitorless digital LDO circuit according to claim 1, wherein The sizes of all MOS transistors in the feedforward minimum LCO maintenance module are the same as those of the MOS transistors in the small-size group.

3. The digital LDO circuit with low ripple and no external capacitor according to claim 1, characterized in that, It further includes a capacitor; one end of the capacitor is grounded, and the other end is connected to the voltage output terminal of the digital LDO circuit.

4. The low-ripple capacitorless digital LDO circuit according to claim 1, wherein The number of bits of the first shift register is the same as the number of MOS transistors in the small-size group, the number of bits of the second shift register is the same as the number of MOS transistors in the medium-size group, and the number of bits of the third shift register is the same as the number of MOS transistors in the large-size group.

5. The low-ripple capacitorless digital LDO circuit according to claim 1, wherein All MOS transistors in the same group of the MOS transistor array have exactly the same size, and the size of the MOS transistors in the small-size group is smaller than that of the MOS transistors in the medium-size group, and the size of the MOS transistors in the medium-size group is smaller than that of the MOS transistors in the large-size group.

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