Method and simulation system for analyzing baseband performance

Abstract

Provided are a method and a simulation system for analyzing baseband performance. The method comprises: inputting a test case to a simulation architecture of a baseband chip to obtain test data, wherein the simulation architecture is an architecture based on a transaction level model, and the simulation architecture comprises at least one module modeled based on a System C language; wherein the test data comprises maximum throughput of the baseband chip and air interface downlink configuration parameters; and analyzing performance of the baseband chip according to the test data. The method for analyzing baseband performance provided in the application can realize fast and accurate performance evaluation of the baseband chip, and shorten the development cycle of the baseband chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of baseband performance analysis, and more particularly, to a method and simulation system for analyzing baseband performance. BACKGROUND

[0002] Most baseband chip designs are based on previously verified chip architectures, and only special modules are optimized. That is, the existing register transfer level (RTL) model is directly used, the process of describing by hardware language is saved, the development time of the chip is shortened, and the quality of the chip is ensured. However, for a baseband chip with a new architecture, the existing RTL model is not available. Rebuilding the RTL level model has the problems of long modeling cycle and complex process, and may not meet the requirements of the development cycle of the baseband chip. Therefore, a method for analyzing the performance of a baseband chip is needed, which can quickly and accurately analyze and evaluate the performance of a new baseband chip architecture, thereby shortening the development cycle of the baseband chip. SUMMARY

[0003] The present application provides a method and simulation system for analyzing baseband performance, which can quickly and accurately analyze and evaluate the performance of a baseband chip.

[0004] In a first aspect, a method for analyzing baseband performance is provided, comprising: inputting a test case to a simulation architecture of a baseband chip to obtain test data, wherein the simulation architecture is an architecture based on a transaction level model, and the simulation architecture comprises at least one module modeled based on a System C language; wherein the test data comprises a maximum throughput of the baseband chip and an air interface downlink configuration parameter; and analyzing the performance of the baseband chip according to the test data.

[0005] Optionally, the simulation architecture of the baseband chip comprises a physical layer processing module, a data plane moving module, and an external storage module, the physical layer module is configured to perform physical layer operations, and the data plane moving module is configured to move baseband data output by the physical layer module to the external storage module.

[0006] Optionally, the simulation architecture of the baseband chip further comprises a CPU module, the CPU module, the physical layer processing module, the data plane moving module, and the external storage module are connected through an on-chip network, and the data plane moving module moves the baseband data to the external storage module in a DMA manner.

[0007] Optionally, the CPU module and the data plane moving module are provided with a module for tracking and debugging the traffic of the on-chip network.

[0008] Optionally, as an implementation manner, the physical layer processing module comprises one or more of the following modules: a DSP core, a microprocessor core, on-chip memory, a HARQ module, and a task driving module, wherein the task driving module communicates with the NoC to perform physical layer related tasks through the NoC.

[0009] In a second aspect, an emulation system is provided, wherein an emulation architecture of a baseband chip is running on the emulation system, the emulation architecture is a transaction level model based architecture, and the emulation architecture comprises at least one module modeled based on a System C language, and the emulation system comprises: a memory for storing data; and a processor for executing the data stored in the memory to perform the following operation: inputting a test case to the emulation architecture of the baseband chip to obtain test data; wherein the test data comprises a maximum throughput of the baseband chip and air interface downlink configuration parameters; and analyzing performance of the baseband chip according to the test data.

[0010] Optionally, the emulation architecture of the baseband chip comprises a physical layer processing module, a data plane moving module, and an external storage module, wherein the physical layer processing module is configured to perform physical layer operations, and the data plane moving module is configured to move baseband data output by the physical layer processing module to the external storage module.

[0011] Optionally, the emulation architecture of the baseband chip further comprises a CPU module, and the CPU module, the physical layer processing module, the data plane moving module, and the external storage module are connected through a NoC, and the data plane moving module moves the baseband data to the external storage module in a DMA manner.

[0012] Optionally, the CPU module and the data plane moving module are provided with a module for tracking and debugging traffic of the NoC.

[0013] Optionally, the physical layer processing module comprises one or more of the following modules: a DSP core, a microprocessor core, on-chip memory, a HARQ module, and a task driving module, wherein the task driving module communicates with the NoC to perform physical layer related tasks through the NoC.

[0014] In a third aspect, a computer readable storage medium is provided, wherein executable codes are stored on the computer readable storage medium, and when the executable codes are executed, the method according to the first aspect can be implemented.

[0015] In a fourth aspect, a computer program product is provided, wherein executable codes are stored in the computer program product, and when the executable codes are executed, the method according to the first aspect can be implemented.

[0016] The method for analyzing baseband chip performance proposed in this application uses a transaction-level model to build a simulation architecture for the baseband chip, and completes the modeling of each module in the simulation architecture based on the System C language. Compared with traditional simulation architectures based on RTL-level models, the simulation architecture involved in this application has the advantages of faster simulation speed and more accurate information acquisition, thereby achieving rapid and accurate performance analysis of the baseband chip. Attached Figure Description

[0017] Figure 1 This is a structural example diagram of a baseband chip provided in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of a method for analyzing baseband performance provided in an embodiment of this application.

[0019] Figure 3 An example diagram of a simulation architecture model of a baseband chip provided in an embodiment of this application.

[0020] Figure 4 for Figure 3 Example diagram of LPDDR read / write model.

[0021] Figure 5 for Figure 3 Example diagram of the model for the flow tracking module.

[0022] Figure 6 An example diagram of the implementation components of a simulation architecture for a baseband chip provided in this application embodiment.

[0023] Figure 7 This application provides an example diagram illustrating the workflow of baseband chip performance analysis.

[0024] Figure 8 This is a schematic diagram of the structure of a simulation system provided in an embodiment of this application. Detailed Implementation

[0025] To facilitate understanding, some related concepts involved in the embodiments of this application will be introduced first.

[0026] A baseband chip is a highly complex system-on-a-chip (SoC). Currently, most baseband chips are fundamentally structured around a microprocessor unit (MPU) and a digital signal processor (DSP). The MPU is the control center of the entire chip, running a real-time embedded operating system. The DSP subsystem is the core of baseband processing, containing numerous hardware accelerators and dedicated baseband processing modules to perform all physical layer functions.

[0027] For example, a baseband chip in a smart phone is a complex SOC chip, which has multiple functions, and the normal work of each function is configured and coordinated by a microprocessor. That is, the microprocessor is the center, and each peripheral function module around the microprocessor is controlled and configured through a dedicated bus of the microprocessor. These function modules can be, for example, global system for mobile communications (GSM), Wi-Fi (i.e., wireless network system), Global Positioning System (GSP), Bluetooth, DSP, and memory, etc. Each function module has independent memory and address space, and the functions are independent of each other.

[0028] An intellectual property (IP) core is a basic unit of an SOC. IP is a functional model that meets specific specifications and requirements and can be repeatedly reused in design. Figure 1 An example of a structure of an SOC provided for an embodiment of the present application is shown in FIG. 1. Figure 1 As shown, an SOC can include many modules or IPs, such as a processor, a memory, an interface, etc. These IPs are connected to each other through a bus to exchange data and implement communication control functions, forming a complete computer system.

[0029] With the rapid development of SOC design technology, transaction level modeling (TLM) has been widely applied in system modeling, simulation verification, and collaborative design in the field of SOC. A transaction refers to the exchange process of data or events between two units in a system model, such as the data interaction between two IPs. A transaction can combine low-level information transmission into higher-level transmission, simplifying system interaction behavior, and can also classify information involved in transmission as a whole without involving specific signals.

[0030] Currently, the market competition of electronic products is becoming increasingly fierce, and people's demand for products is urgent. Designers need to improve the development efficiency of products as much as possible and complete the design of chips in the shortest possible time. For most chips, designers usually adopt IP reuse technology, that is, by pre-setting some verified modules in the system, these modules can be reused. As an example, these IP modules are generally implemented based on RTL level modeling. In this way, designers do not need to design from scratch, and then perform system integration and verification mode, and can directly use pre-designed and verified integrated circuit modules, i.e., IP cores, to achieve chip design. In this way, the development efficiency of chips is improved, the development cycle is shortened, and the quality of chips is guaranteed.

[0031] In other words, in SOC design, for a mature chip, the designer will only optimize the special module based on the previously verified chip. That is, the existing RTL model can be directly used, thereby saving the process of RTL level modeling using hardware language. RTL level modeling is a very long process in time period, which occupies a large part of the SOC development period, and therefore, the method can greatly shorten the development period of the SOC. However, for a brand new architecture of baseband chip, there is no directly usable RTL model, and it is necessary to re-write the RTL code for modeling and simulation.

[0032] On the other hand, in the field of baseband chips, how to design a baseband chip with powerful function, superior performance and high flexibility has always been a great challenge for baseband chip design. The baseband chip generally uses a customized application specific integrated circuit (ASIP) to realize it, which integrates multiple circuit modules together, and different circuits realize different communication functions. For the fixed circuit module function, the chip resources and running speed can be optimized when designing the ASIP, to realize superior performance. However, the customized chip lacks flexibility, and once new functions need to be added, it needs to be redesigned, which consumes a lot of manpower and material resources. In addition, with the development of wireless communication technology, new communication standards are constantly introduced and the compatibility of standards raises higher and higher requirements for the flexibility and scalability of the baseband chip.

[0033] The architecture of the baseband chip is increasingly complex, and the designer faces many new baseband chip architectures. In order to meet the design goals of the chip's time to market and performance (such as can include power, performance, area), it is difficult for the designer to accurately design and evaluate a brand new baseband architecture according to experience. At the beginning of the design, there are multiple alternative solutions, and once an inappropriate system architecture and on-chip resources are selected, the designed chip will not meet the expected performance requirements. Therefore, at the initial stage of chip design, a reliable and perfect simulation platform is needed to evaluate the performance of the baseband chip architecture, so as to ensure that the selected chip architecture and chip resource configuration meet the functional and performance requirements. In addition, the performance evaluation of the baseband chip also lays a solid foundation for the later implementation of the software / hardware of the baseband chip.

[0034] There are various simulations in the baseband chip design cycle. As an example, modeling and simulation of early stage baseband algorithms, which can achieve evaluation of communication link state and parameters. However, the simulation is only for communication link and algorithm, and cannot evaluate the baseband design scheme. As another example, the baseband chip performance can also be simulated by using a field programmable gate array (FPGA) system, so as to generate accurate timing information and perform evaluation. However, when using the simulation method, the chip structure design has been determined, and once the performance does not meet the requirements, the chip design modification will cause cost increase and design cycle extension. Obviously, relying on the existing model or simulation means in the baseband chip design process cannot achieve the purpose of quickly evaluating the baseband chip architecture. Therefore, an independent simulation platform needs to be established, which can perform performance analysis and evaluation on the chip architecture in the early design stage, so as to reduce the design cost and shorten the design cycle.

[0035] In view of the above problems, the present application provides a new and effective method for analyzing the performance of a baseband chip, which can be realized by a simulation architecture of the baseband chip, the simulation architecture is based on a transaction level model architecture with a higher abstraction level, and each module in the simulation architecture is modeled by a System C language, so as to realize fast and accurate performance analysis of the baseband chip.

[0036] The performance analysis method provided in the present application can perform performance analysis on the system architecture at the beginning of the design of the baseband chip, form a reliable model, adjust and optimize the model through behavior calibration between the model and the chip, and improve the reliability of the model. In this way, when designing the next generation chip, only the model needs to be optimized to realize performance analysis of a baseband chip with a new architecture.

[0037] Meanwhile, the present application also provides a simulation system for a baseband chip, which can simulate, evaluate and optimize the overall architecture of the baseband chip in the early design stage of the baseband chip, and has a strong reference significance for the design of the baseband chip by using the simulation system to perform architecture modeling and design exploration of the baseband chip. The simulation system provided in the present application can define the system architecture from zero basis, simplify the complexity of the performance analysis model, reduce the evaluation workload, and also can obtain sufficient information with high precision to select a better solution of the baseband chip.

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments.

[0039] Figure 2A schematic diagram of a method for analyzing baseband performance is provided in the embodiments of the present application, which is described below in combination with Figure 2 The method for analyzing baseband chip performance provided in the present application is described in detail.

[0040] In step S210, a test case is input to a simulation architecture of the baseband chip to obtain test data, wherein the simulation architecture is an architecture based on a transaction level model (TLM), and the simulation architecture includes at least one module modeled based on a System C language; and the test data includes maximum throughput of the baseband chip and air interface downlink configuration parameters.

[0041] The method for analyzing baseband chip performance in the embodiments can be implemented through a simulation architecture of the baseband chip. The simulation architecture of the baseband chip is an architecture based on a TLM model with a higher abstraction level compared to a conventional simulation architecture. The designer can divide the simulation architecture into multiple modules according to the requirements of the baseband chip, wherein each module is implemented based on a System C language modeling, for example, a standard-compliant System C TLM 2.0, which is independent of a supplier, has characteristics such as free license, complete autonomous development, maintenance and possession, etc. The TLM2.0 specification specifies the specifications that must be followed when communicating between various components in a system, and improves the uniformity of interfaces between modules.

[0042] Optionally, the performance evaluation of the baseband chip can include evaluation of throughput and air interface performance of the baseband chip, and therefore, the test data can correspondingly include maximum throughput of the baseband chip and air interface downlink configuration parameters. As an example, the test data can include, for example, maximum throughput of downlink sub6GHz, configured as 3 continuous carriers, and downlink rate of 7.0 Gbps. The test data can further include performance data of the baseband chip in other working conditions.

[0043] As described above, for a brand-new baseband architecture, the existing RTL model is not available. If the modeling and simulation are performed again using the RTL level model, since the abstraction level of the RTL level modeling is low, the implementation details of the underlying layer need to be clear, the modeling speed is slow, and for a baseband chip with a limited time to market, the development cycle will be seriously affected. Therefore, it is necessary to improve the abstraction level to improve the modeling and simulation speed.

[0044] The TLM model is an abstraction of the hardware components of a system at a higher level. The TLM level modeling separates the operation function and the communication function, captures at a high level and communicates through function calls rather than specific signals, and reduces the processing of events and information. Compared with the RTL model, the TLM model reduces a lot of detailed information, such as a single clock cycle, greatly reduces the processing frequency of information and events, and requires less code, so the modeling and simulation speed is faster, and different types of sufficient design accuracy can be provided according to the specific needs of system design. As an example, the simulation speed of the transaction level model is generally 10 to 100 times faster than that of the RTL level model. Obviously, the TLM model can greatly improve the simulation speed of the system. Therefore, compared with the RTL model, the TLM can realize faster system modeling and simulation, and shorten the design and development cycle of the baseband chip.

[0045] System C can quickly realize the establishment of the transaction level model, and simplify the development of the TLM model. Optionally, some modules in the simulation architecture of the baseband chip can be modeled by using an existing modeling tool, so as to further improve the modeling speed and accuracy. For example, a FlexNoC topology can be generated from FlexNoC Explorer, so as to realize cycle-accurate modeling based on the NTTP protocol. FlexNoc is a transaction level modeling based on SystemC, and the simulation speed is fast. As an example, the simulation time of FlexNoc for a typical test case is several tens of minutes. The simulation speed of the baseband chip can be greatly improved, and the development cycle of the baseband chip is shortened.

[0046] Optionally, the simulation architecture has a real-time requirement, and needs to control the real-time performance of the baseband architecture. The simulation architecture involved in the embodiment can completely autonomously establish a parameter file and configure an accuracy target. The size of the accuracy target will affect the performance of the simulation architecture. If the accuracy is configured too high, the cost will be higher; if the accuracy is configured too small, the reliability of the model will be lower. For example, the accuracy target of the simulation architecture can be set to be greater than 85%.

[0047] In step S220, the performance of the baseband chip is analyzed according to the test data.

[0048] As described above, after the simulation architecture is created, the simulation architecture can realize performance analysis of the baseband chip. Specifically, a test case is input into the simulation architecture, and the simulation architecture generates test data. For example, the final test result can be output as a log file, which can be viewed in an interface. The simulation architecture in the embodiment can directly generate a visual and readable analysis report. For example, a log file information of throughput, delay, back pressure statistics, etc. can be obtained through a corresponding button, so as to facilitate designers to intuitively read and analyze.

[0049] The designer analyzes the performance test data of the baseband chip, and compares it with the system performance index to determine whether it meets the expectation and gives a performance feedback report. If there is a gap between the actual test performance and the system performance index, the corresponding module in the simulation architecture needs to be modified and optimized according to the test results. Through the iterative process of repeated modification and test, until the system performance can meet the expected standard, meet various indicators, and achieve a better result.

[0050] Optionally, the model in the simulation architecture in the embodiment can be verified in advance. For example, FlexNoC can be used for NOC depth detection, thereby further improving the simulation time; the detection results of the existing model can also be compared with the simulation results of the model in the embodiment to optimize the model in the embodiment and improve the accuracy of the simulation architecture.

[0051] Figure 3 An example diagram of the model of the simulation architecture of the baseband chip provided in the embodiment of the present application is shown in the following Figure 3 The simulation architecture of the baseband chip is introduced.

[0052] As shown in Figure 3 The simulation architecture 300 of the baseband chip can include five modules, namely a physical layer module 310, a data plane migration module 320, an external storage module 330, a CPU module 340 and a network-on-chip (NOC) 350. The operations performed by each module are described below with reference to Figure 3

[0053] As an example, the physical layer module 310, the data plane migration module 320, the external storage module 330 and the CPU module 340 are connected through the network-on-chip 350 to interact with data.

[0054] The physical layer module 310 is used to perform physical layer operations, such as decoding, demodulation and other operations on data. After receiving the data, the physical layer module 310 performs demodulation and other processing on the data to generate a binary data signal form that can be recognized by a computer. Then, the physical layer module 310 sends the processed data to the network-on-chip 510, which writes the data to the external storage module 330 for storage according to the performance requirements.

[0055] ​External storage module 330, for example, can be LPDDR. As an example, the LPDDR model can be provided by a third party, featuring a first-in-first-out (FIFO) architecture, command placement algorithm, JEDEC-compliant LPDDR latency, and the ability to calibrate to 15% accuracy in selected interaction modes. Furthermore, this LPDDR model can be configured based on System C.

[0056] As an example, the physical layer processing module 310 may include one or more of the following modules: on-chip memory 311, DSP core 312, microprocessor core 313, HARQ module 314, and task-driven module 315.

[0057] Specifically, the DSP core 312, for example, can be a custom application-specific instruction set processor (ASIP) DSP core, which is the core module of the physical layer module 315. A good balance can be achieved by balancing design constraints such as speed, power consumption, cost, and flexibility.

[0058] The on-chip memory 311, such as static random-access memory (SRAM), is a key focus of the simulation architecture 300 optimization due to its relatively high cost. Settings such as the size and location of the SRAM can affect system latency. Therefore, the SRAM requires configurable overhead to control its latency and throughput.

[0059] As one embodiment, the task-driven module 315 communicates with the on-chip network 350 to execute tasks related to the physical layer module 310 via the on-chip network 350.

[0060] Specifically, the task-driven module 315 sends the decomposed tasks to the on-chip network 350 and informs which module will handle which task. The physical layer module 310 stores these data in the external storage module 330. When the physical layer module 310 writes data to the external storage module 330, the writing speed is determined by the priority, throughput, latency of the on-chip network module 350, and the bandwidth between it and the external storage module 330. Figure 4 This is an example diagram of an LPDDR read / write model. Figure 4As shown, after the on-chip network 350 sends a request to the LPDDR, the LPDDR will respond to the request of the on-chip network 350, including the latency information. If the system requires the physical layer module 310 to complete the writing / reading of data in the LPDDR within a specified time granularity, and the processing time of the data writing / reading exceeds the system specified time granularity, it indicates that the baseband chip architecture is not optimal and needs to be modified and optimized.

[0061] As an embodiment, the data plane moving module 320 is configured to move the baseband data output by the physical layer module 310 to the external storage module. Optionally, the data plane moving module 320 moves the baseband data to the external storage module 330 in a direct memory access (DMA) manner, for example, the data plane module 320 can include a DMA module 322. Optionally, the physical layer module 310 only needs to be responsible for data grooming, and the data moving is responsible by the data plane module 320.

[0062] Specifically, when the data volume of the physical layer module 310 is large, the writing of data cannot be completed according to the system specified time, at which time the simulation architecture 300 needs to be optimized. For example, the priority order of data writing between modules can be adjusted by adjusting the priority of the external storage module 330, and the data is read / written to the external storage module 330 in time. The data plane module 320 is designed for optimization, and the data plane module 320 is mainly responsible for the data moving operation of the data processed by the physical layer module 310. As an example, the data moving can be realized by DMA, and the DMA module 322 can realize the interaction of different speed hardware devices without relying on the CPU module 340 to control the transmission, providing a direct data transmission channel, greatly improving the efficiency of the CPU module 340.

[0063] As another embodiment, the CPU module 340 and the data plane moving module 320 are provided with a module for tracking and debugging the traffic of the on-chip network 350.

[0064] As described above, the data moving module 320 needs to move the data processed by the physical layer module 310 to the external storage module 330, and because the CPU module 340 and the data plane moving module 320 have not high requirements on system latency, a traffic tracking module 321 for tracking and debugging the traffic of the on-chip network 350 can be set. As an example, the traffic tracking module 321 is designed in the CPU module 340 and the data plane module 320 which have not high requirements on latency, and the traffic tracking module 321 is not required to be set in the physical layer module 310 which has high requirements on real-time performance, and the module with high real-time performance is set in the physical layer module 310.

[0065] The traffic tracking module 321 can mark the task driving module 315 performing the task process, for example, can mark the time stamp in the task process. Figure 5 An example diagram of the model of the traffic tracking module 321. The traffic tracking module 321 performs fine-grained control on the traffic of the network on a chip 350, for example, can mark the way of transmitting the data stream to track the flow direction of the data stream. The information between the traffic tracking module 321 and the network on a chip 350 includes target address, burst size, sequence ID, inter-transaction latency, deadline, etc., which are configurable. As shown in the figure, when the data amount sent to the network on a chip 350 is too large, it will cause congestion of the network on a chip 350, at this time, the size of the data amount needs to be reduced. In addition, the traffic tracking module 321 can be used for post-analysis of the task driving module 315 and support extraction and conversion of traces from other platforms. Figure 5

[0066] Optionally, the simulation architecture 300 provided by the embodiment can analyze and evaluate the decomposed test case. For example, the evaluation can be performed through maximum throughput verification of the target device, real-time task delay analysis, key task deadline analysis, ordinary task bandwidth analysis, multi-core-cache delay analysis, firmware timing analysis, etc. According to the comparison of the evaluation result and the system performance index, the simulation architecture 300 can be further optimized. In order to realize better performance analysis, for example, the NOC micro-architecture can be verified, as an example, can include Artersi FlexNoC optimization, cache size, arbitration, quality of service, etc. Several aspects of optimization.

[0067] Figure 6 An example diagram of an implementation component of the simulation architecture of the baseband chip provided by the embodiment of the application. As shown in the figure, the implementation component of the simulation architecture of the baseband chip includes a visualization toolkit, mainly used for generating visual and readable performance analysis reports; a data processing toolkit, mainly used for analyzing and processing data; an architecture and workflow, mainly used for model establishment and implementation of the simulation process; a simulation management toolkit, mainly used for use case management and structure exploration management. Figure 6

[0068] As an embodiment, for performance analysis of the baseband chip, a reasonable workflow is also needed, so as to more accurately capture the functions and characteristics of the architecture resources, and further shorten the development cycle of the baseband chip. Based on the above-mentioned baseband performance analysis method, the application proposes a workflow based on overall performance analysis of the baseband SOC.

[0069] Figure 7 ​​A work flow chart of baseband SOC performance analysis is provided for the embodiments of the present application, and the following refers to the work flow chart as shown in Figure 7 The process of baseband SOC performance analysis is introduced.

[0070] As shown in Figure 7 , the performance analysis of baseband SOC is divided into two parts, pre-silicon 710 and post-silicon 720. The pre-silicon 710, also known as pre-silicon verification, is the related verification work to be completed before the chip is back-processed after the baseband SOC scheme is determined. The post-silicon 720, also known as post-silicon verification, is the related verification work performed after the baseband SOC chip is back-processed.

[0071] Step S711, test case writing. The designer writes the test case according to the system requirements of the product, and divides the soft / hardware modules and functional modules according to the functional requirements.

[0072] Step S712, model building. After completing the module division, the model building of each module is implemented based on the transaction level model using System C language.

[0073] Step S713, debugging and analysis. After completing the model building, the designer needs to complete the implementation of the baseband SOC, and verify the correctness of the RTL code in the implementation process.

[0074] Step S721, exploration and optimization. After confirming that the RTL code is correct, the designer converts the RTL code into a logic circuit through a hardware description language; then, the chip is back-processed; after the chip is back-processed, the chip needs to be verified. For example, module-level verification can be used, that is, the function and performance of each module in the chip are verified to see whether they meet the requirements.

[0075] Step S722, verification. The baseband chip is verified as a whole, the function and performance of the interconnection between all modules are compared with the model, thereby the component features and micro-architecture in the module are optimized, and the accuracy of the model is improved.

[0076] The above steps constitute a closed-loop work flow of baseband SOC performance analysis. The work flow cooperates with the baseband performance analysis method to obtain more accurate information, thereby completing the optimization of the simulation architecture and improving the reliability and accuracy of the simulation architecture.

[0077] As part of the architecture exploration process, this application proposes a novel and efficient method for performance analysis of baseband chips. This method is based on transaction-level System C modeling techniques, featuring highly abstract functional specifications and detailed architectural behavior coverage. This method enables a very fast and accurate evaluation of the baseband chip architecture in the initial stages of baseband chip design. Simultaneously, this method can capture the baseband chip functionality and performance analysis of each architectural resource as a sequence of tracking primitives, which are converted into transactions during simulated runtime, providing guidance and direction for architectural decisions regarding the implementation of the baseband chip.

[0078] In addition, the simulation method for baseband chips proposed in this application has a high level of process automation, which can automatically record the architecture exploration process, track revision control tags on the information flow, and has fully reproducible revision control results, i.e., it can be accurately replicated. It also features free trial and the ability to use open source libraries for internal development.

[0079] The above text combined Figures 2 to 7 The method embodiments of this application are described in detail below, in conjunction with... Figure 8 This application describes embodiments of the simulation system proposed in this paper. It should be understood that the description of this part of the embodiments corresponds to the description of the method embodiments; therefore, any parts not described in detail can be referred to the foregoing method embodiments.

[0080] Figure 8 This is a schematic diagram of the structure of a simulation system provided in an embodiment of this application. Figure 8 The simulation system runs a simulation architecture for the baseband chip, which may be, for example, the simulation architecture 300 mentioned above. Simulation architecture 300 is a transaction-level model-based architecture, and simulation architecture 300 includes at least one module modeled using the System C language.

[0081] like Figure 8 As shown, the simulation system 800 includes a memory 810 and a processor 820. The memory 810 is used to store data; the processor 820 is used to execute the data stored in the memory 810 to perform the following operations: inputting test cases into the simulation architecture of the baseband chip to obtain test data; wherein, the test data includes the maximum throughput and air interface downlink configuration parameters of the baseband chip; and analyzing the performance of the baseband chip based on the test data.

[0082] Optionally, the simulation architecture of the baseband chip includes a physical layer processing module, a data plane shifting module, and an external storage module. The physical layer module is used to perform physical layer operations, and the data plane shifting module is used to shift the baseband data output by the physical layer module to the external storage module.

[0083] Optionally, the simulation architecture of the baseband chip further comprises a CPU module, the CPU module, the physical layer processing module, the data plane moving module and the external storage module are connected through the network on chip, and the data plane moving module moves the baseband data into the external storage module in the form of DMA.

[0084] Optionally, the CPU module and the data plane moving module are provided with a module for tracking and debugging the traffic of the network on chip.

[0085] Optionally, the physical layer processing module comprises one or more of the following modules: a DSP core, a microprocessor core, an on-chip memory, a HARQ module, a task driving module, the task driving module communicates with the network on chip to execute the physical layer related tasks through the network on chip.

[0086] As an embodiment, the simulation architecture 300 can also be associated with system verification to calibrate the simulation architecture 300 to be more optimal. For example, the entry of the traffic can be controlled, the auxiliary function can be used to define simple test cases, the Perl module can be used to make more complex test patterns, the object class can help to build complex use cases, the defined sub-use cases are mixed and matched, and the sub-components are isolated for debugging.

[0087] As an embodiment, the DMA module 322 can be based on the flow configuration tool of Excel, and irrelevant information can be abstracted. For example, the key parameters of the DMA module 322 can include initiator name, source memory, target memory, block size, burst size, peak throughput, start time offset, repetition interval, deadline, NOC sequence ID, etc.

[0088] As an embodiment, the running simulation of the simulation architecture 300 can realize script management through an automated process, and can provide test case names and any required adjustment parameters. The script starts the regression system, which manages the simulation process, data post-processing, visualization and report generation steps. When the long-running test is completed and the results are available, an email can be sent to the user.

[0089] As an embodiment, the performance analysis report provided by the baseband performance analysis method can automatically generate a PDF. There are standardized templates that are easy to access (reused between projects, abstracting NOC and DDR implementation details) and clear time points. At the same time, the version history (reproducibility) can be captured in the report.

[0090] It should be understood that in various embodiments of the present application, the size of the sequence number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0091] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the embodiments of the device described above are merely schematic; the division of the units is only a logical function division; there can be another division manner in actual implementation; for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0092] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0093] In addition, each functional unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0094] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be read by a computer or a data storage device such as a server, data center and the like integrated with one or more available media sets. The available media can be magnetic media (for example, floppy disk, hard disk, magnetic tape), optical media (for example, digital video disc (DVD)) or semiconductor media (for example, solid state disk (SSD)) and the like.

[0095] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for analyzing baseband performance, characterized in that, include: Test cases are input into the simulation architecture of the baseband chip to obtain test data. The simulation architecture is a transaction-level model-based architecture, and the simulation architecture includes at least one module modeled using System C language. The test data includes the maximum throughput and air interface downlink configuration parameters of the baseband chip. The transaction-level model communicates through function calls. The performance of the baseband chip was analyzed based on the test data. The simulation architecture of the baseband chip includes a physical layer processing module, a data plane shifting module, and an external storage module. The physical layer module is used to perform physical layer operations, and the data plane shifting module is used to shift the baseband data output by the physical layer module to the external storage module. The data plane migration module is used to adjust the write priority order of data between modules in the physical layer module, and to read / write data between modules to the external storage module in a time-sharing manner according to the write priority order; The simulation architecture of the baseband chip also includes a CPU module. The CPU module, the physical layer processing module, the data plane transfer module, and the external storage module are connected through an on-chip network. The data plane transfer module transfers the baseband data to the external storage module in a DMA manner. The CPU module and the data plane transfer module are equipped with a task-driven module and a traffic tracking module. The task-driven module executes the tasks of the physical layer module through the on-chip network. The traffic tracing module is used to perform one or more of the following: The task execution process of the task-driven module is marked; Fine-grained control is performed on the traffic of the on-chip network; The task-driven module is subjected to post-event analysis, and traces can be extracted and converted from other platforms.

2. The method according to claim 1, characterized in that, The physical layer processing module includes one or more of the following modules: DSP core, microprocessor core, on-chip memory, HARQ module, and task-driven module. The task-driven module communicates with the on-chip network to execute physical layer-related tasks through the on-chip network.

3. A simulation system, characterized in that, The simulation system runs a simulation architecture of a baseband chip. The simulation architecture is based on a transaction-level model and includes at least one module modeled using the System C language. The transaction-level model communicates through function calls. The simulation system includes: A memory used to store data; A processor is configured to execute the data stored in the memory to perform the following operations: Test cases are input into the simulation architecture of the baseband chip to obtain test data; wherein, the test data includes the maximum throughput and air interface downlink configuration parameters of the baseband chip; The performance of the baseband chip was analyzed based on the test data. The simulation architecture of the baseband chip includes a physical layer processing module, a data plane shifting module, and an external storage module. The physical layer module is used to perform physical layer operations, and the data plane shifting module is used to shift the baseband data output by the physical layer module to the external storage module. The data plane migration module is used to adjust the write priority order of data between modules in the physical layer module, and to read / write data between modules to the external storage module in a time-sharing manner according to the write priority order; The simulation architecture of the baseband chip also includes a CPU module. The CPU module, the physical layer processing module, the data plane transfer module, and the external storage module are connected through an on-chip network. The data plane transfer module transfers the baseband data to the external storage module in a DMA manner. The CPU module and the data plane transfer module are equipped with a task-driven module and a traffic tracking module. The task-driven module executes the tasks of the physical layer module through the on-chip network. The traffic tracing module is used to perform one or more of the following: The task execution process of the task-driven module is marked; Fine-grained control is performed on the traffic of the on-chip network; The task-driven module is subjected to post-event analysis, and traces can be extracted and converted from other platforms.

4. The simulation system according to claim 3, characterized in that, The physical layer processing module includes one or more of the following modules: DSP core, microprocessor core, on-chip memory, HARQ module, and task-driven module. The task-driven module communicates with the on-chip network to execute physical layer-related tasks through the on-chip network.

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