A method and device for evaluating fault prediction performance

Abstract

The present invention discloses a method and device for evaluating fault prediction performance, which can determine at least one key circuit in a target board; determine the critical failure mode failure rate of each key circuit to determine the total critical failure mode failure rate of the target board; respectively determine the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each key circuit to determine the total predictable critical failure mode failure rate of the target board; determine the prediction coverage rate of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board; and evaluate the fault prediction performance of the target board based on the prediction coverage rate of the target board. The present invention proposes the prediction coverage rate of the target board as an evaluation indicator, and can determine the prediction coverage rate of the target board. The determined prediction coverage rate is used to quantitatively evaluate the fault prediction effect of the target board, effectively evaluating the fault prediction performance of the target board.

Description

Technical Field

[0001] The present invention relates to the technical field of fault prediction, and in particular to a method and device for evaluating fault prediction performance. Background Art

[0002] With the development of Prognostic and Health Management (PHM) and the advancement of intelligent operation and maintenance technology for nuclear power instrumentation and control, the fault diagnosis technology for nuclear power instrumentation and control system boards has been continuously improved.

[0003] Specifically, existing technologies can evaluate the effectiveness of a board's diagnostic design based on diagnostic coverage. A higher diagnostic coverage indicates that a dangerous failure of the board is more likely to be diagnosed immediately. Diagnostic coverage can reflect the safety of nuclear power instrumentation and control systems.

[0004] Currently, existing technologies can also predict potential board failures in advance. When a board failure is predicted, appropriate troubleshooting procedures can be implemented in advance, or the board can be adjusted to prevent the failure and mitigate its impact. It should be noted that the better the design performance of board failure prediction, the easier it is to predict when a board failure is about to occur.

[0005] However, existing technologies cannot effectively evaluate the fault prediction performance of boards. Summary of the Invention

[0006] In view of the above problems, the present invention provides a method and device for evaluating fault prediction performance that overcomes the above problems or at least partially solves the above problems. The technical solution is as follows:

[0007] A method for evaluating fault prediction performance, comprising:

[0008] Identifying at least one critical circuit in a target board;

[0009] Determining the failure rate of the key failure mode of each of the key circuits;

[0010] Determining the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each of the critical circuits;

[0011] Determining respectively the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each of the critical circuits;

[0012] Determining the total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each of the critical circuits;

[0013] Determining the prediction coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board;

[0014] Based on the prediction coverage of the target board, the fault prediction performance of the target board is evaluated.

[0015] Optionally, respectively determining the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit includes:

[0016] Determining adjustment coefficients corresponding to failure rates of key failure modes of each of the key circuits;

[0017] For any of the critical circuits: a product of the critical failure mode failure rate of the critical circuit and the corresponding adjustment coefficient is determined as the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of the critical circuit.

[0018] Optionally, determining the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each of the critical circuits includes:

[0019] The sum of the critical failure mode failure rates of the critical circuits is determined as the total critical failure mode failure rate of the target board.

[0020] Optionally, determining the total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each of the critical circuits includes:

[0021] Determining a sum of the predictable critical failure mode failure rates corresponding to the critical failure mode failure rates of the critical circuits;

[0022] The determined sum value is determined as the total predictable critical failure mode failure rate of the target board.

[0023] Optionally, determining the prediction coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board includes:

[0024] determining a ratio of the total predictable critical failure mode failure rate to the total critical failure mode failure rate;

[0025] The determined ratio is determined as the predicted coverage rate of the target board.

[0026] Optionally, the evaluating the fault prediction performance of the target board based on the prediction coverage of the target board includes:

[0027] When the prediction coverage of the target board is greater, it is determined that the fault prediction performance of the target board is stronger.

[0028] A device for evaluating fault prediction performance includes: a circuit determination unit, a first determination unit, a second determination unit, a third determination unit, a fourth determination unit, a coverage determination unit, and an evaluation unit; wherein:

[0029] The circuit determination unit is used to determine at least one key circuit in the target board;

[0030] The first determining unit is used to determine the failure rate of the key failure mode of each of the key circuits;

[0031] The second determining unit is configured to determine the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each of the critical circuits;

[0032] The third determining unit is used to respectively determine the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each of the critical circuits;

[0033] The fourth determining unit is configured to determine a total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rates corresponding to the critical failure mode failure rates of the critical circuits;

[0034] The coverage determination unit is configured to determine the predicted coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board;

[0035] The evaluation unit is configured to evaluate the fault prediction performance of the target board based on the prediction coverage of the target board.

[0036] Optionally, the third determining unit includes: a coefficient determining unit and a fifth determining unit;

[0037] The coefficient determination unit is used to respectively determine the adjustment coefficient corresponding to the failure rate of the key failure mode of each of the key circuits;

[0038] The fifth determining unit is configured to determine, for any of the critical circuits, a product of the critical failure mode failure rate of the critical circuit and the corresponding adjustment coefficient as a predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of the critical circuit.

[0039] Optionally, the second determining unit is configured to determine the sum of the critical failure mode failure rates of the critical circuits as the total critical failure mode failure rate of the target board.

[0040] Optionally, the fourth determining unit includes: a sum determining unit and a sixth determining unit;

[0041] The sum value determination unit is used to determine the sum value of the predictable key failure mode failure rates corresponding to the key failure mode failure rates of each of the key circuits;

[0042] The sixth determining unit is configured to determine the determined sum value as the total predictable critical failure mode failure rate of the target board.

[0043] Optionally, the coverage determination unit includes: a ratio determination unit and a seventh determination unit;

[0044] The ratio determination unit is configured to determine a ratio of the total predictable critical failure mode failure rate to the total critical failure mode failure rate;

[0045] The seventh determining unit is configured to determine the determined ratio as the predicted coverage rate of the target board.

[0046] Optionally, the evaluation unit is configured to determine that the fault prediction performance of the target board is stronger when the prediction coverage of the target board is greater.

[0047] The present invention proposes a method and device for evaluating fault prediction performance, which can determine at least one key circuit in a target board; determine the critical failure mode failure rate of each key circuit; determine the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each key circuit; determine the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each key circuit; determine the total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each key circuit; determine the prediction coverage rate of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board; and evaluate the fault prediction performance of the target board based on the prediction coverage rate of the target board. The present invention proposes the prediction coverage rate of the target board as an evaluation indicator, and can determine the prediction coverage rate of the target board. The determined prediction coverage rate is used to quantitatively evaluate the fault prediction effect of the target board, effectively evaluating the fault prediction performance of the target board.

[0048] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0050] Figure 1 A flowchart illustrating a first method for evaluating fault prediction performance provided by an embodiment of the present invention is shown;

[0051] Figure 2 A flowchart illustrating a second method for evaluating fault prediction performance provided by an embodiment of the present invention is shown;

[0052] Figure 3 A flowchart illustrating a third method for evaluating fault prediction performance provided by an embodiment of the present invention is shown;

[0053] Figure 4 A flowchart of a fourth method for evaluating fault prediction performance provided by an embodiment of the present invention is shown;

[0054] Figure 5 A schematic structural diagram of a fault prediction performance evaluation device provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0056] like Figure 1 As shown, this embodiment proposes a first method for evaluating fault prediction performance, which may include the following steps:

[0057] S101, determining at least one key circuit in a target board;

[0058] The target board may be a board in a nuclear power instrumentation and control system.

[0059] The key circuit may be a circuit in the target board whose circuit operating status or operating parameters need to be monitored.

[0060] Optionally, the present invention can identify all critical circuits of the target board in a Failure Mode Effects and Criticality Analysis (FMECA) report. Optionally, the critical circuits can also be determined by a technician based on actual conditions.

[0061] S102, determining the failure rate of key failure modes of each key circuit;

[0062] The critical failure mode failure rate may be the failure rate of a certain critical failure mode.

[0063] The critical failure mode may be a critical failure mode of a critical circuit.

[0064] It should be noted that a critical circuit may have one or more critical failure modes. For a critical circuit, when the critical circuit has multiple critical failure modes, each critical failure mode has a corresponding critical failure mode failure rate. In this case, the critical circuit has multiple critical failure mode failure rates.

[0065] Specifically, the present invention can determine the failure rate of key failure modes of each key circuit in the target board through the FMECA report.

[0066] It is understandable that if a critical circuit has multiple critical failure modes, the present invention may determine the failure rate of each critical mode of the critical circuit separately when determining the failure rate of the critical failure mode of the critical circuit.

[0067] S103, determining the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each critical circuit;

[0068] Specifically, after determining the failure rate of the key failure mode of each key circuit, the present invention can determine the total failure rate of the key failure mode based on the failure rate of each key failure mode.

[0069] Optionally, step S103 may include:

[0070] The sum of the failure rates of the key failure modes of each key circuit is determined as the total failure rate of the key failure mode of the target board.

[0071] Specifically, the present invention can calculate the sum of the failure rates of the key failure modes of each key circuit, and determine the sum as the total failure rate of the key failure mode of the target board.

[0072] Optionally, after determining the critical failure mode failure rate of each key circuit, the present invention may first assign a weight to the critical failure mode failure rate of each key circuit, and then perform a weighted sum based on the critical failure mode failure rate of each key circuit and its weight to calculate the total critical failure mode failure rate of the target board. For example, if the critical failure mode failure rate of the first key circuit in the target board is A with a weight a, and the critical failure mode failure rate of the second key circuit is B with a weight b, then the product of A and a can be calculated, and the product of B and b can be calculated, and the two calculated products can be summed. The value obtained by the summation is the total critical failure mode failure rate of the target board.

[0073] S104, respectively determining the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit;

[0074] The predictable critical failure mode failure rate may be a predictable failure rate of a certain critical failure mode.

[0075] Specifically, for a critical failure mode failure rate, after determining the critical failure mode failure rate, the present invention can determine a predictable critical failure mode failure rate corresponding to the critical failure mode failure rate.

[0076] Optionally, for the predictable critical failure mode failure rate of a certain critical failure mode, the present invention can first determine the health parameter corresponding to the critical failure mode, and then use the inherent gradual characteristics of the health parameter and the critical failure mode failure rate of the critical failure mode to determine the predictable critical failure mode failure rate of the critical failure mode.

[0077] The health parameter can directly or indirectly reflect the corresponding critical failure mode. For example, when the critical failure mode is output overvoltage or output undervoltage, the health parameter can be the output voltage that directly reflects the critical failure mode, or the power supply efficiency that indirectly reflects the critical failure mode.

[0078] The inherent gradual change characteristics of the health parameters may be the gradual change characteristics of the health parameters during the process from a normal range to a fault, that is, the concept of aging in the usual sense.

[0079] Optional, such as Figure 2 As shown, in the second fault prediction performance evaluation method proposed in this embodiment, step S104 may include:

[0080] S1041. Determine the adjustment coefficient corresponding to the failure rate of the key failure mode of each key circuit respectively;

[0081] It should be noted that, for a certain critical failure mode, if the selected health parameter is the first health parameter, and the prior art does not clearly indicate that the first health parameter has a gradual change characteristic, the present invention can determine the corresponding adjustment coefficient based on a predefined evaluation principle.

[0082] Optionally, the evaluation principle may include a first evaluation principle, a second evaluation principle, a third evaluation principle and / or a fourth evaluation principle.

[0083] The first evaluation principle may be that when authoritative technical literature, tests, and field problems prove that the first health parameter has a gradual change characteristic, the present invention may determine that the adjustment coefficient of the critical failure mode is 100%.

[0084] The second evaluation principle may be that when the research technical literature shows that the first health parameter has a gradual change characteristic and there is complete proof, the present invention may determine that the adjustment coefficient of the critical failure mode is 75%.

[0085] Among them, the third evaluation principle can be that when there is a reference to a discussion on the gradual change characteristics of the first health parameter in research technical literature, or when product development experience believes that the first health parameter has a gradual change characteristic, the present invention can determine that the adjustment coefficient of the critical failure mode is 50%.

[0086] The fourth evaluation principle may be that when the prior art believes that the first health parameter may have a gradual change characteristic but still needs to be confirmed, the present invention may determine that the adjustment coefficient of the critical failure mode is 25%.

[0087] S1042. For any critical circuit: multiply the failure rate of the critical failure mode of the critical circuit by the corresponding adjustment coefficient to determine the predictable critical failure mode failure rate corresponding to the failure rate of the critical failure mode of the critical circuit.

[0088] Specifically, when determining the predictable critical failure mode failure rate of a critical failure mode of a critical circuit, the present invention can multiply the critical failure mode failure rate of the critical failure mode by its corresponding adjustment coefficient, and determine the product obtained by the multiplication as the predictable critical failure mode failure rate of the critical failure mode.

[0089] It should be noted that, for a certain critical failure mode, the present invention can adjust and optimize the adjustment coefficient of the critical failure mode to generate a new adjustment coefficient, and use the new adjustment coefficient to calculate a new predictable critical failure mode failure rate.

[0090] It is understood that for a critical circuit, if the critical circuit has multiple critical failure modes, the present invention can separately determine the predictable critical failure mode failure rate for each critical failure mode of the critical circuit. Furthermore, the present invention can separately determine the predictable critical failure mode failure rate for each critical failure mode of the critical circuit.

[0091] S105, determining the total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit;

[0092] Specifically, after determining the predictable critical failure mode failure rate of the critical failure mode of each critical circuit in the target board, the present invention can determine the total predictable critical failure mode failure rate of the target board based on all predictable critical failure mode failure rates of the target board.

[0093] Optional, such as Figure 3 As shown, in the third fault prediction performance evaluation method proposed in this embodiment, step S105 may include:

[0094] S1051. Determine the sum of the predictable critical failure mode failure rates corresponding to the critical failure mode failure rates of each critical circuit;

[0095] Specifically, after determining the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit in the target board, that is, all the predictable critical failure mode failure rates of the target board, the present invention can add up all the predictable critical failure mode failure rates of the target board to obtain the corresponding sum value.

[0096] S1052: Determine the determined sum value as the total predictable critical failure mode failure rate of the target board.

[0097] Specifically, after obtaining the sum of all predictable critical failure mode failure rates of the target board, the present invention can determine the sum as the total predictable critical failure mode failure rate of the target board.

[0098] Optionally, after determining all predictable critical failure mode failure rates of the target board, the present invention first assigns weights to each predictable critical failure mode failure rate respectively, and then performs weighted summation on the weighted predictable critical failure mode failure rates to obtain a corresponding sum value and determines the sum value as the total predictable critical failure mode failure rate of the target board.

[0099] S106, determining the prediction coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board;

[0100] Specifically, after determining the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board, the present invention can calculate the predicted coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board.

[0101] Optional, such as Figure 4 As shown, in the fourth fault prediction performance evaluation method proposed in this embodiment, step S106 may include:

[0102] S1061. Determine the ratio of the total predictable critical failure mode failure rate to the total critical failure mode failure rate;

[0103] Specifically, after determining the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board, the present invention can divide the total predictable critical failure mode failure rate by the total critical failure mode failure rate to obtain a corresponding quotient, that is, the ratio of the total predictable critical failure mode failure rate to the total critical failure mode failure rate.

[0104] S1062: Determine the determined ratio as the predicted coverage rate of the target board.

[0105] Specifically, after obtaining the ratio of the total predictable critical failure mode failure rate to the total critical failure mode failure rate, the present invention can determine the ratio as the prediction coverage of the target board.

[0106] Optionally, after determining the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board, the present invention can also use the correction factor to first make corresponding corrections to the total critical failure mode failure rate and the total predictable critical failure mode failure rate, and then calculate the ratio of the corrected total critical failure mode failure rate to the total predictable critical failure mode failure rate, and determine the ratio as the predicted coverage of the target board.

[0107] Optionally, after determining the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board, the present invention can also input the total critical failure mode failure rate and the total predictable critical failure mode failure rate into a predefined prediction coverage calculation model to obtain the prediction coverage output by the prediction coverage calculation model.

[0108] S107 : Evaluate the fault prediction performance of the target board based on the prediction coverage of the target board.

[0109] Specifically, after determining the prediction coverage of the target board, the present invention can evaluate the fault prediction performance of the target board based on the prediction coverage of the target board.

[0110] It should be noted that the prediction coverage of the target board and its fault prediction performance can be positively correlated. Optionally, when the prediction coverage of the target board is greater, the fault prediction performance of the target board is determined to be stronger; alternatively, when the prediction coverage of the target board is smaller, the present invention can determine that the fault prediction performance of the target board is weaker.

[0111] Optionally, the present invention can classify the fault prediction performance of the target board based on the prediction coverage. Specifically, when the prediction coverage is within a first interval, the present invention can determine that the fault prediction performance of the target board is weak; when the prediction coverage is within a second interval, the present invention can determine that the fault prediction performance of the target board is normal; when the prediction coverage is within a third interval, the present invention can determine that the fault prediction performance of the target board is good; and when the prediction coverage is within a fourth interval, the present invention can determine that the fault prediction performance of the target board is optimal.

[0112] It can be understood that the present invention can quantitatively evaluate the fault prediction effect of the target board by predicting coverage, and determine whether to improve the design of the fault prediction effect of the target board, i.e., predictive design, based on the quantitative evaluation results, so that the fault prediction effect of the target board can meet the requirements or even continue to improve.

[0113] It should be noted that the present invention proposes a targeted evaluation index, prediction coverage, to evaluate the fault prediction effect of the target board. Figure 1 The method shown realizes the determination of the prediction coverage of the target board, and uses the determined prediction coverage to realize the quantitative evaluation of the fault prediction effect of the target board, thereby effectively realizing the evaluation of the fault prediction performance of the target board.

[0114] The fault prediction performance evaluation method proposed in this embodiment can determine at least one key circuit in a target board; determine the key failure mode failure rate of each key circuit; determine the total key failure mode failure rate of the target board based on the key failure mode failure rate of each key circuit; determine the predictable key failure mode failure rate corresponding to the key failure mode failure rate of each key circuit; determine the total predictable key failure mode failure rate of the target board based on the predictable key failure mode failure rate corresponding to the key failure mode failure rate of each key circuit; determine the prediction coverage rate of the target board based on the total key failure mode failure rate and the total predictable key failure mode failure rate of the target board; and evaluate the fault prediction performance of the target board based on the prediction coverage rate of the target board. The present invention proposes the prediction coverage rate of the target board as an evaluation indicator, and can determine the prediction coverage rate of the target board. The determined prediction coverage rate is used to quantitatively evaluate the fault prediction effect of the target board, thereby effectively evaluating the fault prediction performance of the target board.

[0115] and Figure 1 The method shown corresponds to Figure 5 As shown, this embodiment provides a device for evaluating fault prediction performance. The device may include a circuit determination unit 101, a first determination unit 102, a second determination unit 103, a third determination unit 104, a fourth determination unit 105, a coverage determination unit 106, and an evaluation unit 107; wherein:

[0116] The circuit determination unit 101 is configured to determine at least one key circuit in a target board;

[0117] A first determining unit 102 is configured to determine a failure rate of a key failure mode of each key circuit;

[0118] The second determining unit 103 is configured to determine the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each critical circuit;

[0119] The third determining unit 104 is configured to determine the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit;

[0120] The fourth determining unit 105 is configured to determine the total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit;

[0121] A coverage determination unit 106 is configured to determine a predicted coverage of a target board based on a total critical failure mode failure rate and a total predictable critical failure mode failure rate of the target board;

[0122] The evaluation unit 107 is configured to evaluate the fault prediction performance of the target board based on the prediction coverage of the target board.

[0123] It should be noted that the specific processing procedures of the circuit determination unit 101, the first determination unit 102, the second determination unit 103, the third determination unit 104, the fourth determination unit 105, the coverage determination unit 106 and the evaluation unit 107 and the technical effects thereof can be referred to respectively. Figure 1 Steps S101, S102, S103, S104, S105, S106 and S107 in .

[0124] Optionally, the third determining unit 104 includes: a coefficient determining unit and a fifth determining unit;

[0125] A coefficient determination unit, used to determine the adjustment coefficient corresponding to the failure rate of the key failure mode of each key circuit;

[0126] The fifth determining unit is configured to determine, for any critical circuit, a product of the critical failure mode failure rate of the critical circuit and the corresponding adjustment coefficient as the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of the critical circuit.

[0127] Optionally, the second determining unit 103 is configured to determine the sum of the critical failure mode failure rates of the critical circuits as the total critical failure mode failure rate of the target board.

[0128] Optionally, the fourth determining unit 105 includes: a sum determining unit and a sixth determining unit;

[0129] a sum value determination unit, configured to determine a sum value of the predictable key failure mode failure rates corresponding to the key failure mode failure rates of each key circuit;

[0130] The sixth determining unit is configured to determine the determined sum value as the total predictable critical failure mode failure rate of the target board.

[0131] Optionally, the coverage determination unit 106 includes: a ratio determination unit and a seventh determination unit;

[0132] a ratio determination unit, used to determine the ratio of the total predictable critical failure mode failure rate to the total critical failure mode failure rate;

[0133] The seventh determining unit is configured to determine the determined ratio as the predicted coverage of the target board.

[0134] Optionally, the evaluation unit 107 is configured to determine that the fault prediction performance of the target board is stronger when the prediction coverage of the target board is greater.

[0135] The fault prediction performance evaluation device proposed in this embodiment can determine at least one key circuit in a target board; determine the key failure mode failure rate of each key circuit; determine the total key failure mode failure rate of the target board based on the key failure mode failure rate of each key circuit; determine the predictable key failure mode failure rate corresponding to the key failure mode failure rate of each key circuit; determine the total predictable key failure mode failure rate of the target board based on the predictable key failure mode failure rate corresponding to the key failure mode failure rate of each key circuit; determine the prediction coverage rate of the target board based on the total key failure mode failure rate and the total predictable key failure mode failure rate of the target board; and evaluate the fault prediction performance of the target board based on the prediction coverage rate of the target board. The present invention proposes the prediction coverage rate of the target board as an evaluation indicator, and can determine the prediction coverage rate of the target board. The determined prediction coverage rate is used to quantitatively evaluate the fault prediction effect of the target board, thereby effectively evaluating the fault prediction performance of the target board.

[0136] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0137] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A method for evaluating fault prediction performance, characterized in that: include: Identifying at least one critical circuit in a target board; Determining the failure rate of the key failure mode of each of the key circuits; Determining the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each of the critical circuits; Determining respectively the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit, including: determining a health parameter corresponding to the critical failure mode of the critical circuit; the health parameter is used to directly or indirectly reflect the corresponding critical failure mode; using the inherent gradual change characteristics of the health parameter to determine the adjustment coefficient corresponding to the critical failure mode failure rate of the critical circuit; multiplying the critical failure mode failure rate of the critical circuit by the corresponding adjustment coefficient to determine the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of the critical circuit; the predictable critical failure mode failure rate is the predictable failure rate of a certain critical failure mode; Determining the total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each of the critical circuits; Determining the prediction coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board; Based on the prediction coverage of the target board, the fault prediction performance of the target board is evaluated.

2. The method for evaluating fault prediction performance according to claim 1, wherein: Determining the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each critical circuit includes: The sum of the critical failure mode failure rates of the critical circuits is determined as the total critical failure mode failure rate of the target board.

3. The method for evaluating fault prediction performance according to claim 1, wherein: Determining the total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each critical circuit includes: Determining a sum of the predictable critical failure mode failure rates corresponding to the critical failure mode failure rates of the critical circuits; The determined sum value is determined as the total predictable critical failure mode failure rate of the target board.

4. The method for evaluating fault prediction performance according to claim 1, wherein: The determining of the prediction coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board includes: determining a ratio of the total predictable critical failure mode failure rate to the total critical failure mode failure rate; The determined ratio is determined as the predicted coverage rate of the target board.

5. The method for evaluating fault prediction performance according to claim 1, wherein: The evaluating the fault prediction performance of the target board based on the prediction coverage of the target board includes: When the prediction coverage of the target board is greater, it is determined that the fault prediction performance of the target board is stronger.

6. A device for evaluating fault prediction performance, characterized in that: include: a circuit determination unit, a first determination unit, a second determination unit, a third determination unit, a fourth determination unit, a coverage determination unit, and an evaluation unit; wherein: The circuit determination unit is used to determine at least one key circuit in the target board; The first determining unit is used to determine the failure rate of the key failure mode of each of the key circuits; The second determining unit is configured to determine the total critical failure mode failure rate of the target board based on the critical failure mode failure rate of each of the critical circuits; The third determining unit is used to respectively determine the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of each of the critical circuits; The third determining unit includes: a coefficient determining unit and a fifth determining unit; The coefficient determination unit is configured to determine a health parameter corresponding to a critical failure mode of the critical circuit; the health parameter is configured to directly or indirectly reflect the corresponding critical failure mode; and to determine an adjustment coefficient corresponding to a failure rate of the critical failure mode of the critical circuit using an inherent gradual change characteristic of the health parameter; The fifth determining unit is configured to determine the product of the critical failure mode failure rate of the critical circuit and the corresponding adjustment coefficient as the predictable critical failure mode failure rate corresponding to the critical failure mode failure rate of the critical circuit; the predictable critical failure mode failure rate is the predictable failure rate of a certain critical failure mode; The fourth determining unit is configured to determine a total predictable critical failure mode failure rate of the target board based on the predictable critical failure mode failure rates corresponding to the critical failure mode failure rates of the critical circuits; The coverage determination unit is configured to determine the predicted coverage of the target board based on the total critical failure mode failure rate and the total predictable critical failure mode failure rate of the target board; The evaluation unit is configured to evaluate the fault prediction performance of the target board based on the prediction coverage of the target board.

7. The device for evaluating fault prediction performance according to claim 6, wherein: The second determining unit is configured to determine the sum of the critical failure mode failure rates of the critical circuits as the total critical failure mode failure rate of the target board.

8. The device for evaluating fault prediction performance according to claim 6, wherein: The fourth determining unit includes: a sum determining unit and a sixth determining unit; The sum value determination unit is used to determine the sum value of the predictable key failure mode failure rates corresponding to the key failure mode failure rates of each of the key circuits; The sixth determining unit is configured to determine the determined sum value as the total predictable critical failure mode failure rate of the target board.

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