A slot identification method, device, equipment and machine-readable storage medium

Abstract

The present disclosure provides a slot identification method, device, equipment and machine-readable storage medium, the method comprising: assigning an associated PCIE port to each GPIO channel; changing the signal of the GPIO channel one by one, and obtaining the association relationship between each slot and each GPIO channel according to the signal change associated with the GPIO channel signal change in the slot; and obtaining the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel. Through the technical solution of the present disclosure, the signal of the GPIO channel is changed one by one, and the physical connection relationship between the slot and the GPIO is obtained by reading the signal change of the slot, thereby obtaining the corresponding relationship between the slot and the PCIE port associated with the GPIO, so that the BIOS can correctly identify the hardware devices of different slot arrangements and combinations without software upgrade, and correctly allocate PCIE ports and bandwidth to the PCIE slots.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a slot identification method, device, equipment, and machine-readable storage medium. Background Art

[0002] PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. It is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) and other functions.

[0003] GPIO (General-purpose input / output) is similar in function to P0-P3 of 8051. Its pins can be freely used by users through program control. The pins can be used as general-purpose input (GPI) or general-purpose output (GPO) or general-purpose input and output (GPIO) according to practical considerations. A pin can be used for input, output or other special functions, and registers can be used to select these functions. For input, the pin voltage level can be determined by reading a register; for output, the pin can be made to output high or low voltage by writing to a register; for other special functions, there are other registers to control them.

[0004] A RISER card generally refers to a function expansion card or adapter card that is inserted into a PCI-E interface.

[0005] Server CPUs support many PCIE signals for expanding peripherals such as GPUs, network cards, storage controllers, etc. For example, Intel's Xeon CPU supports 5-way X16 PCIE4.0 models.

[0006] In order to support various configurations, servers will support many PCIE slot expansion cards, also known as RISER cards. PCIE slots generally have at least two types, with two bandwidths, X8 and X16. Eventually, the same PCIE port of the CPU may be connected to different slots or the same slot but with different bandwidths. The BIOS software needs to know the above two pieces of information to correctly configure PCIE resources. Usually, the BIOS configuration solution is based on a fixed combination of components. Whenever a new combination is added, the software has to develop a new version to be compatible with the hardware, which is very inefficient. Summary of the invention

[0007] In view of this, the present disclosure provides a slot identification method, device, electronic device, and machine-readable storage medium to improve the problem that the above-mentioned BIOS cannot correctly identify the PCIE slot after the PCIE slot changes.

[0008] The specific technical solutions are as follows:

[0009] The present disclosure provides a slot identification method, which is applied to a server. The method includes: allocating an associated PCIE port to each GPIO channel; changing the signals of the GPIO channels one by one, and obtaining the association relationship between each slot and each GPIO channel according to the signal change associated with the GPIO channel signal change in the slot; and obtaining the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel.

[0010] As a technical solution, allocating an associated PCIE port to each GPIO channel includes: allocating an associated PCIE port to each GPIO channel according to the minimum number of PCIE ports that can be associated with a single slot.

[0011] As a technical solution, the step of changing the signals of the GPIO channels one by one and obtaining the association relationship between each slot and each GPIO channel according to the signal change in the slot that is associated with the signal change of the GPIO channel includes: obtaining that the same slot is simultaneously associated with the two GPIO channels according to the signal changes of two GPIO channels that are associated with the signal change of the same slot; and obtaining the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel includes: obtaining the association relationship between each slot and the PCIE port associated with the two GPIO channels.

[0012] As a technical solution, the server includes a RISER device, the RISER device includes a plurality of slots, and the slots establish a communication connection with a BIOS module through a GPIO channel.

[0013] The present disclosure also provides a slot identification device, which is applied to a server, and the device includes: a processing module, which is used to assign an associated PCIE port to each GPIO channel; a detection module, which is used to change the signal of the GPIO channel one by one, and obtain the association relationship between each slot and each GPIO channel according to the signal change associated with the GPIO channel signal change in the slot; a logic module, which is used to obtain the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel.

[0014] As a technical solution, allocating an associated PCIE port to each GPIO channel includes: allocating an associated PCIE port to each GPIO channel according to the minimum number of PCIE ports that can be associated with a single slot.

[0015] As a technical solution, the step of changing the signals of the GPIO channels one by one and obtaining the association relationship between each slot and each GPIO channel according to the signal change in the slot that is associated with the signal change of the GPIO channel includes: obtaining that the same slot is simultaneously associated with the two GPIO channels according to the signal changes of two GPIO channels that are associated with the signal change of the same slot; and obtaining the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel includes: obtaining the association relationship between each slot and the PCIE port associated with the two GPIO channels.

[0016] As a technical solution, the server includes a RISER device, the RISER device includes a plurality of slots, and the slots establish a communication connection with a BIOS module through a GPIO channel.

[0017] The present disclosure also provides an electronic device, including a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the aforementioned slot identification method.

[0018] The present disclosure also provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the aforementioned slot identification method.

[0019] The above technical solution provided by the present disclosure brings at least the following beneficial effects:

[0020] By changing the signals of the GPIO channels one by one and reading the signal changes of the slots, the physical connection relationship between the slots and the GPIO is obtained, thereby obtaining the corresponding relationship between the slots and the PCIE ports associated with the GPIO, so that the BIOS can correctly identify the hardware devices in different slot arrangements and combinations without upgrading the software, and correctly allocate PCIE ports and bandwidth to the PCIE slots. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments of the present disclosure or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings of the embodiments of the present disclosure.

[0022] Figure 1 is a flow chart of a slot identification method in one embodiment of the present disclosure;

[0023] Figure 2 is a structural diagram of a slot identification device in one embodiment of the present disclosure;

[0024] Figure 3 It is a hardware structure diagram of an electronic device in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, rather than limiting the present disclosure. The singular forms of "a", "said" and "the" used in the present disclosure and claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to any or all possible combinations of one or more associated listed items.

[0026] It should be understood that although the terms first, second, third, etc. may be used to describe various information in the embodiments of the present disclosure, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, in addition, the word "if" used may be interpreted as "at the time of" or "when" or "in response to determining".

[0027] The present disclosure provides a slot identification method, device, electronic device, and machine-readable storage medium to improve the problem that the above-mentioned BIOS cannot correctly identify the PCIE slot after the PCIE slot changes.

[0028] Specifically, the technical solution is as described below.

[0029] In one embodiment, the present disclosure provides a slot identification method, which is applied to a server, and the method includes: allocating an associated PCIE port to each GPIO channel; changing the signals of the GPIO channels one by one, and obtaining the association relationship between each slot and each GPIO channel based on the signal changes in the slot associated with the GPIO channel signal changes; based on the association relationship between each slot and each GPIO channel, obtaining the association relationship between each slot and the corresponding PCIE port.

[0030] Specifically, Figure 1 , including the following steps:

[0031] Step S11, assigning an associated PCIE port to each GPIO channel;

[0032] Step S12, changing the signals of the GPIO channels one by one, and obtaining the association relationship between each slot and each GPIO channel according to the signal change in the slot associated with the signal change of the GPIO channel;

[0033] Step S13, according to the association relationship between each slot and each GPIO channel, obtain the association relationship between each slot and the corresponding PCIE port.

[0034] By changing the signals of the GPIO channels one by one and reading the signal changes of the slots, the physical connection relationship between the slots and the GPIO is obtained, thereby obtaining the corresponding relationship between the slots and the PCIE ports associated with the GPIO, so that the BIOS can correctly identify the hardware devices in different slot arrangements and combinations without upgrading the software, and correctly allocate PCIE ports and bandwidth to the PCIE slots.

[0035] In one implementation, allocating an associated PCIE port to each GPIO channel includes: allocating an associated PCIE port to each GPIO channel according to a minimum number of PCIE ports that can be associated with a single slot.

[0036] In one embodiment, the step of changing the signals of the GPIO channels one by one and obtaining the association relationship between each slot and each GPIO channel according to the signal change in the slot that is associated with the signal change of the GPIO channel includes: obtaining that the same slot is simultaneously associated with the two GPIO channels according to the signal changes of two GPIO channels that are associated with the signal change of the same slot; and obtaining the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel includes: obtaining the association relationship between each slot and the PCIE port associated with the two GPIO channels.

[0037] In one implementation, the server includes a RISER device, the RISER device includes a plurality of slots, and the slots establish a communication connection with the BIOS module through a GPIO channel.

[0038] In one implementation, the hardware design needs to provide GPIO that can be controlled by the BIOS, temporarily defined as slot-controlled GPIO, which can be the GPIO provided by the south bridge chip, or the GPIO can be expanded through logic devices such as CPLD.

[0039] In one embodiment, each slot controls GPIO to be allocated to a PCIE resource with bandwidth X8 corresponding to the CPU, for example, GPIO1 corresponds to CPU1 P4E1A / 1B, and the GPIO1 and the corresponding PCIE signal are connected to the RISER. In different embodiments, each slot controls GPIO to correspond to a CPU bandwidth X4, or other bandwidths that meet actual application scenarios.

[0040] There is a parallel-to-serial module on the RISER, which enables the BIOS to read the information of the parallel-to-serial module by connecting to the CPLD or other optional methods.

[0041] The first bit of the parallel-to-serial module corresponds to slot identification 1, and the second bit corresponds to slot identification 2. If a group of PCIE signals is actually connected to slot 1, then the corresponding slot control GPIO signal must be connected to slot identification 1. If PCIE slot 1 on the RISER corresponds to the X16 slot of P4E1A / 1B / 1C / 1D, then GPIO1 associated with P4E1A / 1B and GPIO2 associated with P4E1C / 1D must be connected to slot identification 1 of the parallel-to-serial module.

[0042] If slot 2 corresponds to slot X8 of P4E2A / 2B, and slot 3 corresponds to slot X8 of P4E2C / 2D, then GPIO3 associated with P4E2A / 2B should be connected to slot identification 2 of the parallel-to-serial module, and GPIO4 associated with P4E2C / 2D should be connected to slot identification 3 of the parallel-to-serial module. This can be applied to more slots and GPIO channels.

[0043] The above is a hardware connection relationship, where the GPIO connection pins or contacts on different RISER cards directly establish connections with the CPLD or BIOS module during installation.

[0044] When BIOS initializes PCIE configuration, it first operates the slot control GPIO. BIOS only changes the signal of one GPIO channel at a time.

[0045] In one implementation, the BIOS first changes the signal of GPIO1, and after waiting for a period of time, the BIOS reads the slot judgment register again. At this time, if the signal of slot 1 is found to have changed accordingly, it is considered that CPU1 P4E1A / 1B is connected to slot 1. The BIOS changes the signal of GPIO2, and then reads the slot judgment register. If it is found that slot 1 also presents a corresponding state, it means that CPU1 P4E1C / 1D is also connected to slot 1. In summary, the BIOS can determine that the slot number of CPU1 P4E1A / 1B / 1C / 1D is 1 and the bandwidth is X16. The BIOS changes the signal of GPIO3, and then reads the slot judgment register. If it is found that the signal of slot 2 has changed accordingly, it means that CPU1 P4E2A / 2B is connected to slot 2. The BIOS changes the signal of GPIO4, and then reads the slot judgment register. If it is found that the signal of slot 3 has changed accordingly, it means that CPU1 P4E1C / 1D is connected to slot 3. In summary, BIOS can determine that CPU1 P4E2A / 2B slot number is 2, bandwidth is X8, CPU1 P4E2C / 2D slot number is 3, bandwidth is X8. And so on, the correspondence between all slots and PCIE ports can be obtained.

[0046] In one embodiment, the present disclosure also provides a slot identification device, such as Figure 2, applied to a server, the device includes: a processing module 21, used to assign an associated PCIE port to each GPIO channel; a detection module 22, used to change the signal of the GPIO channel one by one, and obtain the association relationship between each slot and each GPIO channel according to the signal change associated with the GPIO channel signal change in the slot; a logic module 23, used to obtain the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel.

[0047] In one implementation, allocating an associated PCIE port to each GPIO channel includes: allocating an associated PCIE port to each GPIO channel according to a minimum number of PCIE ports that can be associated with a single slot.

[0048] In one embodiment, the step of changing the signals of the GPIO channels one by one and obtaining the association relationship between each slot and each GPIO channel according to the signal change in the slot that is associated with the signal change of the GPIO channel includes: obtaining that the same slot is simultaneously associated with the two GPIO channels according to the signal changes of two GPIO channels that are associated with the signal change of the same slot; and obtaining the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel includes: obtaining the association relationship between each slot and the PCIE port associated with the two GPIO channels.

[0049] In one implementation, the server includes a RISER device, the RISER device includes a plurality of slots, and the slots establish a communication connection with the BIOS module through a GPIO channel.

[0050] The device implementation is the same as or similar to the corresponding method implementation, and will not be described in detail here.

[0051] In one embodiment, the present disclosure provides an electronic device, including a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the aforementioned slot identification method. From a hardware level, the hardware architecture diagram can be seen in Figure 3 shown.

[0052] In one embodiment, the present disclosure provides a machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the aforementioned slot identification method.

[0053] Here, the machine-readable storage medium may be any electronic, magnetic, optical or other physical storage device that may contain or store information, such as executable instructions, data, etc. For example, the machine-readable storage medium may be: RAM (RadomAccess Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as CD, DVD, etc.), or similar storage medium, or a combination thereof.

[0054] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver, a game console, a tablet computer, a wearable device or a combination of any of these devices.

[0055] For the convenience of description, the above device is described in terms of functions and is divided into various units and described separately. Of course, when implementing the present disclosure, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0056] It will be appreciated by those skilled in the art that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may be provided in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the embodiments of the present disclosure may be provided in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0057] The present disclosure is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0058] Moreover, these computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0059] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0060] It will be appreciated by those skilled in the art that the embodiments of the present disclosure may be provided as methods, systems or computer program products. Therefore, the present disclosure may be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may be in the form of a computer program product implemented on one or more computer-usable storage media (which may include but are not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0061] The above description is only an embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the scope of the claims of the present disclosure.

Claims

1. A slot identification method, characterized in that: Applied to a server, the method comprises: Assign an associated PCIE port to each GPIO channel; Change the signals of the GPIO channels one by one, and obtain the correlation between each slot and each GPIO channel according to the signal change in the slot associated with the GPIO channel signal change; According to the association relationship between each slot and each GPIO channel, the association relationship between each slot and the corresponding PCIE port is obtained, and according to the association relationship between each slot and the corresponding PCIE port, the bandwidth of each slot is obtained.

2. The method according to claim 1, characterized in that The step of allocating an associated PCIE port to each GPIO channel includes: According to the minimum number of PCIE ports that can be associated with a single slot, an associated PCIE port is allocated to each GPIO channel.

3. The method according to claim 2, characterized in that The step of changing the signals of the GPIO channels one by one and acquiring the association between each slot and each GPIO channel according to the signal change in the slot associated with the signal change of the GPIO channel includes: According to the signal changes of the two GPIO channels being associated with the signal changes of the same slot, it is obtained that the same slot is associated with the two GPIO channels at the same time; The obtaining, according to the association relationship between each slot and each GPIO channel, an association relationship between each slot and a corresponding PCIE port includes: Obtain the association relationship between each slot and the PCIE port associated with the two GPIO channels.

4. The method according to claim 1, characterized in that: The server includes a RISER device, which includes a plurality of slots, and the slots establish a communication connection with a BIOS module through a GPIO channel.

5. A slot identification device, characterized in that: Applied to a server, the device comprises: A processing module, used for allocating an associated PCIE port to each GPIO channel; A detection module, used to change the signals of the GPIO channels one by one, and obtain the association relationship between each slot and each GPIO channel according to the signal change associated with the GPIO channel signal change in the slot; The logic module is used to obtain the association relationship between each slot and the corresponding PCIE port according to the association relationship between each slot and each GPIO channel, and obtain the bandwidth of each slot according to the association relationship between each slot and the corresponding PCIE port.

6. The device according to claim 5, characterized in that The step of allocating an associated PCIE port to each GPIO channel includes: According to the minimum number of PCIE ports that can be associated with a single slot, an associated PCIE port is allocated to each GPIO channel.

7. The device according to claim 6, characterized in that The step of changing the signals of the GPIO channels one by one and acquiring the association between each slot and each GPIO channel according to the signal change in the slot associated with the signal change of the GPIO channel includes: According to the signal changes of the two GPIO channels being associated with the signal changes of the same slot, it is obtained that the same slot is associated with the two GPIO channels at the same time; The obtaining, according to the association relationship between each slot and each GPIO channel, an association relationship between each slot and a corresponding PCIE port includes: Obtain the association relationship between each slot and the PCIE port associated with the two GPIO channels.

8. The device according to claim 5, characterized in that The server includes a RISER device, which includes a plurality of slots, and the slots establish a communication connection with a BIOS module through a GPIO channel.

9. An electronic device, characterized in that: include: A processor and a machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method described in any one of claims 1 to 4.

10. A machine-readable storage medium, characterized in that: The machine-readable storage medium stores machine-executable instructions, and when the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement any one of the methods of claims 1-4.

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