A method, system, device, and storage medium for formal verification

Abstract

The present invention provides a method, system, device and storage medium for formal verification. The method includes: describing template files for each working mode using general template syntax rules and creating user-defined files; in response to the user-defined files receiving working mode information, generating a corresponding formal verification framework according to the working mode; calling the template files corresponding to the working mode and storing the template files in the directory corresponding to the formal verification framework; and connecting the file relationships of the entire environment at the top layer of the formal verification environment to form an overall framework, and using the framework for formal verification. The present invention generates corresponding verification platform frameworks for different formal verification working modes, which not only improves the reusability of the verification environment while improving the verification efficiency, but also shortens the verification cycle.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and more particularly, to a method, system, device, and storage medium for formal verification. Background Art

[0002] The rapid development of technology has driven the rapid development of the chip industry. Improving verification reliability can greatly increase the probability of chip success. The current mainstream verification method is to use the UVM (Universal Verification Methodology) platform for simulation verification. This verification method uses writing direct test cases plus random constraint conditions to achieve the verification purpose. To improve verification reliability, it is also necessary to define functional coverage during the verification process and write comparison models if necessary. However, for some difficult-to-reach scenarios, it is very difficult to construct this verification method. Therefore, it is not easy to discover deeply hidden bugs (vulnerabilities). The emergence of the formal verification method can complement the simulation verification method. This verification method can control all input signals and fully randomize the input signals under the condition of satisfying the input constraints. The random combination of input signals fully ensures that all verification scenarios can be achieved, further ensuring the reliability of verification.

[0003] However, there are multiple working modes in formal verification, and the specific verification schemes for each working mode are different. For example, in the FPV (Formal Property Verification) mode, checks are performed between SVA (SystemVerilog Assertion) files and RTL (Register Transfer Level) code; in the SEQ (Equivalence Checking) mode, checks are performed between two different versions of RTL code; in the CC (Connectivity Checking) mode, checks are performed between TCL (Tool Command Language) files or CSV (Comma-Separated Values) files and RTL code. Different files need to be checked for different working modes. For formal verification, even for the same working mode, different verification engineers may have different ways of building the verification environment, resulting in disadvantages such as non-uniform formal verification platform structures and poor reusability. Moreover, when formulating a formal verification strategy, it is necessary to determine in advance the specific working mode and verification boundary required to verify the current module, consider the internal small modules in the DUT (Design Under Test) that do not need to be verified using formal verification methods, and then build the verification environment. Additionally, in the initial stage of the project, the design is unstable and the top-level ports are changed significantly. An upgrade and transformation need to be carried out on the basis of the original environment. The multiple application modes of formal verification methods correspond to multiple verification environments. If the verification environment is developed by multiple engineers, there will be multiple different code styles, and it will be very difficult to reuse the developed verification components in other projects. To solve these problems, with limited resources, enabling engineers with different experiences to quickly build a formal verification platform with a unified style for easy management and maintenance, the development of a unified and standardized formal verification platform is urgently needed by major enterprises. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present invention is to propose a method, system, computer device, and computer-readable storage medium for formal verification. The present invention can quickly generate the verification platform directory structure and generate a complete verification platform through a small number of user parameters. It also supports the selection of multiple working modes in formal verification and can generate corresponding verification platform frameworks according to the characteristics of different working modes. For some internal small modules in the design under test that do not need to be checked, users can set them to the black box mode (black_box) by setting parameters, thereby realizing the customization of the design under test hierarchy. At the same time, it can automatically generate directly usable script files according to the environment configuration for compilation and simulation.

[0005] For the above purposes, an aspect of an embodiment of the present invention provides a formal verification method, including the following steps: describing template files for each working mode using general template syntax rules, and creating user-defined files; in response to the user-defined files receiving working mode information, generating corresponding formal verification frameworks according to the working modes; calling the template files corresponding to the working modes and storing the template files in the directories corresponding to the formal verification frameworks; and connecting the file relationships of the entire environment at the top layer of the formal verification environment to form an overall framework, and using the framework for formal verification.

[0006] In some embodiments, the method further includes: generating a list of port signals of the top-level file of the verification environment and a list of port signals of the checking mechanism file according to the user-defined files.

[0007] In some embodiments, the connecting the file relationships of the entire environment at the top layer of the formal verification environment to form an overall framework includes: obtaining the path where the list of design files to be verified in the user-defined files is located and the name of the top-level module of the design to be verified, and extracting the port signals of the design to be verified as the port signals of the top-level file of the verification environment according to the path where the list of design files to be verified is located and the name of the top-level module of the design to be verified.

[0008] In some embodiments, the connecting the file relationships of the entire environment at the top layer of the formal verification environment to form an overall framework includes: using the way of hierarchical instantiation to connect all the port signals of the design to be verified with the top-level port signals of the verification environment one by one, and copying the port signals of the design to be verified to the port list of the checking mechanism file.

[0009] Another aspect of an embodiment of the present invention provides a formal verification system, including: a template module configured to describe template files for each working mode using general template syntax rules and create user-defined files; a verification module configured to generate corresponding formal verification frameworks according to the working modes in response to the user-defined files receiving working mode information; a calling module configured to call the template files corresponding to the working modes and store the template files in the directories corresponding to the formal verification frameworks; and an execution module configured to connect the file relationships of the entire environment at the top layer of the formal verification environment to form an overall framework and use the framework for formal verification.

[0010] In some embodiments, the system further includes a list module configured to: generate a list of port signals of the top-level file of the verification environment and a list of port signals of the checking mechanism file according to the user-defined files.

[0011] In some embodiments, the execution module is configured to: obtain the path where the list of design files to be verified in the user-defined file is located and the top-level module name of the design to be verified, and extract the port signals of the design to be verified as the port signals of the top-level file of the verification environment according to the path where the list of design files to be verified is located and the top-level module name of the design to be verified.

[0012] In some embodiments, the execution module is further configured to: connect all the port signals of the design to be verified to the top-level port signals of the verification environment one by one in an instance-based manner, and copy the port signals of the design to be verified to the port list of the check mechanism file.

[0013] Another aspect of the embodiments of the present invention further provides a computer device, including: at least one processor; and a memory, where the memory stores computer instructions that can be run on the processor, and when the instructions are executed by the processor, the steps of the above method are implemented.

[0014] Another aspect of the embodiments of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program that implements the steps of the above method when executed by a processor.

[0015] The present invention has the following beneficial technical effects: By reading the user-defined file, the modules that need to be set as black boxes can be flexibly set, and the hierarchy of the design to be verified can be customized, so as to quickly generate the corresponding verification platform framework. The input parameters of the user-defined file are simple, clear, and easy to understand. By reading the user-defined file, the port signal list of the top-level file of the verification environment and the port signal list of the SVA file can be automatically generated. At the same time, the script automatically completes the connection between the verification environment and the design to be verified in the form of Verilog language instantiation, and can automatically generate a directly usable script file according to the environment configuration for compilation and simulation. It is not necessary for the verification engineer to manually connect the verification environment and configure the script file. All are processed by scripts, which reduces the possibility of mistakes in the engineer's manual connection of the environment, and it is not necessary for the engineer to have more basic knowledge of formal verification. As long as the engineer simply understands the principle of formal verification and can simply use the simulation tool, the entire verification can be completed. While improving the verification efficiency, it not only improves the reusability of the verification environment, but also shortens the verification cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0017] Figure 1 Schematic diagram of an embodiment of the formal verification method provided by the present invention;

[0018] Figure 2 Formal verification flowchart;

[0019] Figure 3 Flowchart of an embodiment of the formal verification method provided by the present invention;

[0020] Figure 4 Schematic diagram of an embodiment of the formal verification system provided by the present invention;

[0021] Figure 5 Schematic diagram of the hardware structure of an embodiment of the formal verification computer device provided by the present invention;

[0022] Figure 6 Schematic diagram of an embodiment of the formal verification computer storage medium provided by the present invention. Detailed implementation manners

[0023] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further describes the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0024] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0025] In the first aspect of the embodiments of the present invention, an embodiment of a formal verification method is proposed. Figure 1 The following shows a schematic diagram of an embodiment of the formal verification method provided by the present invention. As Figure 1 shown, the embodiments of the present invention include the following steps:

[0026] S1. Describe the template files for each working mode using general template syntax rules and create user-defined files;

[0027] S2. In response to the working mode information received by the user-defined file, generate a corresponding formal verification framework according to the working mode;

[0028] S3. Call the template file corresponding to the working mode and store the template file in the directory corresponding to the formal verification framework; and

[0029] S4. Connect the file relationships of the entire environment at the top layer of the formal verification environment to form an overall framework, and use the framework for formal verification.

[0030] Formal verification is the only verification method that uses mathematical analysis to ensure the correctness of each functional point of the design under verification and to explore all possible behaviors in the design under verification in detail. Although there are dozens of working modes in formal verification, no matter which working mode it is, the general verification idea is the same. It is necessary to first determine the verification scope, evaluate the verification difficulty, understand all the functional points of the design under verification by reading the design document, and then determine the specific working mode of formal verification according to the characteristics of the design under verification. Figure 2 It is a formal verification flowchart.

[0031] Figure 2 The verification environment in it mainly includes a checker, a constraint file, an assertion file, a script file (SVA / TCL), etc. After setting up the verification environment, a formal verification simulation tool is used for compilation and simulation. There are three types of simulation results: the checker check is successful, the checker check fails, and if the checker itself is written unreasonably and the condition is not established, then the simulation result is an indeterminate state. At this time, the verification personnel need to modify the checker again and then perform compilation and simulation.

[0032] For each working mode, although the formal verification process is the same, the working principles of each mode are very different. For example, the CC mode requires the environment to input a CSV file, and the FPV mode requires the environment to input an SVA file, etc. And for modules such as register modules in the design under verification, if the verification environment does not process these modules, it not only has no verification significance but also makes the simulation speed very slow. The embodiment of the present invention can solve the problems that the verification environment is not unified due to compatibility with different working modes in formal verification, and unnecessary verification modules affect the simulation speed. Figure 3 It is a flowchart of an embodiment of the method for formal verification provided by the present invention. In combination with Figure 3 the embodiments of the present invention are described.

[0033] Describe the template files for each working mode using general template syntax rules and create user-defined files. Use general template syntax (such as Jinja2, etc.) rules to describe the templates of the files required for each working mode. The template files corresponding to the general template (such as Jinja2) syntax rules mainly contain the required environmental components and basic configurations for each working mode. Taking the FPV working mode as an example, after specifying the APP Mode as FPV in the formal.list, the script file (such as Genformal.py) will first generate the formal verification framework corresponding to the FPV mode, and then call the script file template and the check mechanism file (SVA) template of the FPV mode described by the Jinja2 syntax rules, and place the templates in the specific directory of the corresponding formal verification framework. After that, the Genformal.py script will read the formal.list. The partial format of the user-defined file formal.list is as follows. In the formal.list file, it is necessary to specify the project name, working mode (APP Mode), the path where the list of design files to be verified is located, the top module name of the design to be verified, the module names that need to be black boxed, the clock frequency, and the reset signal, etc.:

[0034] Pro Name:Project A

[0035] APP Mode:CC / FPV…

[0036] Dut Path:. / dut.sv

[0037] Top Name:dut_top

[0038] Black box Module Name:register_top

[0039] CLK Frequency:

[0040] Reset Signal Name:

[0041] In response to the working mode information received by the user-defined file, generate the corresponding formal verification framework according to the working mode. After specifying the specific working mode in the user-defined file, the script file will generate the corresponding formal verification framework for the specified working mode.

[0042] Call the template file corresponding to the working mode and store the template file in the directory corresponding to the formal verification framework.

[0043] Connect the file relationships of the entire environment at the top layer of the formal verification environment to form an overall framework, and use the framework for formal verification.

[0044] In some embodiments, the method further includes: generating a list of port signals for the top-level file of the verification environment and a list of port signals for the check mechanism file according to the user-defined file. The input parameters of the user-defined file are simple, clear, and easy to understand. By reading the user-defined file, the generation of the list of port signals for the top-level file of the verification environment and the list of port signals for the SVA file can be automatically completed.

[0045] In some embodiments, the connection of the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework includes: obtaining the path where the list of design files to be verified in the user-defined file is located and the top-level module name of the design to be verified, and extracting the port signals of the design to be verified as the port signals of the top-level file of the verification environment. The specific port signals of the design to be verified are extracted as the port signals of the top-level file of the verification environment through the two items of Dut Path (the path where the list of design files to be verified is located) and Top Name (the top-level module name of the design to be verified) in formal.list.

[0046] In some embodiments, the connection of the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework includes: using the method of hierarchical instantiation to connect all the port signals of the design to be verified with the top-level port signals of the verification environment one by one, and copying the port signals of the design to be verified to the port list of the check mechanism file. Using the method of hierarchical instantiation of Verilog language modules to connect all the port signals in the design to be verified with the top-level port signals of the verification environment one by one, and at the same time copying the port signals of the design to be verified to the port list of the SVA file for subsequent writing of assertions in the SVA file. An assertion is a first-order logic in a program (such as a logical judgment formula with a result of true or false), and its purpose is to represent the result expected by the verification software developer - when the program executes to the position of the assertion, the corresponding assertion should be true. If the assertion is not true, the program will abort and give an error message. SVA also provides many built-in functions for testing specific timing relationships and automatically collecting functional coverage data, and when an assertion fails, the simulation system will decide whether to print an error prompt message or exit the simulation process according to the severity of the failed assertion, which is convenient for locating the error position.

[0047] In the embodiments of the present invention, by reading a user-defined file, the modules that need to be set as black boxes can be flexibly set, and the hierarchy of the design to be verified can be customized, so as to quickly generate the corresponding verification platform framework. The input parameters of the user-defined file are simple, clear, and easy to understand. By reading the user-defined file, the port signal list of the top-level file of the verification environment and the port signal list of the SVA file can be automatically generated. At the same time, the script automatically completes the connection between the verification environment and the design to be verified through Verilog language instantiation, and can automatically generate a directly usable script file according to the environment configuration for compilation and simulation. It is not necessary for verification engineers to manually connect the verification environment and configure the script file. All are processed by scripts, reducing the possibility of mistakes in manual connection of the environment by engineers. And it is not necessary for engineers to have more basic knowledge of formal verification. As long as they simply understand the principle of formal verification and can use simulation tools simply, the entire verification can be completed. While improving the verification efficiency, it not only improves the reusability of the verification environment but also shortens the verification cycle.

[0048] It should be particularly noted that each step in the various embodiments of the above formal verification method can be mutually crossed, replaced, added, or deleted. Therefore, these reasonable permutation and combination transformations for the formal verification method should also fall within the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.

[0049] Based on the above purpose, in the second aspect of the embodiments of the present invention, a formal verification system is proposed. As Figure 4 shown, the system 200 includes the following modules: a template module configured to describe the template files of each working mode using general template syntax rules and create user-defined files; a verification module configured to receive working mode information in response to the user-defined file and generate a corresponding formal verification framework according to the working mode; a calling module configured to call the template file corresponding to the working mode and store the template file in the directory corresponding to the formal verification framework; and an execution module configured to connect the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework and perform formal verification using the framework.

[0050] In some embodiments, the system further includes a list module configured to: generate a port signal list of the top-level file of the verification environment and a port signal list of the check mechanism file according to the user-defined file.

[0051] In some embodiments, the execution module is configured to: obtain the path where the list of design files to be verified in the user-defined file is located and the top-level module name of the design to be verified, and extract the port signals of the design to be verified as the port signals of the top-level file of the verification environment according to the path where the list of design files to be verified is located and the top-level module name of the design to be verified.

[0052] In some embodiments, the execution module is further configured to: connect all the port signals of the design to be verified to the top-level port signals of the verification environment one by one in an instantiated manner, and copy the port signals of the design to be verified to the port list of the check mechanism file.

[0053] For the above purpose, in the third aspect of the embodiments of the present invention, a computer device is proposed, including: at least one processor; and a memory, where the memory stores computer instructions that can be run on the processor, and the instructions are executed by the processor to implement the following steps: S1. Describe the template files of each working mode using general template syntax rules and create a user-defined file; S2. In response to the user-defined file receiving working mode information, generate a corresponding formal verification framework according to the working mode; S3. Call the template file corresponding to the working mode and store the template file in the directory corresponding to the formal verification framework; and S4. Connect the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework, and use the framework for formal verification.

[0054] In some embodiments, the steps further include: generating a port signal list of the top-level file of the verification environment and a port signal list of the check mechanism file according to the user-defined file.

[0055] In some embodiments, the connecting the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework includes: obtaining the path where the list of design files to be verified in the user-defined file is located and the top-level module name of the design to be verified, and extracting the port signals of the design to be verified as the port signals of the top-level file of the verification environment according to the path where the list of design files to be verified is located and the top-level module name of the design to be verified.

[0056] In some embodiments, the connecting the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework includes: connecting all the port signals of the design to be verified to the top-level port signals of the verification environment one by one in an instantiated manner, and copying the port signals of the design to be verified to the port list of the check mechanism file.

[0057] As Figure 5 shown, it is a schematic diagram of the hardware structure of an embodiment of the above-mentioned computer device for formal verification provided by the present invention.

[0058] Taking the device shown as an example, Figure 5 the device includes a processor 301 and a memory 302.

[0059] The processor 301 and the memory 302 can be connected through a bus or other means, Figure 5 and taking the connection through the bus as an example.

[0060] As a non-volatile computer-readable storage medium, the memory 302 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the formal verification method in the embodiments of the present application. By running the non-volatile software programs, instructions, and modules stored in the memory 302, the processor 301 executes various functional applications and data processing of the server, that is, implements the formal verification method.

[0061] The memory 302 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the formal verification method, etc. In addition, the memory 302 can include high-speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 302 may optionally include a memory remotely set relative to the processor 301, and these remote memories can be connected to the local module through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0062] One or more computer instructions 303 corresponding to the formal verification method are stored in the memory 302, and when executed by the processor 301, they execute the formal verification method in any of the above method embodiments.

[0063] Any embodiment of the computer device executing the above formal verification method can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

[0064] The present invention also provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program that, when executed by a processor, executes the formal verification method.

[0065] As Figure 6 shown, it is a schematic diagram of an embodiment of the above-mentioned computer storage medium for formal verification provided by the present invention. Taking the computer storage medium shown as an example, Figure 6 the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, executes the above method.

[0066] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program of the formal verification method can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer program can achieve the same or similar effects as the corresponding foregoing method embodiments.

[0067] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any specific order. In addition, although the elements disclosed by the embodiments of the present invention can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0068] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the related listed items.

[0069] The serial numbers of the disclosed embodiments of the present invention above are only for description and do not represent the superiority or inferiority of the embodiments.

[0070] Those of ordinary skill in the art can understand that all or part of the steps of the above embodiments can be completed by hardware or by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. The storage media mentioned above can be a read-only memory, a magnetic disk, an optical disk, etc.

[0071] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features between the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for formal verification, characterized in that It includes the following steps: Describe the template files for each working mode using general template syntax rules, and create user-defined files; generate the port signal list of the top-level file of the verification environment and the port signal list of the check mechanism file according to the user-defined files; In response to the working mode information received by the user-defined file, generate a corresponding formal verification framework according to the working mode; Call the template file corresponding to the working mode and store the template file in the directory corresponding to the formal verification framework; And Connect the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework. Among them, obtain the path where the list of design files to be verified in the user-defined file is located and the top-level module name of the design to be verified, and extract the port signals of the design to be verified according to the path where the list of design files to be verified is located and the top-level module name of the design to be verified. Use instantiation to connect all the port signals of the design to be verified with the top-level port signals of the verification environment one by one, and copy the port signals of the design to be verified to the port list of the check mechanism file; And perform formal verification using the framework.

2. A formal verification system, characterized in that, It includes: A template module configured to describe the template files for each working mode using general template syntax rules, and create user-defined files; generate the port signal list of the top-level file of the verification environment and the port signal list of the check mechanism file according to the user-defined files; A verification module configured to generate a corresponding formal verification framework according to the working mode in response to the working mode information received by the user-defined file; A call module configured to call the template file corresponding to the working mode and store the template file in the directory corresponding to the formal verification framework; And An execution module configured to connect the file relationships of the entire environment at the top level of the formal verification environment to form an overall framework. Among them, obtain the path where the list of design files to be verified in the user-defined file is located and the top-level module name of the design to be verified, and extract the port signals of the design to be verified according to the path where the list of design files to be verified is located and the top-level module name of the design to be verified. Use instantiation to connect all the port signals of the design to be verified with the top-level port signals of the verification environment one by one, and copy the port signals of the design to be verified to the port list of the check mechanism file; And perform formal verification using the framework.

3. A computer device, characterized in that, It includes: At least one processor; And A memory storing computer instructions that can run on the processor, and when the instructions are executed by the processor, the steps of the method according to any one of claims 1 are implemented.

4. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 are implemented.

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