Method for testing semiconductor chips
By using different coordinates to represent the addresses of logic pages and logic blocks in semiconductor chip testing, the problem of frequent adjustments to test programs in existing technologies is solved, the reusability and scalability of test programs are realized, and development costs and cycles are reduced.
Patent Information
- Application Number
- CN202210050634.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-01-17
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2042-01-17
AI Technical Summary
Existing semiconductor chip testing methods require frequent adjustments to address rules when dealing with different products, resulting in significant changes to the testing program and a high risk of errors, which increases development difficulty and cost.
Different coordinates are used to represent the addresses of logical pages and logical blocks. By using preset address rules, the test object can be located and tested in the test program, which is applicable to a variety of semiconductor products.
It improves the reusability and scalability of test programs, and reduces the development cost and cycle of similar tests for different products.
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Figure CN114420196B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuit manufacturing, and in particular to a semiconductor chip testing method. BACKGROUND
[0002] With the development of microelectronic technology, the application range of semiconductor chips is more and more extensive, from daily life to professional field, semiconductor chip related products have penetrated into all aspects of people's life. With the development of technology, new requirements are put forward for the reliability of related products. In order to ensure the reliability of semiconductor products, reliability test, such as aging test, high and low temperature test, etc. needs to be carried out on semiconductor chips and related products before the semiconductor chips are shipped. SUMMARY
[0003] The technical problem to be solved by the present application is to provide a semiconductor chip testing method with strong multiplexing and good scalability.
[0004] The technical solution adopted by the present application to solve the above technical problem is a semiconductor chip testing method, the semiconductor chip includes at least one logic unit, each logic unit includes a plurality of logic blocks, each logic block includes a plurality of logic pages, and each logic page includes a plurality of logic columns, characterized in that it comprises: starting a test program, the test program includes a preset address rule, in the address rule, the address of the plurality of logic pages is represented by a first coordinate, the address of the plurality of logic blocks is represented by a second coordinate, and the address of the plurality of logic columns is represented by a register; reading a test file, the test file includes the address of the object to be tested; and the test program positions and tests the object to be tested according to the address rule.
[0005] In an embodiment of the present application, the first coordinate is the abscissa, and the second coordinate is the ordinate.
[0006] In an embodiment of the present application, the first coordinate includes a first number of logic page bits, and in the test file, the address of the logic page where the object to be tested is located is obtained by setting each logic page bit.
[0007] In an embodiment of the present application, the second coordinate includes a second number of logic block bits, and in the test file, the address of the logic block where the object to be tested is located is obtained by setting each logic block bit.
[0008] In an embodiment of the present application, in the address rule, the address of the plurality of logic units is also represented by the second coordinate.
[0009] In an embodiment of the present application, the second coordinate comprises a third number of logical unit bits, and in the test file, the address of the logical unit where the object to be tested is located is obtained by setting each of the logical unit bits.
[0010] In an embodiment of the present application, the register comprises a fourth number of logical column bits, and in the test file, the address of the logical column where the object to be tested is located is obtained by setting each of the logical column bits.
[0011] In an embodiment of the present application, when the actual number of logical pages of the object to be tested is greater than the first number, the address rule is updated in the test program, and the number of logical page bits in the first coordinate is equal to the actual number.
[0012] In an embodiment of the present application, the semiconductor chip is a memory chip, the logical page corresponds to a word line in the memory chip, and the logical column corresponds to a bit line in the memory chip.
[0013] In an embodiment of the present application, the test program is used for a machine for performing reliability test on the semiconductor chip.
[0014] The test method of the present application is suitable for a plurality of different semiconductor products by presetting a specific address rule in a test program and using different coordinates to represent the addresses of logical pages and logical blocks, respectively. The test program has strong expansibility, and the development cost and development cycle of different products of the same type are reduced. BRIEF DESCRIPTION OF DRAWINGS
[0015] In order to make the above objects, features and advantages of the present application more apparent, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0016] Figure 1 is an exemplary flowchart of a test method of a semiconductor chip according to an embodiment of the present application;
[0017] Figure 2 is an exemplary flowchart of a test method of a semiconductor chip according to another embodiment of the present application. DETAILED DESCRIPTION
[0018] In order to make the above objects, features and advantages of the present application more apparent, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0019] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and therefore the present application is not limited to the specific embodiments disclosed below.
[0020] As used in this application and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a" or "the" element or steps includes a single or multiple elements or steps. Similarly, terms connoting a certain spatial orientation, such as "above," "below," "up," "down," "top," and "bottom," are used herein for ease of description to describe the assumptions in the drawings. Terms of approximation, such as "approximately," "substantially," or "about," are used herein to convey an expected range of deviation as would be recognized by those of ordinary skill in the art.
[0021] In describing and claiming the present application, the following terminology will be used in accordance with the definitions set out below. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting, unless otherwise specifically indicated. It is further to be understood that any and all
[0022] Spatially relative terms, such as "beneath," "below," "lower," "under," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Well-known functions or constructions can be omitted or combined within various elements for the sake of simplicity and clarity. Furthermore, the terms "comprise," "include," "encompass," and the like used in the detailed description and the appended claims should not be construed as necessarily limited to the elements explicitly described therein. Rather, these terms can encompass one or more steps, elements, or features in addition to those explicitly set forth herein.
[0023] In the context of this application, structures described as being "on" the second feature can include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features can not be in direct contact.
[0024] In addition, it should be noted that the use of "first," "second," and the like in the description above do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, and are not intended to refer to the order of use or to characteristics of the elements other than those that are otherwise described herein. Thus, no inference should be drawn from the mere use of "first," "second," etc., in the description.
[0025] The term "three-dimensional (3D) memory device" as used herein refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of the substrate.
[0026] Flowcharts have been used herein to illustrate the operations performed by systems in accordance with embodiments of the present application. It should be understood that the operations previously or hereafter are not necessarily performed in the order shown. Rather, various steps can be processed in reverse order, or at the same time. Also, other operations can be added, or steps can be removed from these processes.
[0027] The test method of the semiconductor chip can be used for reliability testing of the semiconductor chip, and the present application does not limit the specific signals, functions, types, and structures of the semiconductor chip. The semiconductor chip includes at least one logic unit, each logic unit includes a plurality of logic blocks, each logic block includes a plurality of logic pages, and each logic page includes a plurality of logic columns.
[0028] Figure 1 is an exemplary flowchart of the test method of the semiconductor chip according to an embodiment of the present application. Referring to Figure 1 The test method of the embodiment includes the following steps:
[0029] Step S110: Start the test program, the test program includes a preset address rule, in the address rule, a first coordinate is used to represent the address of the plurality of logic pages, a second coordinate is used to represent the address of the plurality of logic blocks, and a register is used to represent the address of the plurality of logic columns;
[0030] Step S120: Read the test file, the test file includes the address of the object to be tested; and
[0031] Step S130: The test program locates and tests the object to be tested according to the address rule.
[0032] The above steps S110-S130 are described in detail as follows.
[0033] In step S110, the semiconductor chip is usually tested on a specific machine. Different test machines can be used for different test contents. The test program can be loaded into the test machine.
[0034] The test program in step S110 includes a preset address rule.
[0035] In some embodiments, the first coordinate is a horizontal coordinate and the second coordinate is a vertical coordinate. In the test program, the addresses of the logical page, logical block and logical column can be set by using X to represent the horizontal coordinate and Y to represent the vertical coordinate.
[0036] In other embodiments, the first coordinate is a vertical coordinate and the second coordinate is a horizontal coordinate.
[0037] The register in the address rule can be a type of register provided by the test machine, which can be edited and used by the user. The present application does not limit the number of the register.
[0038] Two address setting methods for semiconductor chips A and B are given below, which have different address rules from the address rule in step S110.
[0039] Address setting method for semiconductor chip A:
[0040] BBM_PAGE = _ADDR (X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10) ;
[0041] BBM_BLOCK = _ADDR (X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21) ;
[0042] BBM_LUN = _ADDR (X23).
[0043] Address setting method for semiconductor chip B:
[0044] BBM_PAGE = _ADDR (X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11) ;
[0045] BBM_BLOCK = _ADDR (X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22) ;
[0046] BBM_LUN = _ADDR (X23).
[0047] Wherein, BBM_PAGE represents the logical page, BBM_BLOCK represents the logical block, and BBM_LUN represents the logical unit.
[0048] In the address setting of semiconductor chip A, 11-bit X coordinate (X0:X10) is used to represent the address of the logical page, and semiconductor chip A can have 2 11 = 2048 logical pages; 11-bit X coordinate (X11:X21) is used to represent the address of the logical block, and semiconductor chip A can have 2 11= 2048 logical blocks; and the semiconductor chip A can have 2 1 = 2 logical units.
[0049] Similarly to the semiconductor chip A, in the address setting of the semiconductor chip B, the address of the logical page is represented by 12-bit X coordinate (X0:X11), and the semiconductor chip B can have 2 12 = 4096 logical pages; and the semiconductor chip B can have 2 11 = 2048 logical blocks; and the semiconductor chip B can have 2 1 = 2 logical units.
[0050] In the above address rules of the semiconductor chips A and B, only the X coordinate is used to set the address of the logical page, the logical block and the logical unit, and in addition, the Y coordinate is used to represent the address of the logical column. In this way, when testing, the address of the object to be tested can be known by reading the X coordinate and the Y coordinate in the test file. For example: the object to be tested is located in the 2nd logical unit (Lun 2), the 5th logical block (Block 5), the 5th logical page (Page 5), and the 1st logical column (Column 1) of the semiconductor chip A. According to the above address setting mode of the semiconductor chip A, the X coordinate and the Y coordinate in the test file are assigned as follows:
[0051] X0 = 1, X1 = 0, X2 = 1, X3 = 0;
[0052] X11 = 1, X12 = 0, X13 = 1, X14 = 0;
[0053] X23 = 0.
[0054] Y = 0.
[0055] The test program can locate the object to be tested and perform the test process according to the address rule of the semiconductor chip A by reading the test file.
[0056] However, the above address rule has the following problems:
[0057] (1) The address of logical page, logical block and logical unit is expressed by X coordinate. When the bit number of some address changes for different semiconductor chips, the related address needs to be adjusted. For example, if the address rule in the test program is the address rule of semiconductor chip A, when semiconductor chip B is to be tested, the bit number of logical page changes from 11 bits to 12 bits, and all the bit numbers in the logical page need to be changed. This causes great change of the test program and is prone to error, which may result in the failure of the whole test.
[0058] (2) Due to the above problem (1), different test programs need to be designed for different products, which increases the difficulty of development of the test program.
[0059] The present application solves the above problems by setting the address rule and using different coordinates to express the logical page and logical block in step S110.
[0060] In some embodiments, the first coordinate includes a first number of logical page bits, and in the test file, the address of the logical page where the object to be tested is located is obtained by setting each logical page bit.
[0061] In some embodiments, the second coordinate includes a second number of logical block bits, and in the test file, the address of the logical block where the object to be tested is located is obtained by setting each logical block bit.
[0062] In some embodiments, in the address rule, the address of a plurality of logical units is also expressed by the second coordinate.
[0063] In some embodiments, the second coordinate includes a third number of logical unit bits, and in the test file, the address of the logical unit where the object to be tested is located is obtained by setting each logical unit bit.
[0064] In some embodiments, the register includes a fourth number of logical column bits, and in the test file, the address of the logical column where the object to be tested is located is obtained by setting each logical column bit.
[0065] The present application does not limit the specific number of the first number, the second number, the third number and the fourth number.
[0066] The above embodiments are described by taking the first coordinate as the horizontal coordinate and the second coordinate as the vertical coordinate as an example. According to the above embodiments, the address rule in step S110 is as follows:
[0067] BBM_PAGE = _ADDR (X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11) ;
[0068] BBM_BLOCK = _ADDR (Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12) ;
[0069] BBM_LUN = _ADDR (Y13, Y14, Y15).
[0070] Wherein, 12-bit X coordinate (X0:X11) is used to represent the address of the logical page, the semiconductor chip to be tested can have 2 12 =4096 logical pages; 13-bit Y coordinate (Y0:Y12) is used to represent the address of the logical block, the semiconductor chip to be tested can have 2 13 =8192 logical blocks; 3-bit Y coordinate (Y13:Y15) is used to represent the address of the logical unit, the semiconductor chip to be tested can have 2 3 =8 logical units.
[0071] In the above embodiment, the first number is 12, the first coordinate includes 12-bit logical page bits; the second number is 13, the second coordinate includes 13-bit logical block bits; the third number is 3, and the second coordinate further includes 3-bit logical unit bits.
[0072] In the embodiment of the present application, the addresses of the logical block and the logical unit are set by using the same coordinate, and the address of the logical unit is connected after the address of the logical block.
[0073] The above address rule is only an example and is not used to limit the bit number of the first coordinate and the second coordinate in the address rule in step S110. The present application does not limit the bit number of the register.
[0074] Referring to Figure 1 Fig. 1, in step S120, a test file is read, and the test file includes the address of the object to be tested.
[0075] The present application does not limit how to read the test file. The test file can be read by using the test program in step S110. The test file is written by the tester according to the test purpose, and in addition to the address of the object to be tested, the test file can further include test content, etc., and the present application does not limit this.
[0076] In some embodiments, the test file is a file with suffix name csv.
[0077] Referring to Figure 1 Fig. 1, in step S130, the test program positions and tests the object to be tested according to the address rule.
[0078] In step S130, the test program can use the first coordinate to represent the address of the logical page of the object under test, use the second coordinate to represent the address of the logical block of the object under test, or use the second coordinate to represent the address of the logical block and the logical unit of the object under test, and use the register to represent the address of the logical column of the object under test according to the address of the object under test and the address rule, so that the test machine can be positioned to the object under test and execute the test process on the object under test.
[0079] According to the test method of the present application, the reusability of the test program is enhanced. For different products, such as the semiconductor chips A and B described above, only a small amount of adjustment is needed, the code development is simple, and the execution efficiency is high. For example, continuing the above-described embodiment, when the first number of the logical page bits of the semiconductor chip to be tested changes, only the part related to the logical page address in the address rule needs to be modified, and other parts do not need to be modified.
[0080] In some embodiments, the test method of the present application further comprises: when the actual number of the logical pages of the object under test is greater than the first number, updating the address rule in the test program, so that the number of the logical page bits in the first coordinate is equal to the actual number. Taking the above-described example as an example, assuming that the actual number of the logical pages of the object under test is 2 13 = 8192, only BBM_PAGE needs to be modified as follows:
[0081] BBM_PAGE = _ADDR(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12).
[0082] Other BBM_BLOCK and BBM_LUN do not need to be modified.
[0083] In some embodiments, the semiconductor chip involved in the test method of the present application is a memory chip, and the logical page corresponds to the word line in the memory chip, and the logical column corresponds to the bit line in the memory chip.
[0084] The present application does not limit the type of memory chip.
[0085] In some embodiments, the memory chip is a 3D NAND.
[0086] In some embodiments, the test procedure in the present application is used in a machine for performing reliability tests on semiconductor chips. The reliability tests can include aging tests, environmental reliability tests, functional reliability tests, memory cell characteristic tests, etc. Specifically, for example, single page read disturb (SPRD), block read disturb (BLRD), low temperature data retention (LTDR), low temperature operation life (LTOL).
[0087] Figure 2 is an exemplary flowchart of a test method for a semiconductor chip according to another embodiment of the present application. Figure 2 A specific example of performing a test process according to the test method of the present application is shown. Referring to Figure 2 The test method includes the following steps:
[0088] Step S210: Start the test procedure.
[0089] The test procedure is the test procedure as in step S110, including the preset address rule. Before starting the test procedure, the test procedure is loaded in the test machine.
[0090] Step S220: Determine whether there is an SPRD.csv file. If yes, perform step S230. If no, perform step S240.
[0091] The SPRD.csv file is a test file written by a test personnel, and the file name indicates that the test file is used for single page read disturb tests. The test file can include addresses of the objects to be tested, such as the addresses of the logical units, logical blocks, logical pages, logical columns, etc. of the memory cells to be tested. It can also include test sequences of a plurality of memory cells to be tested, applied voltages for read disturb, etc.
[0092] Step S230: Perform SPRD tests.
[0093] In this step, the SPRD tests are performed according to the contents of the SPRD.csv file.
[0094] Step S240: Determine whether there is a BLRD.csv file. If yes, perform step S250. If no, perform step S260.
[0095] Similar to step S220, the BLRD.csv file is a test file written by a tester, and the file name indicates that the test file is used for block read disturb test. The test file can include addresses of the object to be tested, such as logical units, logical blocks, logical pages, logical columns, and the like, in which the storage units to be tested are located. The test file can also include a test sequence of a plurality of storage units to be tested, an applied voltage for block read disturb, and the like.
[0096] Step S250: Perform other operations. The process can end.
[0097] After the test execution in step S230 and step S250 ends, the process can end, or the test file can be read continuously to perform the next test.
[0098] According to the test method of the present application, for different semiconductor products, the pin format can be uniformly coded according to the set address rule, and the pin correspondence relationship is unified, so that one test program can be applied to a plurality of different semiconductor products. Moreover, the test program has strong expansibility, and the development cost and development cycle of different products and the same type of test are reduced.
[0099] Although the present application has been described with reference to the current specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or replacements can be made without departing from the spirit of the present application, therefore, any changes or modifications of the above embodiments within the scope of the spirit of the present application will fall within the scope of the claims of the present application.
Claims
1. A method of testing a semiconductor chip, said semiconductor chip comprising at least one logic unit, each of said logic units comprising a plurality of logic blocks, each of said logic blocks comprising a plurality of logic pages, each of said logic pages comprising a plurality of logic columns, characterized by, The application relates to a method for testing a semiconductor chip, comprising: starting a test program, wherein the test program comprises a preset address rule, in which a first coordinate represents an address of a plurality of logical pages, a second coordinate represents an address of a plurality of logical blocks, and a register represents an address of a plurality of logical columns; reading a test file, wherein the test file comprises an address of an object to be tested; and locating and testing the object to be tested according to the address rule.
2. The test method of claim 1, wherein, The first coordinate is a horizontal coordinate, and the second coordinate is a vertical coordinate.
3. The test method of claim 1, wherein, The first coordinate comprises a first number of logical page bits, and in the test file, the address of a logical page where the object to be tested is located is obtained by setting each logical page bit.
4. The test method of claim 1, wherein, The second coordinate comprises a second number of logical block bits, and in the test file, the address of a logical block where the object to be tested is located is obtained by setting each logical block bit.
5. The test method of claim 1, wherein, In the address rule, the address of the plurality of logical units is also represented by the second coordinate.
6. The test method of claim 5, wherein, The second coordinate comprises a third number of logical unit bits, and in the test file, the address of a logical unit where the object to be tested is located is obtained by setting each logical unit bit.
7. The test method of claim 1, wherein, The register comprises a fourth number of logical column bits, and in the test file, the address of a logical column where the object to be tested is located is obtained by setting each logical column bit.
8. The test method of claim 3, wherein, The application further relates to a method for testing a semiconductor chip, comprising: when an actual number of logical pages of the object to be tested is greater than the first number, updating the address rule in the test program, so that the number of logical page bits in the first coordinate is equal to the actual number.
9. The test method of claim 1, wherein, The semiconductor chip is a memory chip, the logical page corresponds to a word line in the memory chip, and the logical column corresponds to a bit line in the memory chip.
10. The test method of claim 1, wherein, The test program is used for a machine for performing a reliability test on the semiconductor chip.
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