Semiconductor structure and method of manufacturing the same, memory, storage system, electronic device

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, a memory, a storage system and an electronic device, and relates to the technical field of semiconductor chips, so as to reduce mutual interference between storage units and improve device performance. The semiconductor structure comprises a stack layer, a first isolation structure, a second isolation structure and a channel structure penetrating the stack layer. The stack layer comprises a plurality of first dielectric layers and a plurality of gate line layers alternately stacked. The first isolation structure extends along a first direction to divide the gate line layers into a plurality of gate lines. The second isolation structure extends along the first direction to separate the gate lines into at least two sub-gate lines; the dielectric constant of the second isolation structure is less than that of the first dielectric layer. At least part of the channel structure is located on a straight line where the second isolation structure is located, and the sub-gate lines on both sides of the second isolation structure are respectively in contact with the channel structure. The above semiconductor structure is applied to a memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its preparation method, a memory, a storage system, and an electronic device. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] However, in order to increase storage density, memory sizes are getting smaller and smaller. During programming operations, the mutual interference between memory cells is difficult to ignore, affecting device performance. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, a memory, a storage system, and an electronic device to reduce mutual interference between storage cells and improve device performance.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a semiconductor structure is provided. The semiconductor structure includes a stacked layer, and a first isolation structure, a second isolation structure, and a channel structure extending through the stacked layer. The stacked layer includes a plurality of alternately stacked first dielectric layers and a plurality of gate line layers. The first isolation structure extends along a first direction to divide the gate line layers into a plurality of gate lines. The second isolation structure extends along the first direction to divide the gate lines into at least two sub-gate lines; the dielectric constant of the second isolation structure is less than the dielectric constant of the first dielectric layers. The channel structure is disposed between two adjacent first isolation structures; at least a portion of the channel structure is located on the straight line containing the second isolation structure, and the sub-gate lines on both sides of the second isolation structure respectively contact the channel structure located on the straight line containing the second isolation structure.

[0008] In the semiconductor structure provided by the above embodiments of this disclosure, the second isolation structure divides the gate line into multiple sub-gate lines. The channel structure is located on the straight line where the second isolation structure is located, and the sub-gate lines on both sides of the second isolation structure where the channel structure is located are in contact with the channel structure. That is, in the plane where the gate line layer is located, one channel structure is in contact with two sub-gate lines respectively to form two transistors arranged opposite each other. In this case, a memory cell string can include more memory cells, which can increase the storage density of the semiconductor structure without increasing the total number of stacked layers.

[0009] Furthermore, the dielectric constant of the second isolation structure is lower than that of the first dielectric layer. In other words, the second isolation structure can be made of a material with a lower dielectric constant to reduce the electric field coupling between two transistors positioned opposite each other on the plane of the gate layer within the same memory cell string, and to reduce interference between adjacent gate layers in the direction perpendicular to the plane of the gate layer, thereby improving device performance.

[0010] In some embodiments, along the first direction, the second isolation structure penetrates a corresponding row of channel structures to divide the channel structure into a first sub-channel structure and a second sub-channel structure, wherein the first sub-channel structure contacts a first sub-gate line and the second sub-channel structure contacts a second sub-gate line.

[0011] In some embodiments, along the first direction, the second isolation structure contacts the outer surface of a corresponding row of channel structures.

[0012] In some embodiments, the semiconductor structure further includes a third isolation structure that extends through the stacked layers, the third isolation structure being located between two adjacent second isolation structures.

[0013] In some embodiments, the dielectric constant of the second isolation structure is less than or equal to 3.

[0014] In some embodiments, the material of the second isolation structure includes any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

[0015] In some embodiments, along a second direction, the size of the second isolation structure is smaller than the diameter of the channel structure, the second direction is perpendicular to the first direction and parallel to the plane of the stacked layers.

[0016] In some embodiments, the first dielectric layer is recessed near the boundary of the channel structure compared to the boundary of the sub-gate line near the channel structure. The semiconductor structure further includes a plurality of second dielectric layers. Along a direction parallel to the plane of the stacked layers, the second dielectric layers are located between the first dielectric layer and the channel structure; along a direction perpendicular to the plane of the stacked layers, the second dielectric layers are located between two adjacent gate layers, and the dielectric constant of the second dielectric layers is less than that of the first dielectric layer.

[0017] In some embodiments, one side of the second dielectric layer is in contact with the first dielectric layer, and the other side is in contact with the channel structure.

[0018] On the other hand, a method for fabricating a semiconductor structure is provided, comprising: fabricating an intermediate semiconductor structure; the intermediate semiconductor structure includes a stacked layer, a first isolation structure and a channel structure penetrating the stacked layer; the stacked layer includes a plurality of alternately stacked first dielectric layers and a plurality of gate line layers, the first isolation structure extending along a first direction to divide the gate line layers into a plurality of gate lines, and the channel structure being located between two adjacent first isolation structures; forming a second isolation structure penetrating the stacked layer, the second isolation structure extending along the first direction to divide the gate lines into at least two sub-gate lines; the dielectric constant of the second isolation structure is less than the dielectric constant of the first dielectric layer; at least a portion of the channel structure is in contact with one of the second isolation structures and in contact with two of the sub-gate lines in the plane direction of the gate line layers.

[0019] In some embodiments, forming a second isolation structure penetrating the stacked layers includes: etching the stacked layers to form a second gap; the second gap extending along the first direction to divide the gate line into sub-gate lines and the channel structure into a first sub-channel structure and a second sub-channel structure. A target material is filled within the second gap to form the second isolation structure; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer.

[0020] In some embodiments, the fabrication of the intermediate semiconductor structure includes: forming an initial stacked layer; the initial stacked layer including a plurality of sacrificial layers and a plurality of first dielectric layers alternately disposed; forming a channel via through the initial stacked layer; forming a channel structure within the channel via; forming a first gap through the initial stacked layer; replacing the sacrificial layers with gate layers via the first gap; and forming a first isolation structure within the first gap.

[0021] In some embodiments, between forming the channel hole and forming the channel structure, the fabrication method further includes: removing an edge portion of the first dielectric layer near the channel hole via the channel hole, such that the first dielectric layer near the boundary of the channel hole is recessed relative to the boundary of the sacrificial layer near the channel hole to form a groove. A second dielectric layer is formed within the groove; the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.

[0022] In some embodiments, forming the second dielectric layer within the groove includes: depositing a target material to form a second dielectric film; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer; and removing portions of the second dielectric film covering the initial stacked layer and the portion covering the inner wall of the channel hole to form the second dielectric layer.

[0023] In another aspect, a method for fabricating a semiconductor structure is provided, comprising: forming an initial stacked layer; the initial stacked layer comprising a plurality of sacrificial layers and a plurality of first dielectric layers alternately disposed; forming a second isolation structure penetrating the initial stacked layer; the second isolation structure extending along a first direction to divide the sacrificial layers into a plurality of sub-sacrificial layers; the dielectric constant of the second isolation structure being less than the dielectric constant of the first dielectric layers; forming a channel via penetrating the initial stacked layer, and forming a channel structure within the channel via; at least a portion of the channel structure contacting one of the second isolation structures, and contacting two of the sub-sacrificial layers in the plane direction of the sacrificial layers.

[0024] In some embodiments, forming a second isolation structure through the initial stacked layer includes: forming a second gap through the initial stacked layer; the second gap extending along the first direction to divide the sacrificial layer into a plurality of sub-sacrificial layers; and filling the second gap with a target material; the dielectric constant of the target material being less than that of the material of the first dielectric layer.

[0025] In some embodiments, after forming the channel structure, the fabrication method further includes: forming a first slot and a third slot penetrating the initial stacked layer; the first slot and the third slot extending along a first direction, the first slot located on both sides of the arrayed channel structure, and the third slot located between two adjacent rows of the channel structure. The sacrificial layer is replaced with a gate line layer via the first slot and the third slot. A first isolation structure and a third isolation structure are formed within the first slot and the third slot, respectively.

[0026] In some embodiments, between forming the channel hole and forming the channel structure, the fabrication method further includes: removing an edge portion of the first dielectric layer near the channel hole via the channel hole, such that the first dielectric layer near the boundary of the channel hole is recessed relative to the boundary of the sacrificial layer near the channel hole to form a groove. A second dielectric layer is formed within the groove; the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.

[0027] In some embodiments, forming the second dielectric layer within the groove includes: depositing a target material to form a second dielectric film; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer; and removing portions of the second dielectric film covering the initial stacked layer and the portion covering the inner wall of the channel hole to form the second dielectric layer.

[0028] In another aspect, a memory is provided. The memory includes a semiconductor structure as described in some of the embodiments above, and peripheral devices electrically connected to the semiconductor structure.

[0029] In another aspect, a storage system is provided, comprising: a memory as described above, and a controller coupled to the memory to control the memory to store data.

[0030] In another aspect, an electronic device is provided, characterized in that it includes the storage system described above.

[0031] It is understood that the beneficial effects that the semiconductor structure preparation method, memory, storage system and electronic device provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure in the above text, and will not be repeated here. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0033] Figure 1 A cross-sectional view of a memory according to some embodiments;

[0034] Figure 2 for Figure 1 A cross-sectional view of a string of memory cells in the memory shown;

[0035] Figure 3 for Figure 2 Equivalent circuit diagram of the memory cell string;

[0036] Figure 4 This is a top view of a semiconductor structure according to some embodiments;

[0037] Figure 5 A top view of a semiconductor structure according to some other embodiments;

[0038] Figure 6 for Figure 4 A sectional view along section line AA';

[0039] Figures 7-18 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0040] Figures 19-23 This is a diagram illustrating the fabrication steps of a method for fabricating a semiconductor structure according to some other embodiments;

[0041] Figures 24-30 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0042] Figures 31-37 This is a flowchart of a method for fabricating a semiconductor structure according to some other embodiments;

[0043] Figure 38 This is a block diagram of a storage system according to some embodiments;

[0044] Figure 39 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0045] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0046] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0049] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0050] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0051] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0052] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0053] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0055] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0056] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0058] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0059] Figure 1 A cross-sectional view of a memory provided in some embodiments of this disclosure. Figure 2 for Figure 1 The diagram shows a cross-sectional view of a string of memory cells in the memory. Figure 3 for Figure 2 Equivalent circuit diagram of the storage cell string.

[0060] See Figure 1 Some embodiments of this disclosure provide a memory 10. The memory 10 may include a semiconductor structure 200. The memory 10 may also include a source layer SL coupled to the semiconductor structure 200, and peripheral devices 100 coupled to the semiconductor structure 200. The peripheral devices 100 may be disposed on the side of the semiconductor structure 200 away from the source layer SL.

[0061] The source layer SL can be made of semiconductor materials, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL can be partially or completely doped. For example, the source layer SL can include doped regions doped with p-type dopant. The source layer SL can also include undoped regions.

[0062] See Figure 1 and Figure 2 The semiconductor structure 200 may include arrays of memory cell transistor strings 400 (referred to herein as “memory cell strings”, such as NAND memory cell strings). A source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0063] Specifically, see Figure 2 and Figure 3 The storage cell string 400 may include multiple transistors T, one transistor T (e.g. Figure 3 Transistors T1 to T12 can be configured as a memory cell, and these transistors T are connected together to form a memory cell string 400. A transistor T (e.g., each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor T.

[0064] It should be noted that, Figures 1-3 The number of transistors is only illustrative. The memory cell string provided in the embodiments of this disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0065] Further, along the third direction Z, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as source selection gates SGS1 and SGS2. Source selection gate SGS1 is configured to control the conduction state of transistor T6, thereby controlling the conduction state of one source channel in the memory cell string 400; source selection gate SGS2 is configured to control the conduction state of transistor T12, thereby controlling the conduction state of another source channel in the memory cell string 400. The uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as drain selection gates SGD1 and SGD2. Drain selection gate SGD1 is configured to control the conduction state of transistor T1, thereby controlling the conduction state of one drain channel in the memory cell string 400; drain selection gate SGD2 is configured to control the conduction state of transistor T7, thereby controlling the conduction state of another drain channel in the memory cell string 400. The middle gate line among multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be accomplished.

[0066] It should be noted that the memory 10 extends in the XY plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0067] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a memory) is determined relative to the substrate or source layer of the semiconductor device in the third direction Z, when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concepts are applied throughout this disclosure to describe spatial relationships.

[0068] See also Figure 1 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0069] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT coupled to bit lines; and drain select gate contacts coupled to drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of interconnect lines, such as bit lines, and word line interconnect lines coupled to word lines WL. The materials of the first interconnect conductor layers 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and one or more combinations of metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, or other suitable materials.

[0070] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0071] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include the transistor 120.

[0072] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0073] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0074] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuits in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 100 to achieve the transmission of electrical signals between the peripheral circuits and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, through which the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other.

[0075] To increase storage density, the size of the memory 10 is becoming smaller, and the distance between the individual transistors T in the memory cell string 400 is also decreasing. In this case, when programming the transistor T, due to electric field coupling, the threshold voltage of other transistors T adjacent to the transistor T being programmed in the same memory cell string 400 will increase, thereby affecting device performance.

[0076] Based on this, in some embodiments, such as Figure 4 and Figure 6 As shown, the semiconductor structure 200 includes a stacked layer 210, a first isolation structure 220, a second isolation structure 230, and a channel structure 240 that penetrate the stacked layer 210.

[0077] Combination Figure 4 and Figure 6 The stacked layer 210 can be disposed on the source layer SL, that is, the stacked layer 210 is located in the thickness direction of the source layer SL (i.e., Figure 6 The stacked layer 210 includes a plurality of first dielectric layers 211 and a plurality of gate line layers 212, which are stacked alternately along the third direction Z.

[0078] It should be noted that the material of the first dielectric layer 211 may include insulating materials, including at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0079] The gate layer 212 may include a conductor layer 2121, and the material of the conductor layer 2121 may include a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

[0080] In some embodiments, such as Figure 6 As shown, the gate layer 212 may further include a metal compound layer 2122, which is located between the conductor layer 2121, the channel structure 240, and the first dielectric layer 211. The metal compound layer 2122 is configured as an adhesive layer to improve the adhesion between the conductor layer 2121 and the first dielectric layer 211. The material of the metal compound layer 2122 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0081] In some embodiments, such as Figure 6 As shown, the gate layer 212 may further include a high dielectric constant layer 2123, which is located between the metal compound layer 2122, the channel structure 240, and the first dielectric layer 211 to reduce the risk of charge flowing from the channel structure 240 to the conductor layer. The dielectric constant of the high dielectric constant layer 2123 is greater than or equal to 7. Exemplarily, the material of the high dielectric constant layer 2123 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0082] In some embodiments, the stacked layer 210 is in contact with the source layer SL. In other embodiments, other functional layers are also disposed between the stacked layer 210 and the source layer SL. For example, a semiconductor layer 281 and a third dielectric layer 282 are also disposed between the stacked layer 210 and the source layer SL, with the semiconductor layer 281 in contact with the stacked layer 210 and the third dielectric layer 282 in contact with the source layer SL. The layer of the stacked layer 210 closest to the source layer SL may be the first dielectric layer 211.

[0083] It should be noted that the material of semiconductor layer 281 includes semiconductor materials, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The material of third dielectric layer 282 includes insulating materials, which may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0084] The embodiments disclosed herein do not limit the number of stacked layers 210. For example, the number of stacked layers 210 can be 8, 64, 128, etc. It is understood that the more stacked layers 210 there are, the higher the integration density, and the more transistors T are in the memory cell string 400 formed by them.

[0085] like Figure 4 and Figure 6 As shown, the first isolation structure 220 extends along the first direction X and penetrates the stacked layer 210 to divide the gate line layer 212 into multiple gate lines G. The first isolation structure 220 includes an insulating isolation portion 221, which contacts the first dielectric layer 211 and the side surfaces of the gate line layer 212. It should be noted that the material of the gate line filling layer 222 can be an insulating material, which may include at least one of silicon oxide, silicon nitride, and high dielectric constant insulating materials; this disclosure is not limited thereto.

[0086] In some embodiments, such as Figure 6 As shown, the first isolation structure 220 may further include a gate line filling layer 222. The insulating isolation portion 221 contacts the side of the first dielectric layer 211 and the gate line layer 212, and a cavity is left inside the insulating isolation portion 221. The gate line filling layer 222 fills the cavity to provide mechanical support. It should be noted that the material of the gate line filling layer 222 can be a conductive material or an insulating material, and this disclosure does not specifically limit it.

[0087] like Figure 4 and Figure 6 As shown, the second isolation structure 230 extends along the first direction X and penetrates the stacked layer 210 to separate the gate line G into at least two sub-gate lines G1. The dielectric constant of the second isolation structure 230 is less than the dielectric constant of the first dielectric layer 211.

[0088] like Figure 4 and Figure 6 As shown, the channel structure 240 penetrates the stack layer 210 and is arranged between two adjacent first isolation structures 220. In addition, at least a portion of the channel structure 240 is located on the straight line of the second isolation structure 230, and the sub-gate lines G1 on both sides of the second isolation structure 230 respectively contact the channel structure 240 located on the straight line of the second isolation structure 230.

[0089] It should be noted that when the stacked layer 210 can be disposed on the source layer SL, and a semiconductor layer and a third dielectric layer are disposed between the stacked layer 210 and the source layer SL, the channel structure 240 also penetrates the semiconductor layer and the third dielectric layer, so that the channel structure 240 can be coupled to the source layer SL.

[0090] In some embodiments, see Figure 6 The channel structure 240 includes a storage function layer 241 and a semiconductor channel layer 242. One side of the storage function layer 241 is in contact with the side of the first dielectric layer 211 and the gate line layer 212, and the other side is in contact with the semiconductor channel layer 242. That is, the storage function layer 241 is located between the semiconductor channel layer 242 and the first dielectric layer 211 and the gate line layer 212.

[0091] It should be noted that the material of the semiconductor channel layer 242 includes semiconductor materials, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0092] The storage functional layer 241 includes a barrier layer 2411, a charge trapping layer 2412, and a tunneling layer 2413. The materials of the barrier layer 2411, the charge trapping layer 2412, the tunneling layer 2413, and the semiconductor channel layer 242 can be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, to form a "SONO" structure.

[0093] In some embodiments, such as Figure 6 As shown, the channel structure 240 also includes a channel filling layer 243, which is disposed on the side of the semiconductor channel layer 242 away from the storage function layer 241 to provide mechanical support. It should be noted that the material of the channel filling layer 243 includes an insulating material, which may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0094] As described above, the second isolation structure 230 divides the gate line G into multiple sub-gate lines G1. The channel structure 240 is located on the straight line of the second isolation structure 230, and the sub-gate lines G1 located on both sides of the second isolation structure 230 are in contact with the channel structure 240. That is, in the plane (XY plane) where the gate line layer 212 is located, one channel structure 240 is in contact with two sub-gate lines G1 respectively to form two oppositely arranged transistors T. In this case, a memory cell string 400 can include more memory cells, thus increasing the storage density of the semiconductor structure 200 without increasing the total number of stacked layers 210.

[0095] Furthermore, the dielectric constant of the second isolation structure 230 is lower than that of the first dielectric layer 211. That is, the second isolation structure 230 can be made of a material with a lower dielectric constant to reduce the electric field coupling between two transistors T arranged opposite each other in the XY plane within the same memory cell string 400, and to reduce the electric field coupling in the direction perpendicular to the plane containing the gate layer 212. Figure 1 In the Z-direction, interference between adjacent gate line layers 212 is reduced, thereby improving device performance.

[0096] For example, the dielectric constant of the second isolation structure 230 is less than or equal to 3. For instance, the material of the second isolation structure 230 may include either carbon-doped silicon hydroxide or fluorine-doped silicon oxide.

[0097] In some embodiments, such as Figure 4 and Figure 6 As shown, along the first direction X, the second isolation structure 230 penetrates the corresponding row of channel structures 240 to divide the channel structure 240 into a first sub-channel structure 244 and a second sub-channel structure 245. The first sub-channel structure 244 contacts the first sub-gate line, and the second sub-channel structure 245 contacts the second sub-gate line. In this case, two transistors T (see [reference]) are arranged opposite each other on the XY plane. Figure 3 The corresponding channel structure 240 separation can reduce the risk of leakage current.

[0098] In this context, along the second direction Y, the size of the second isolation structure 230 is smaller than the diameter of the channel structure 240. The second direction Y is perpendicular to the first direction X and parallel to the plane (XY plane) where the stacked layer 210 is located.

[0099] In other embodiments, such as Figure 5 As shown, along the first direction X, the second isolation structure 230 contacts the outer surface of the corresponding row channel structure 240, which can also improve the storage density of the semiconductor structure 200.

[0100] In this context, along the second direction Y, the size of the second isolation structure 230 is smaller than the diameter of the channel structure 240. The second direction Y is perpendicular to the first direction X and parallel to the plane (XY plane) where the stacked layer 210 is located.

[0101] like Figure 5 As shown, when the second isolation structure 230 is in contact with the outer surface of the corresponding row channel structure 240, the semiconductor structure 200 also includes a through-layer stack 210 (see...). Figure 23 The third isolation structure 250 is located between two adjacent second isolation structures 230 to ensure that the sub-gate line G1 between the two adjacent second isolation structures 230 can be formed by a replacement process.

[0102] Among them, see Figure 5 and Figure 23 The material of the third isolation structure 250 may be the same as or different from that of the first isolation structure 220. This disclosure does not make any specific limitation.

[0103] It should be noted that the third isolation structure 250 can be formed in the same process as the first isolation structure 220. For example, the first isolation structure 220 and the third isolation structure 250 can be formed by one etching and one filling process. For details, please refer to the following text. This disclosure will not elaborate further here.

[0104] In some embodiments, see Figure 6 The first dielectric layer 211 is located near the edge of the channel structure 240, compared to the gate line layer 212 (which could also be...). Figure 4 or Figure 5 The sub-gate line G1 in the middle is recessed near the edge of the channel structure 240, along a direction parallel to the plane of the stacked layer 210 (i.e., Figure 4 The plane defined by XY).

[0105] Based on this, such as Figure 6 As shown, the semiconductor structure 200 further includes a second dielectric layer 260, which is located between the first dielectric layer 211 and the channel structure 240. The dielectric constant of the second dielectric layer 260 is less than that of the first dielectric layer 211. Here, the material of the second dielectric layer 260 can be the same as the material of the second isolation structure 230, or it can be different from the material of the second isolation structure 230.

[0106] Therefore, the first dielectric layer 211 and the second dielectric layer 260 can be made of different materials. In other words, the first dielectric layer 211 and the second dielectric layer 260 can each be made of suitable materials according to their respective design requirements, resulting in lower costs.

[0107] For example, the first dielectric layer 211 can be made of a material with a high elastic modulus to support the stacked layers 210. The dielectric constant of the first dielectric layer 211 does not need to be too high; thus, a wider variety of materials can be selected for the first dielectric layer 211, resulting in lower cost. The second dielectric layer 260 can be made of a material with a low dielectric constant to reduce the electric field coupling between adjacent transistors T in the third direction Z within the same memory cell string 400, thereby improving device performance. The elastic modulus of the second dielectric layer 260 does not need to be too low; thus, a wider variety of materials can be selected for the second dielectric layer 260, resulting in lower cost.

[0108] For example, the dielectric constant of the second dielectric layer 260 is less than or equal to 3. Specifically, the material of the second dielectric layer 260 may include either carbon-doped silicon hydroxide or fluorine-doped silicon oxide. In this case, the elastic modulus of the second dielectric layer 260 is less than that of the first dielectric layer 211.

[0109] For example, the elastic modulus of the first dielectric layer 211 is greater than that of the second dielectric layer 260 to improve the structural stability of the stacked layer 210 and reduce the risk of the stacked layer 210 tilting. The elastic modulus of the first dielectric layer 211 can be between 70 GPa and 100 GPa. Specifically, the material of the first dielectric layer 211 can be silicon dioxide. In this case, the dielectric constant of the first dielectric layer 211 is 3.9.

[0110] In some embodiments, such as Figure 6 As shown, one side of the second dielectric layer 260 is in contact with the first dielectric layer 211, and the other side is in contact with the channel structure 240. That is, the second dielectric layer 260 fills the gap between the first dielectric layer 211 and the channel structure 22, avoiding the problem of short circuits between different gate layers 212 during the fabrication of the semiconductor structure 200, especially during the replacement of the gate layer 212.

[0111] In some embodiments, such as Figure 6 As shown, the second dielectric layer 260 is far from the boundary of the first dielectric layer 211 and flush with the boundary of the gate line layer 212 near the channel structure 240, so that a second dielectric layer 260 with a low dielectric constant is provided between the edge portions of different gate line layers 212 near the channel structure 240, thereby minimizing the electric field coupling effect between transistors T in the same memory cell string 400 and improving device performance.

[0112] The second dielectric layer 260 is located near the boundary of the first dielectric layer 211, and the distance between the second dielectric layer 260 and the boundary of the second dielectric layer 260 away from the first dielectric layer 211 is 0.5 nm to 5 nm. This avoids the risk of the stacked layer 210 tipping over due to the size of the second dielectric layer 260 being too large, and also avoids the risk of the second dielectric layer 260 being too small, which would prevent the electric field coupling between transistors T in the same memory cell string 400 from being reduced to the preset requirements. For example, the distance between the boundary of the second dielectric layer 260 near the boundary of the first dielectric layer 211 and the boundary of the second dielectric layer 260 away from the first dielectric layer 211 is any one of 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, and 5 nm.

[0113] In some embodiments, such as Figure 6 As shown, the semiconductor structure 200 may also include a virtual channel structure 270.

[0114] The virtual channel structure 270 penetrates the stacked layer 210 and is configured to provide mechanical support for the semiconductor structure 200. It should be noted that the virtual channel structure 270 can be penetrated and divided by the second isolation structure 230, or it can bypass the second isolation structure 230, i.e., the virtual channel structure 270 and the second isolation structure 230 are staggered; this disclosure does not specifically limit this. Furthermore, the virtual channel structure 270 may include an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high-dielectric-constant insulating materials, or other suitable materials. Additionally, the virtual channel structure 270 may include one or more air gaps to reduce structural stress.

[0115] In some embodiments, see Figure 6 The semiconductor structure 200 may further include a capping layer 280. The capping layer 280 may cover the stacked layer 210 to protect the semiconductor structure 200. The material of the capping layer 280 may include an insulating material, which may include at least one of silicon oxide, silicon nitride, and high dielectric constant insulating materials, but this disclosure is not limited thereto.

[0116] It should be noted that the surface of the cover layer 280 away from the stacked layer 210 needs to be treated with a chemical mechanical polishing process to make the surface of the cover layer 280 away from the stacked layer 210 completely planarized.

[0117] Embodiments of this disclosure also provide a method for fabricating a semiconductor structure 200, such as... Figure 24 As shown, the preparation method includes steps S100 to S200.

[0118] S100: See also Figure 16 , Prepare intermediate semiconductor structure 200'.

[0119] In the above steps, the intermediate semiconductor structure 200' includes a stacked layer 210, a first isolation structure 220 penetrating the stacked layer 210, and a channel structure 240. The stacked layer 210 includes a plurality of alternately stacked first dielectric layers 211 and a plurality of gate line layers 212, combined with... Figure 4 The first isolation structure 220 extends along the first direction X to divide the gate line layer 212 into multiple gate lines G, and the channel structure 240 is located between two adjacent first isolation structures 220.

[0120] It should be noted that the specific process for preparing the intermediate semiconductor structure 200' can be found in S110 to S160, and will not be elaborated here.

[0121] S200: See also Figure 18 This forms a second isolation structure 230 that penetrates the stacked layer 210.

[0122] In the above steps, such as Figure 4 and Figure 18 The second isolation structure 230 extends along the first direction X to divide the gate line G into at least two sub-gate lines G1. The dielectric constant of the second isolation structure 230 is less than the dielectric constant of the first dielectric layer 211. At least a portion of the channel structure 240 contacts one of the second isolation structures 230 and contacts both sub-gate lines G1 in the plane direction of the gate line layer 212.

[0123] In some embodiments, see Figure 25 S200 includes S210 to S220.

[0124] S210: See also Figure 17 The stacked layer 210 is etched to form the second gap GLS2.

[0125] In the above steps, refer to Figure 4 and Figure 17 The second slit GLS2 extends along the first direction X to divide the gate line G into sub-gate lines G1 and the channel structure 240 into a first sub-channel structure 244 and a second sub-channel structure 245.

[0126] In the above steps, a second gap GLS2 penetrating the stacked layer 210 can be formed by a dry / wet etching process. For example, a photoresist layer is formed on the upper surface of the stacked layer 210, and using this photoresist layer as a mask, an anisotropic etching process (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation) is employed to form the second gap GLS2.

[0127] S220: See also Figure 17 and Figure 18 The target material is filled into the second gap GLS2 to form the second isolation structure 230.

[0128] In the above steps, the dielectric constant of the target material is less than that of the material of the first dielectric layer 211. Specifically, any thin film deposition process among CVD, PVD, and ALD can be used to deposit the target material. The target material is the material of the second isolation structure 230, as detailed above, and will not be repeated here.

[0129] It should be noted that if a photoresist layer is formed on the upper surface of the stacked layer 210, the photoresist layer needs to be removed after the second isolation structure 230 is formed.

[0130] In some embodiments, such as Figure 26 As shown, S100 includes S110 to S160.

[0131] S110: As Figure 7 As shown, an initial stacking layer 210' is formed.

[0132] In the above steps, the initial stacked layer 210' includes a plurality of alternating first dielectric layers 211 and a plurality of sacrificial layers 212'. The initial stacked layer 210' can be formed on the substrate 300 using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0133] It should be noted that the material of the first dielectric layer 211 can be referred to above and will not be repeated here. The material of the sacrificial layer 212' includes at least one of polycrystalline silicon, silicon nitride, and polycrystalline germanium, and this disclosure is not limited thereto. Here, the material of the first dielectric layer 211 is different from the material of the sacrificial layer 212', so that the first dielectric layer 211 and the sacrificial layer 212' have different etching selectivity ratios for the same etchant. For example, the material of the first dielectric layer 211 is silicon dioxide, and the material of the sacrificial layer 212' is silicon nitride.

[0134] The substrate 300 can be used to support the initial stacked layer 210' thereon, which can be removed in subsequent processes, as detailed below. The material of the substrate 300 includes at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0135] In some embodiments, such as Figure 7 As shown, substrate 300 may be a composite substrate. Exemplarily, substrate 300 may include a base 310, and a sacrificial silicon oxide layer 320 and a sacrificial polysilicon layer 330 sequentially formed on the base 310. The material of the base 310 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, group III-V compound semiconductor materials, group IIVI compound semiconductor materials, or other semiconductor materials known in the art; the material of the sacrificial silicon oxide layer 320 may include silicon oxide; and the material of the sacrificial polysilicon layer 330 may include polysilicon.

[0136] S120: As Figure 8 As shown, a channel hole CH is formed that penetrates the initial stacked layer 210'.

[0137] In the above steps, a channel hole CH penetrating the initial stacked layer 210' can be formed using a dry / wet etching process. Exemplarily, an anisotropic etching process (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation) is used to form the channel hole CH. The channel hole CH extends into the substrate 300; for example, the substrate 300 is a composite substrate, and the channel hole CH extends into the sacrificial polysilicon layer 330.

[0138] S130: As Figure 8 and Figure 12 As shown, a channel structure 240 is formed within the channel hole CH.

[0139] In the above steps, any of the thin film deposition processes selected from CVD, PVD, and ALD can be used to sequentially deposit a barrier layer 2411, a charge trapping layer 2412, a tunneling layer 2413, and a semiconductor channel layer 242 along the inner wall of the channel hole CH to form a channel structure 240. The barrier layer 2411, charge trapping layer 2412, and tunneling layer 2413 can be referred to as the storage functional layer 241.

[0140] It should be noted that the materials of the barrier layer 2211, charge trapping layer 2212, tunneling layer 2213 and semiconductor channel layer 222 can be referred to above, and will not be repeated here.

[0141] In some embodiments, after the storage functional layer 241 and the semiconductor channel layer 242 are sequentially formed in the channel hole CH, a channel filling layer 243 may also be formed in the channel hole CH. For example, any thin film deposition process selected from CVD, PVD, and ALD can be used to fill the channel hole CH, where the storage functional layer 241 and the semiconductor channel layer 242 are formed, with an insulating material, such as silicon oxide, to form a channel structure 240 having the storage functional layer 241, the semiconductor channel layer 242, and the channel filling layer 243.

[0142] S140: As Figure 13 As shown, a first gap GLS1 is formed that penetrates the initial stacked layer 210'.

[0143] In the above steps, a first gap GLS1 penetrating the initial stacked layer 210' can be formed using a dry / wet etching process. Exemplarily, the first gap GLS1 is formed using an anisotropic etching process (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation). The first gap GLS1 extends into the substrate 300; for example, the substrate 300 is a composite substrate, and the first gap GLS1 extends into the sacrificial polysilicon layer 330.

[0144] It should be noted that the formation of the channel hole CH penetrating the initial stacked layer 210' in S130 and the formation of the first gap GLS1 penetrating the initial stacked layer 210' in S140 can be carried out in different processes or in the same process. This disclosure does not limit this process.

[0145] S150: As Figure 13 , Figure 14 and Figure 15 As shown, the sacrificial layer 212' is replaced with the gate line layer 212 via the first gap GLS1.

[0146] In the above steps, see Figure 13 and Figure 14 The first gap GLS1 can be used as an etchant channel, and isotropic etching can be used to remove the sacrificial layer 212' to form a sacrificial gap; see [link to relevant documentation]. Figure 14 and Figure 15 Then, using the first gap GLS1 as a deposition channel, a gate line layer 212 is formed within the sacrificial gap using any one of the following thin film deposition processes: CVD, PVD, or ALD. It should be noted that the structure and material of the gate line layer 212 can be referred to above, and will not be repeated here.

[0147] The isotropic etching can be performed using selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant; in vapor phase etching, an etching gas is used as the etchant. Here, when the first dielectric layer 211 is made of silicon oxide and the sacrificial layer 212' is made of silicon nitride, a phosphoric acid solution can be used as the etchant in wet etching; and at least one of C4F8, C4F6, and CH2F2 can be used as the etching gas in vapor phase etching.

[0148] Based on the above, such as Figure 15 As shown, a stacked layer 210 can be formed, which includes an alternately stacked first dielectric layer 211 and a gate line layer 212.

[0149] S160: See also Figure 15 and Figure 16 A first isolation structure 220 is formed within the first gap GLS1.

[0150] In the above steps, any one of the thin film deposition processes, such as CVD, PVD, or ALD, can be used to form the first isolation structure 220 within the first gap GLS1. The structure and materials of the first isolation structure 220 can be referred to above, and will not be repeated here.

[0151] In some embodiments, see Figure 27 Between S120 and S130, the above preparation method also includes S121 to S122.

[0152] S121: As Figure 9 As shown, the edge portion of the first dielectric layer 211 near the channel hole CH is removed via the channel hole CH.

[0153] In the above steps, the channel hole CH is used as an etchant channel to etch the exposed end of the first dielectric layer 211 at the channel hole CH, and the etchant is used to etch the first dielectric layer 211. The first dielectric layer 211 is recessed near the boundary of the channel hole CH compared to the boundary of the sacrificial layer 212' near the channel hole CH, to form a groove.

[0154] It should be noted that the above etching can be either wet etching or vapor phase etching. Wet etching uses an etching solution as the etchant; vapor phase etching uses an etching gas as the etchant.

[0155] S122: As Figure 9 and Figure 11 As shown, a second dielectric layer 260 is formed in the groove.

[0156] In the above steps, along a direction parallel to the plane where the initial stacked layer 210' is located, the second dielectric layer 260 is located between the first dielectric layer 211 and the channel structure 240, and the dielectric constant of the second dielectric layer 260 is less than that of the first dielectric layer 211. The second dielectric layer 260 can utilize the channel holes CH as deposition channels, and can be formed within the groove using any of the thin film deposition processes of CVD, PVD, or ALD. For details, please refer to S1221-S1222, which will not be elaborated upon here.

[0157] It should be noted that the material of the second dielectric layer 260 can be referred to above, and will not be repeated here.

[0158] In some embodiments, such as Figure 28 As shown, S122 includes S1221 to S1222.

[0159] S1221: As Figure 10 As shown, the target material is deposited to form a second dielectric film 260'.

[0160] In the above steps, the dielectric constant of the target material is less than that of the material of the first dielectric layer 211. Specifically, any thin film deposition process among CVD, PVD, and ALD can be used to deposit the target material. During the deposition of the target material, the target material is also formed on the upper side of the initial stacked layer 210' and on the inner wall of the channel hole CH.

[0161] It should be noted that the target material is the material of the second dielectric layer 260, which can be referred to above for details, and will not be repeated here.

[0162] S1222: As Figure 10 and Figure 11 As shown, the portion of the second dielectric film 260' covering the initial stacked layer 210' and the portion covering the inner wall of the channel hole CH are removed to form the second dielectric layer 260.

[0163] In the above steps, an etchant can be used to etch the initial stacked layer 210' covered with the second dielectric film 260', and the etchant is used to etch the target material.

[0164] In the process of etching the portion of the second dielectric film 260' covering the initial stacked layer 210' and the portion covering the inner wall of the channel hole CH, the etching time can be controlled so that after the portion of the second dielectric film 260' covering the initial stacked layer 210' and the portion covering the inner wall of the channel hole CH are removed, the etching is stopped, so that the second dielectric layer 260 is away from the boundary of the first dielectric layer 211 and flush with the boundary of the sacrificial layer 212' near the channel hole CH.

[0165] In some embodiments, such as Figure 29 As shown, between S110 and S120, the above preparation method also includes S111.

[0166] S111: See also Figure 7 , forming a 280-degree covering layer.

[0167] In the above steps, any one of CVD, PVD, and ALD thin film deposition processes can be used to form a capping layer 280 on the initial stacked layer 210'. That is, the capping layer 280 is disposed on the initial stacked layer 210'. The material of the capping layer 280 can be referred to above, and will not be repeated here.

[0168] In this case, during the formation of the channel hole CH in S120, the channel hole CH also penetrates the capping layer. Similarly, during the formation of the first gap GLS1 in S140, the first gap GLS1 also penetrates the capping layer 280. At this time, if the material of the capping layer 280 is the same as the material of the first dielectric layer 211, during the removal of the edge portion of the first dielectric layer 211 near the channel hole CH in S121, a portion of the capping layer 280 is also removed, for example, the edge portion of the capping layer 280 near the channel hole CH is removed, and a portion of the capping layer 280 away from the initial stacked layer 210' is removed.

[0169] Based on this, after S122, such as Figure 30 As shown, the above preparation method also includes S123.

[0170] S123: See also Figure 11The side of the cover layer 280 away from the initial stacked layer 210' is planarized.

[0171] In the above steps, chemical mechanical polishing can be used to treat the surface of the cover layer 280 away from the stacked layer 210 so as to planarize the surface of the cover layer 280 away from the stacked layer 210.

[0172] In some embodiments, after S123, the above preparation method further includes S170.

[0173] S170: Remove substrate 300.

[0174] In the above steps, chemical mechanical planarization (CMP) and dry / wet etching processes can be used to remove the substrate 300.

[0175] For example, the substrate 300 is a composite substrate, and a wet etching process can be used to remove the substrate 310, the sacrificial silicon oxide layer 320 and the sacrificial polysilicon layer 330 in sequence to expose the portion of the channel structure 220 extending into the sacrificial polysilicon layer 330.

[0176] Embodiments of this disclosure also provide a method for fabricating a semiconductor structure 200, such as... Figure 31 As shown, the preparation method includes steps S100 to S300.

[0177] S100: See also Figure 7 This forms the initial stacked layer 210'.

[0178] The process and structure of the initial stacked layer 210' in the above steps can be referred to the above text, and will not be repeated here.

[0179] S200: See also Figure 20 This forms a second isolation structure 230 that extends through the initial stacked layer 210'.

[0180] In the above steps, such as Figure 5 and Figure 20 As shown, the second isolation structure 230 extends along the first direction X to divide the sacrificial layer 212' into multiple sub-sacrificial layers. The dielectric constant of the second isolation structure 230 is less than the dielectric constant of the first dielectric layer 211.

[0181] S300: See also Figure 21 This forms a channel structure of 240.

[0182] In the above steps, refer to Figure 32 S300 includes S310 to S320.

[0183] S310: See also Figure 8 This forms a channel hole CH that penetrates the initial stacked layer 210'.

[0184] In the above steps, a channel hole CH penetrating the initial stacked layer 210' can be formed by a dry / wet etching process. For example, an anisotropic etching process (any one of dry etching processes such as ion milling, plasma etching, reactive ion etching, and laser ablation) is used to form the channel hole CH.

[0185] S320: See also Figure 8 and Figure 12 A channel structure 240 is formed within the channel hole CH.

[0186] In the above steps, at least a portion of the channel structure 240 contacts a second isolation structure 230, and contacts two sub-sacrificial layers in the plane direction where the sacrificial layer 212' is located. The process and structure of the channel structure 240 can be referred to above, and will not be repeated here.

[0187] In some embodiments, see Figure 33 The above S200 includes S210 to S220.

[0188] S210: See also Figure 19 This forms a second gap, GLS2, that penetrates the initial stacked layer 210'.

[0189] In the above steps, refer to Figure 5 and Figure 19 The second slit GLS2 extends along the first direction X to divide the sacrificial layer 212' into multiple sub-sacrificial layers. The second slit GLS2 can be formed through the stacked layer 210 using a dry / wet etching process. Exemplarily, the second slit GLS2 is formed using an anisotropic etching process (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation).

[0190] S220: See also Figure 19 and Figure 20 The target material is then filled into the second gap, GLS2.

[0191] In the above steps, the dielectric constant of the target material is less than that of the material of the first dielectric layer 211. Specifically, any thin film deposition process among CVD, PVD, and ALD can be used to deposit the target material. The target material is the material of the second isolation structure 230, as detailed above, and will not be repeated here.

[0192] It should be noted that the target material filling the second gap GLS2 here can be the same as the target material forming the second dielectric film 260' in S3121 mentioned below.

[0193] In some embodiments, such as Figure 34 As shown, after S300, the above preparation method also includes S400 to S600.

[0194] S400: See also Figure 21 This forms the first slot GLS1 and the third slot GLS3 ​​that penetrate the initial stacked layer 210'.

[0195] In the above steps, refer to Figure 5 and Figure 21 The first slot GLS1 and the third slot GLS3 ​​extend along the first direction X. The first slot GLS1 is located on both sides of the array-arranged channel structure 240, and the third slot GLS3 ​​is located between two adjacent rows of channel structures 240.

[0196] In the above steps, the first gap GLS1 and the third gap GLS3 ​​penetrating the initial stacked layer 210' can be formed by dry / wet etching processes. For example, the first gap GLS1 and the third gap GLS3 ​​are formed by anisotropic etching (any one of dry etching processes such as ion milling, plasma etching, reactive ion etching, and laser ablation).

[0197] It should be noted that the first slit GLS1 and the third slit GLS3 ​​mentioned above can be formed in the same process, that is, by forming the first slit GLS1 and the third slit GLS3 ​​through a single etching process; the first slit GLS1 and the third slit GLS3 ​​mentioned above can also be formed in different processes, for example, forming the first slit GLS1 through a single etching process and forming the third slit GLS3 ​​through another etching process. This disclosure does not restrict the order of the above two steps.

[0198] S500: See also Figure 21 , Figure 22 and Figure 23 The sacrificial layer 212' is replaced with the gate line layer 212 via the first gap GLS1 and the third gap GLS3.

[0199] In the above steps, refer to Figure 21 and Figure 22 The first slit GLS1 and the third slit GLS3 ​​can be used as etchant channels, and isotropic etching can be used to remove the sacrificial layer 212' to form a sacrificial gap; see reference Figure 22 and Figure 23 Then, using the first gap GLS1 and the third gap GLS3 ​​as deposition channels, a gate line layer 212 is formed within the sacrificial gap using any one of the following thin film deposition processes: CVD, PVD, or ALD. It should be noted that the structure and material of the gate line layer 212 can be referred to above, and will not be repeated here.

[0200] Based on the above, such as Figure 23 As shown, a stacked layer 210 can be formed, which includes an alternately stacked first dielectric layer 211 and a gate line layer 212.

[0201] S600: See also Figure 22 and Figure 23 A first isolation structure 220 and a third isolation structure 250 are formed in the first gap GLS1 and the third gap GLS3, respectively.

[0202] In the above steps, any thin film deposition process selected from CVD, PVD, and ALD can be used to form the first isolation structure 220 and the third isolation structure 250 in the first gap GLS1 and the third gap GLS3, respectively. The structure and materials of the first isolation structure 220 and the third isolation structure 250 can be referred to above, and will not be repeated here.

[0203] It should be noted that when the materials of the first isolation structure 220 and the third isolation structure 250 are the same, the first isolation structure 220 and the third isolation structure 250 can be formed in the same process, that is, through a single deposition process. When the materials of the first isolation structure 220 and the third isolation structure 250 are different, the first isolation structure 220 and the third isolation structure 250 can be formed in different processes, for example, the first isolation structure 220 can be formed through a single deposition process, and the third isolation structure 250 can be formed through another deposition process. This disclosure does not restrict the order of the above two steps.

[0204] In some embodiments, such as Figure 35 As shown, between S310 and S320, the above preparation method also includes S311 to S312.

[0205] S311: See also Figure 9 The edge portion of the first dielectric layer 211 near the channel hole CH is removed via the channel hole CH.

[0206] In the above steps, the channel hole CH is used as an etchant channel to etch the exposed end of the first dielectric layer 211 at the channel hole CH, and the etchant is used to etch the first dielectric layer 211. The first dielectric layer 211 is recessed near the boundary of the channel hole CH compared to the boundary of the sacrificial layer 212' near the channel hole CH, to form a groove.

[0207] S312: See also Figure 9 and Figure 11 A second dielectric layer 260 is formed within the groove.

[0208] In the above steps, along the direction parallel to the plane where the initial stacked layer 210' is located (i.e., the plane defined by XY in the figure), the second dielectric layer 260 is located between the first dielectric layer 211 and the channel structure 240, and the dielectric constant of the second dielectric layer 260 is less than that of the first dielectric layer 211. The second dielectric layer 260 can utilize the channel holes CH as deposition channels, and can be formed within the groove using any of the thin film deposition processes of CVD, PVD, and ALD. For details, please refer to S3121 to S3122, which will not be elaborated upon here.

[0209] It should be noted that the material of the second dielectric layer 260 can be referred to above, and will not be repeated here.

[0210] In some embodiments, such as Figure 36 As shown, S312 includes S3121 to S3122.

[0211] S3121: As Figure 10 As shown, the target material is deposited to form a second dielectric film 260'.

[0212] In the above steps, the dielectric constant of the target material is less than that of the material of the first dielectric layer 211. Specifically, any thin film deposition process among CVD, PVD, and ALD can be used to deposit the target material. During the deposition of the target material, the target material is also formed on the upper side of the initial stacked layer 210' and on the inner wall of the channel hole CH.

[0213] It should be noted that the target material is the material of the second dielectric layer 260, which can be referred to above for details, and will not be repeated here.

[0214] S3122: As Figure 10 and Figure 11 As shown, the portion of the second dielectric film 260' covering the initial stacked layer 210' and the portion covering the inner wall of the channel hole CH are removed to form the second dielectric layer 260.

[0215] In the above steps, an etchant can be used to etch the initial stacked layer 210' covered with the second dielectric film 260', and the etchant is used to etch the target material.

[0216] In the process of etching the portion of the second dielectric film 260' covering the initial stacked layer 210' and the portion covering the inner wall of the channel hole CH, the etching time can be controlled so that after the portion of the second dielectric film 260' covering the initial stacked layer 210' and the portion covering the inner wall of the channel hole CH are removed, the etching is stopped, so that the second dielectric layer 260 is away from the boundary of the first dielectric layer 211 and flush with the boundary of the sacrificial layer 212' near the channel hole CH.

[0217] In some embodiments, such as Figure 37 As shown, between S100 and S310, the above preparation method also includes S110.

[0218] S110: See also Figure 7 , forming a 280-degree covering layer.

[0219] In the above steps, any one of CVD, PVD, and ALD thin film deposition processes can be used to form a capping layer 280 on the initial stacked layer 210'. That is, the capping layer 280 is disposed on the initial stacked layer 210'. The material of the capping layer 280 can be referred to above, and will not be repeated here.

[0220] The order in which S110 and S200 are performed is not restricted. For example, S200 is performed after S110, in which case the second isolation structure 230 still penetrates the cover layer 280.

[0221] In this case, during the formation of the channel hole CH in S310, the channel hole CH also penetrates the capping layer. Similarly, during the formation of the first slot GLS1 and the third slot GLS3 ​​in S500, the first slot GLS1 and the third slot GLS3 ​​also penetrate the capping layer 280. At this time, if the material of the capping layer 280 is the same as the material of the first dielectric layer 211, during the removal of the edge portion of the first dielectric layer 211 near the channel hole CH in S311, a portion of the capping layer 280 is also removed, for example, the edge portion of the capping layer 280 near the channel hole CH is removed, and a portion of the capping layer 280 away from the initial stacked layer 210' is removed.

[0222] Based on this, after S312, such as Figure 37 As shown, the above preparation method also includes S313.

[0223] S313: See also Figure 11 The side of the cover layer 280 away from the initial stacked layer 210' is planarized.

[0224] In the above steps, chemical mechanical polishing can be used to treat the surface of the cover layer 280 away from the stacked layer 210 so as to planarize the surface of the cover layer 280 away from the stacked layer 210.

[0225] Figure 38 This is a block diagram of a storage system according to some embodiments. Figure 39 This is a block diagram of a storage system according to some other embodiments.

[0226] Please see Figure 38 and Figure 39Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a memory 10 as described in some of the embodiments above. The controller 20 is coupled to the memory 10 to control the memory 10 to store data.

[0227] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0228] In some embodiments, see Figure 38 The storage system 1000 includes a controller 20 and a memory 10, and the storage system 1000 can be integrated into a memory card.

[0229] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0230] In other embodiments, see Figure 39 The storage system 1000 includes a controller 20 and multiple storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0231] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0232] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0233] In some embodiments, controller 20 may be configured to manage data stored in memory 10 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to memory 10.

[0234] Of course, controller 20 can also perform any other suitable functions, such as formatting memory 10; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0235] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0236] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0237] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0238] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The stacked layer includes multiple alternating first dielectric layers and multiple gate line layers; A first isolation structure extending through the stacked layers, the first isolation structure extending along a first direction, to divide the gate line layer into multiple gate lines; A second isolation structure extends through the stacked layers along the first direction to divide the gate line into at least two sub-gate lines; the dielectric constant of the second isolation structure is less than the dielectric constant of the first dielectric layer. A channel structure penetrating the stacked layer is disposed between two adjacent first isolation structures; at least a portion of the channel structure is located on the straight line where the second isolation structure is located, and the sub-gate lines on both sides of the second isolation structure respectively contact the channel structure located on the straight line where the second isolation structure is located.

2. The semiconductor structure according to claim 1, characterized in that, Along the first direction, the second isolation structure penetrates the corresponding row of channel structures to divide the channel structure into a first sub-channel structure and a second sub-channel structure, wherein the first sub-channel structure contacts the first sub-gate line and the second sub-channel structure contacts the second sub-gate line.

3. The semiconductor structure according to claim 1, characterized in that, Along the first direction, the second isolation structure contacts the outer surface of the corresponding row of channel structures.

4. The semiconductor structure according to claim 3, characterized in that, Also includes: A third isolation structure extends through the stacked layers, and the third isolation structure is located between two adjacent second isolation structures.

5. The semiconductor structure according to claim 1, characterized in that, The dielectric constant of the second isolation structure is less than or equal to 3.

6. The semiconductor structure according to claim 5, characterized in that, The material of the second isolation structure includes any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

7. The semiconductor structure according to claim 1, characterized in that, Along the second direction, the size of the second isolation structure is smaller than the diameter of the channel structure, the second direction is perpendicular to the first direction and parallel to the plane of the stacked layers.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that, The first dielectric layer is recessed near the boundary of the channel structure compared to the boundary of the sub-gate line near the channel structure. The semiconductor structure also includes: Multiple second dielectric layers are provided, with the second dielectric layer located between the first dielectric layer and the channel structure along a direction parallel to the plane of the stacked layers; and with the second dielectric layer located between two adjacent gate lines along a direction perpendicular to the plane of the stacked layers, wherein the dielectric constant of the second dielectric layer is less than that of the first dielectric layer.

9. The semiconductor structure according to claim 8, characterized in that, One side of the second dielectric layer is in contact with the first dielectric layer, and the other side is in contact with the channel structure.

10. A method for fabricating a semiconductor structure, characterized in that, include: An intermediate semiconductor structure is fabricated; the intermediate semiconductor structure includes a stacked layer, a first isolation structure and a channel structure penetrating the stacked layer, the stacked layer includes a plurality of alternately stacked first dielectric layers and a plurality of gate line layers, the first isolation structure extends along a first direction to divide the gate line layers into a plurality of gate lines, and the channel structure is located between two adjacent first isolation structures; A second isolation structure is formed through the stacked layers, the second isolation structure extending along the first direction to divide the gate line into at least two sub-gate lines; the dielectric constant of the second isolation structure is less than the dielectric constant of the first dielectric layer; at least a portion of the channel structure contacts one of the second isolation structures and contacts two of the sub-gate lines in the plane direction of the gate line layer.

11. The preparation method according to claim 10, characterized in that, The second isolation structure forming through the stacked layers includes: The stacked layers are etched to form a second gap; the second gap extends along the first direction to divide the gate line into sub-gate lines and the channel structure into a first sub-channel structure and a second sub-channel structure; The second gap is filled with a target material to form a second isolation structure; the dielectric constant of the target material is less than that of the material of the first dielectric layer.

12. The preparation method according to claim 10, characterized in that, The preparation of the intermediate semiconductor structure includes: An initial stack layer is formed; the initial stack layer includes a plurality of sacrificial layers and a plurality of first dielectric layers arranged alternately. Forming channel holes that penetrate the initial stacked layers; A channel structure is formed within the channel hole; Forming a first gap through the initial stacked layer; The sacrificial layer is replaced with a gate line layer via the first gap; A first isolation structure is formed within the first gap.

13. The preparation method according to claim 12, characterized in that, Between forming the channel hole and forming the channel structure, the method further includes: The edge portion of the first dielectric layer near the channel hole is removed through the channel hole, so that the boundary of the first dielectric layer near the channel hole is recessed relative to the boundary of the sacrificial layer near the channel hole to form a groove. A second dielectric layer is formed within the groove; the dielectric constant of the second dielectric layer is less than that of the first dielectric layer.

14. The preparation method according to claim 13, characterized in that, The formation of the second dielectric layer within the groove includes: A target material is deposited to form a second dielectric thin film; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer. The portion of the second dielectric film covering the initial stacked layer and the portion covering the inner wall of the channel hole are removed to form the second dielectric layer.

15. A method for fabricating a semiconductor structure, characterized in that, include: Form the initial stacking layers; The initial stack layer includes multiple sacrificial layers and multiple first dielectric layers arranged alternately; Forming a second isolation structure that extends through the initial stacked layers; The second isolation structure extends along the first direction to divide the sacrificial layer into multiple sub-sacrificial layers; the dielectric constant of the second isolation structure is less than the dielectric constant of the first dielectric layer; A channel hole is formed through the initial stacked layer, and a channel structure is formed within the channel hole; at least a portion of the channel structure contacts a second isolation structure and contacts two sub-sacrificial layers in the plane direction of the sacrificial layer.

16. The preparation method according to claim 15, characterized in that, The second isolation structure forming through the initial stacked layer includes: A second gap is formed through the initial stacked layer; the second gap extends along the first direction to divide the sacrificial layer into a plurality of sub-sacrificial layers; The second gap is filled with a target material; the dielectric constant of the target material is less than that of the material of the first dielectric layer.

17. The preparation method according to claim 15, characterized in that, After forming the channel structure, the method further includes: forming a first gap and a third gap through the initial stacked layer; the first gap and the third gap extend along a first direction, the first gap being located on both sides of the arrayed channel structure, and the third gap being located between two adjacent rows of the channel structure; The sacrificial layer is replaced with a gate line layer via the first gap and the third gap; A first isolation structure and a third isolation structure are formed in the first gap and the third gap, respectively.

18. The preparation method according to claim 15, characterized in that, Between forming the channel hole and forming the channel structure, the method further includes: The edge portion of the first dielectric layer near the channel hole is removed through the channel hole, so that the boundary of the first dielectric layer near the channel hole is recessed relative to the boundary of the sacrificial layer near the channel hole to form a groove. A second dielectric layer is formed within the groove; the dielectric constant of the second dielectric layer is less than that of the first dielectric layer.

19. The preparation method according to claim 18, characterized in that, The formation of the second dielectric layer within the groove includes: A target material is deposited to form a second dielectric thin film; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer. The portion of the second dielectric film covering the initial stacked layer and the portion covering the inner wall of the channel hole are removed to form the second dielectric layer.

20. A memory, characterized in that, include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure as described in any one of claims 1 to 9; Peripheral devices are electrically connected to the semiconductor structure.

21. A storage system, characterized in that, include: The memory is the memory as described in claim 20; A controller, coupled to the memory, controls the memory to store data.

22. An electronic device, characterized in that, Including the storage system as described in claim 21.

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