High electron mobility transistor epitaxial wafer with impurity blocking layer and preparation method thereof

Abstract

The present disclosure provides a high electron mobility transistor epitaxial wafer with an impurity barrier layer and a preparation method, which belongs to the field of semiconductor device technology. An impurity barrier layer is added between the silicon substrate and the AlN layer, and the impurity barrier layer is a TiC film layer. Since the C atoms in TiC are located at all octahedral positions of the Ti sublattice, it is a tightly packed interstitial compound that can effectively block impurities that diffuse upward from the substrate, reduce impurities in the epitaxial layer grown on the silicon substrate, improve the crystal quality of the epitaxial layer grown on the silicon substrate, and improve the quality and reliability of the high electron mobility transistor. In addition, the TiC film layer has a good lattice matching with the AlN layer, which improves the growth quality of the AlN layer to improve the overall quality of the epitaxial layer grown on the AlN layer, and ultimately effectively improves the quality and reliability of the obtained high electron mobility transistor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a high electron mobility transistor epitaxial wafer with an impurity barrier layer and a preparation method thereof. Background Art

[0002] A HEMT (High Electron Mobility Transistor) is a heterojunction field-effect transistor widely used in various electrical devices. HEMT epitaxial wafers are the foundation for HEMT device fabrication. These wafers consist of a substrate and, stacked on top of it, an AlN layer, an AlGaN buffer layer, a GaN high-resistance layer, a GaN channel layer, an AlGaN barrier layer, and a GaN cap layer.

[0003] HEMT epitaxial wafers are often grown on silicon substrates. However, during the high-temperature growth of epitaxial materials, the Si atoms in the silicon substrate will diffuse more rapidly under the action of high temperature, resulting in a certain amount of Si atoms in the epitaxial material stacked on the silicon substrate. These Si atoms are also prone to react with ammonia in the growth atmosphere, forming partially amorphous Si in the epitaxial material and on the surface of the silicon substrate. x N y Thin film. Si atoms diffused into the epitaxial material and amorphous Si x N y Thin films are impurities in the epitaxial material, which will affect the crystal quality of the epitaxial material. It will also make the epitaxial material on the side of the high electron mobility transistor close to the silicon substrate unable to achieve high resistance and may cause leakage, thereby reducing the quality and reliability of the final high electron mobility transistor. Summary of the Invention

[0004] The present disclosure provides a high electron mobility transistor epitaxial wafer with an impurity barrier layer and a method for manufacturing the same, which can reduce impurities within the high electron mobility transistor epitaxial wafer to improve the quality and reliability of the resulting high electron mobility transistor. The technical solution is as follows:

[0005] An embodiment of the present disclosure provides a high electron mobility transistor epitaxial wafer, wherein the high electron mobility transistor epitaxial wafer with an impurity blocking layer includes a silicon substrate and an impurity blocking layer, an AlN layer, an AlGaN buffer layer, a GaN high resistance layer, a GaN channel layer, an AlGaN barrier layer and a GaN cap layer sequentially stacked on the silicon substrate, wherein the impurity blocking layer is a TiC film layer.

[0006] Optionally, the thickness of the TiC film layer is 15 to 30 nm.

[0007] Optionally, the density of the TiC film is 10+E7 / cm -3 ~10+E8 / cm -3 .

[0008] The present disclosure provides a method for preparing a high electron mobility transistor epitaxial wafer having an impurity blocking layer. The method for preparing a high electron mobility transistor epitaxial wafer having an impurity blocking layer includes:

[0009] providing a silicon substrate;

[0010] An impurity blocking layer, an AlN layer, an AlGaN buffer layer, a GaN high resistance layer, a GaN channel layer, an AlGaN barrier layer and a GaN cap layer are sequentially grown on the silicon substrate, wherein the impurity blocking layer is a TiC film layer.

[0011] Optionally, the TiC film layer is obtained by sputtering, and the sputtering power of the TiC film layer is 500-800W.

[0012] Optionally, the deposition temperature of the TiC film layer is 400-600° C., and the deposition pressure of the TiC film layer is 1-10 Torr.

[0013] Optionally, the sputtering target material of the TiC film layer is Ti, the reaction gas of the TiC film layer is CH4, the sputtering gas of the TiC film layer is Ar, and the gas volume ratio of CH4 to Ar in the reaction chamber is 2:1 to 10:1.

[0014] Optionally, the method for preparing a high electron mobility transistor epitaxial wafer having an impurity blocking layer further includes:

[0015] After the impurity blocking layer is grown and before the AlN layer is grown, the impurity blocking layer is subjected to high-temperature treatment in a pure hydrogen environment.

[0016] Optionally, the impurity blocking layer is subjected to high-temperature treatment in a pure hydrogen environment at a pressure of 50-150 mbar and a temperature of 1000-1200° C.

[0017] Optionally, an AlN layer is grown on the impurity blocking layer under conditions of a pressure of 40-70 mbar and a temperature of 1100-1200° C.

[0018] The technical solutions provided by the embodiments of the present disclosure bring beneficial effects including:

[0019] An impurity barrier layer is added between the silicon substrate and the AlN layer, and the impurity barrier layer is a TiC film. Because the carbon atoms in TiC are located at all octahedral positions in the Ti sublattice, it is a tightly packed interstitial compound that effectively blocks impurities (oxygen and Si atoms) that diffuse upward from the substrate, reducing impurities in the epitaxial layer grown on the silicon substrate and improving the crystal quality of the epitaxial layer grown on the silicon substrate. Furthermore, the reduction of impurities in the epitaxial layer grown on the silicon substrate also ensures the high resistance effect of the epitaxial layer grown on the silicon substrate, effectively reducing the possibility of leakage in the resulting high electron mobility transistor, and improving the quality and reliability of the high electron mobility transistor. Furthermore, the TiC film and the AlN layer have excellent lattice matching, with a lattice mismatch of 1.5%. Therefore, the AlN layer can be well grown on the TiC film, reducing defects and stress caused by the lattice mismatch between the silicon substrate and the AlN layer, improving the growth quality of the AlN layer, and thus improving the overall quality of the epitaxial layer grown on the AlN layer, ultimately effectively improving the quality and reliability of the resulting high electron mobility transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 1 is a schematic structural diagram of a high electron mobility transistor epitaxial wafer with an impurity barrier layer provided by an embodiment of the present disclosure;

[0022] Figure 2 1 is a schematic structural diagram of another high electron mobility transistor epitaxial wafer with an impurity barrier layer provided by an embodiment of the present disclosure;

[0023] Figure 3 This is a flow chart of a method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer provided by an embodiment of the present disclosure;

[0024] Figure 4 This is a flow chart of another method for preparing a high electron mobility transistor epitaxial wafer with an impurity barrier layer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0026] Figure 1This is a schematic structural diagram of a high electron mobility transistor epitaxial wafer with an impurity barrier layer provided by an embodiment of the present disclosure, with reference to Figure 1 It can be seen that the embodiment of the present disclosure provides a high electron mobility transistor epitaxial wafer, and the high electron mobility transistor epitaxial wafer with an impurity blocking layer 2 includes a silicon substrate 1 and an impurity blocking layer 2, an AlN layer 3, an AlGaN buffer layer 4, a GaN high resistance layer 5, a GaN channel layer 6, an AlGaN barrier layer 7 and a GaN cap layer 8 stacked in sequence on the silicon substrate 1, and the impurity blocking layer 2 is a TiC film layer.

[0027] An impurity barrier layer 2 is added between the silicon substrate 1 and the AlN layer 3, and this impurity barrier layer 2 is a TiC film. Because the carbon atoms in TiC are located at all octahedral positions in the Ti sublattice, it is a tightly packed interstitial compound that effectively blocks impurities (oxygen and Si atoms) that diffuse upward from the substrate, reducing impurities in the epitaxial layer grown on the silicon substrate 1 and improving the crystal quality of the epitaxial layer grown on the silicon substrate 1. Furthermore, the reduction of impurities in the epitaxial layer grown on the silicon substrate 1 ensures the high resistance of the epitaxial layer grown on the silicon substrate 1, effectively reducing the potential for leakage in the resulting high electron mobility transistor (HEMT), thereby improving the quality and reliability of the HEMT. Furthermore, the TiC film and the AlN layer 3 have excellent lattice matching, with a lattice mismatch of 1.5%. Therefore, the AlN layer 3 can be well grown on the TiC film, reducing defects and stress caused by the lattice mismatch between the silicon substrate 1 and the AlN layer 3, improving the growth quality of the AlN layer 3, and thus improving the overall quality of the epitaxial layer grown on the AlN layer 3, ultimately effectively improving the quality and reliability of the resulting HEMT.

[0028] Optionally, the thickness of the TiC film layer is 15-30 nm.

[0029] When the thickness of the TiC film layer is within the above range, it can be ensured that the TiC film layer has a good impurity barrier capability, and the quality of the TiC film layer itself is also good.

[0030] For example, the density of the TiC film is 10+E7 / cm -3 ~10+E8 / cm -3 .

[0031] When the density of the TiC film is within the above range, the impurity blocking effect of the TiC film can be further improved, the impurities inside the high electron mobility transistor are reduced, and the quality and reliability of the ultimately obtained high electron mobility transistor can be further improved.

[0032] It should be noted that, under the premise that the TiC film layer itself has the ability to block impurities, setting the thickness or density of the TiC film layer outside the above range can also achieve an effective impurity blocking effect.

[0033] Figure 2 This is a schematic structural diagram of another high electron mobility transistor epitaxial wafer with an impurity barrier layer 2 provided in an embodiment of the present disclosure, with reference to Figure 2 It can be seen that the high electron mobility transistor epitaxial wafer may include a substrate and an impurity blocking layer 2, an AlN layer 3, an AlGaN buffer layer 4, a GaN high resistance layer 5, a GaN channel layer 6, an AlN insertion layer 9, an AlGaN barrier layer 7 and a GaN cap layer 8 stacked in sequence on a silicon substrate 1, and the impurity blocking layer 2 is a TiC film layer.

[0034] It should be noted that Figure 2 The structure of the TiC film shown in Figure 1 The structure of the TiC film layer is the same as that shown in , so it will not be repeated here.

[0035] Optionally, the thickness of the AlN layer 3 is 150-300 nm, which can ensure good quality of the AlN layer 3 and provide a good growth foundation for the HEMT epitaxial wafer.

[0036] For example, the thickness of the AlGaN buffer layer 4 is 1 to 1.5 micrometers. The obtained AlGaN buffer layer 4 is of good quality.

[0037] Optionally, the thickness of the GaN channel layer 6 may be 100-400 nm.

[0038] The thickness of the GaN channel layer 6 is appropriate, the cost is reasonable, and the quality of the high electron mobility transistor epitaxial wafer can be effectively improved.

[0039] In one implementation provided in the present disclosure, the thickness of the GaN channel layer 6 may be 400 nm, which is not limited in the present disclosure.

[0040] Figure 2 Relative Figure 1 The structure of the HEMT epitaxial wafer incorporates an AlN insertion layer 9, which minimizes the negative impact of the underlying lattice mismatch. Furthermore, a two-dimensional electron gas (2DEG) forms at the interface between the AlN insertion layer 9 and the GaN channel layer 6, and between the AlN insertion layer 9 and the AlGaN barrier layer 7. This 2DEG increases carrier accumulation at these interfaces, ensuring the effectiveness of the high electron mobility transistor epitaxial wafer.

[0041] Optionally, the thickness of the AlN insertion layer 9 is 0.5-2 nm.

[0042] When the thickness of the AlN insertion layer 9 is within the above range, the two-dimensional electron gas can be effectively generated without excessively increasing the cost.

[0043] In one implementation provided by the present disclosure, the thickness of the AlN insertion layer 9 may be 2 nm, which is not limited by the present disclosure.

[0044] Optionally, the thickness of the AlGaN barrier layer 7 may be 15-40 nm, which can ensure the quality of the high electron mobility transistor epitaxial wafer.

[0045] In one implementation provided in the present disclosure, the thickness of the AlGaN barrier layer 7 may be 100 nm, which is not limited in the present disclosure.

[0046] For example, the GaN capping layer 8 may be a P-type GaN layer, which is easy to prepare and obtain.

[0047] Optionally, the thickness of the GaN capping layer 8 is 3-10 nm. The obtained GaN capping layer 8 has good overall quality.

[0048] Exemplarily, the impurity in the GaN capping layer 8 is Mg, which is convenient for preparation and acquisition.

[0049] It should be noted that Figure 2 This is only one implementation of the high electron mobility transistor epitaxial wafer provided in the embodiment of the present disclosure. In other implementations provided in the present disclosure, the high electron mobility transistor epitaxial wafer may also be other forms of high electron mobility transistor epitaxial wafer including a reflective layer, and the present disclosure does not limit this.

[0050] Figure 3 This is a flow chart of a method for preparing a high electron mobility transistor epitaxial wafer with an impurity barrier layer provided by an embodiment of the present disclosure, with reference to Figure 3 It can be seen that the embodiment of the present disclosure provides a method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer includes:

[0051] S101: Provide a silicon substrate.

[0052] S102: An impurity blocking layer, an AlN layer, an AlGaN buffer layer, a GaN high resistance layer, a GaN channel layer, an AlGaN barrier layer and a GaN cap layer are sequentially grown on a silicon substrate, wherein the impurity blocking layer is a TiC film layer.

[0053] An impurity barrier layer is added between the silicon substrate and the AlN layer, and the impurity barrier layer is a TiC film. Because the carbon atoms in TiC are located at all octahedral positions in the Ti sublattice, it is a tightly packed interstitial compound that effectively blocks impurities (oxygen and Si atoms) that diffuse upward from the substrate, reducing impurities in the epitaxial layer grown on the silicon substrate and improving the crystal quality of the epitaxial layer grown on the silicon substrate. Furthermore, the reduction of impurities in the epitaxial layer grown on the silicon substrate also ensures the high resistance effect of the epitaxial layer grown on the silicon substrate, effectively reducing the possibility of leakage in the resulting high electron mobility transistor, and improving the quality and reliability of the high electron mobility transistor. Furthermore, the TiC film and the AlN layer have excellent lattice matching, with a lattice mismatch of 1.5%. Therefore, the AlN layer can be well grown on the TiC film, reducing defects and stress caused by the lattice mismatch between the silicon substrate and the AlN layer, improving the growth quality of the AlN layer, and thus improving the overall quality of the epitaxial layer grown on the AlN layer, ultimately effectively improving the quality and reliability of the resulting high electron mobility transistor.

[0054] Optionally, in step S102 , the TiC film layer is obtained by sputtering, and the sputtering power of the TiC film layer is 500-800W.

[0055] The quality of the TiC film layer obtained by sputtering is good, and the sputtering power of the TiC film layer is within the above range, which can further improve the crystal quality of the final TiC film layer, ensure the deposition efficiency and deposition quality of the TiC film layer, and thus improve the quality and reliability of the final high electron mobility transistor.

[0056] Illustratively, the deposition temperature of the TiC film layer is 400-600° C., and the deposition pressure of the TiC film layer is 1-10 Torr.

[0057] When the deposition temperature and deposition pressure of the TiC film layer are within the above ranges, a TiC film layer with a higher density can be obtained. The TiC film layer with a higher density also has a better effect of blocking impurities, effectively reducing impurities that can eventually enter the interior of the high electron mobility transistor, thereby improving the quality and reliability of the high electron mobility transistor finally obtained.

[0058] For example, the deposition rate of the TiC film layer may be 0.1 nm / min to 1 nm / min.

[0059] The deposition rate of the TiC film layer will also affect the density of the obtained TiC film layer to a certain extent. Setting the deposition rate of the TiC film layer within the above range can further improve the density of the final TiC film layer, thereby improving the TiC film layer's barrier effect on impurities, reducing impurities that can ultimately enter the interior of the high electron mobility transistor, and improving the quality and reliability of the final high electron mobility transistor.

[0060] Optionally, the sputtering target material of the TiC film layer is Ti, the reaction gas of the TiC film layer is CH4, the sputtering gas of the TiC film layer is Ar, and the gas volume ratio of CH4 to Ar in the reaction chamber is 2:1 to 10:1.

[0061] The sputtering target material of the TiC film layer is Ti, the reaction gas of the TiC film layer is CH4, and the sputtering gas of the TiC film layer is Ar, which can facilitate the deposition and growth of the TiC film layer. The gas volume ratio of CH4 to Ar in the reaction chamber where the TiC film layer is located is set within the above range. This can ensure that the Ar gas in the reaction chamber as kinetic energy is sufficient, which can improve the sputtering efficiency of Ti. In addition, the volume of CH4 is also relatively reasonable, which can fully react with Ti to obtain a TiC film layer with relatively appropriate deposition efficiency and good quality.

[0062] Figure 4 This is a flow chart of another method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer provided by an embodiment of the present disclosure. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer may further include:

[0063] S201: Provide a silicon substrate.

[0064] S202: growing an impurity barrier layer on the silicon substrate, where the impurity barrier layer is a TiC film layer.

[0065] The specific deposition conditions and deposition rate of the impurity barrier layer in step S202 can be found in Figure 3 The deposition conditions and deposition rate of the impurity blocking layer in step S102 of the method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer are not described in detail here.

[0066] S203: performing high-temperature treatment on the impurity barrier layer in a pure hydrogen environment.

[0067] High-temperature treatment of the impurity barrier layer in a pure hydrogen environment will not, on the one hand, cause damage or injury to the impurity barrier layer; on the other hand, it can clean impurities that may exist on the surface of some impurity barrier layers, thereby improving the surface quality of the impurity barrier layer, thereby improving the quality of other epitaxial materials grown on the surface of the impurity barrier layer, and thereby improving the quality and reliability of the high electron mobility transistor finally obtained.

[0068] Optionally, the impurity barrier layer is subjected to high-temperature treatment in a pure hydrogen environment at a pressure of 50-150 mbar and a temperature of 1000-1200° C.

[0069] This effectively treats impurities that may be present on the surface of the impurity barrier layer, effectively improving the crystal quality of the epitaxial material grown on the surface of the impurity barrier layer. Furthermore, the high temperature also makes it easier to transition to the growth environment required for the AlN layer, improving the growth efficiency of high electron mobility transistors.

[0070] For example, the treatment time of the impurity blocking layer may be 5 to 10 minutes, which can ensure that impurities are fully removed, thereby ensuring the cleanliness of the surface of the impurity blocking layer and the quality of the epitaxial material grown on the surface of the impurity blocking layer.

[0071] S204: growing an AlN layer on the impurity barrier layer.

[0072] Optionally, an AlN layer is grown on the impurity barrier layer at a pressure of 40-70 mbar and a temperature of 1100-1200° C.

[0073] Under conditions of lower pressure and higher temperature, the lattice mismatch between the grown AlN layer and the TiC film layer is very small.

[0074] S205: growing an AlGaN buffer layer on the AlN layer.

[0075] Optionally, step S204 may include: introducing an Al source, a Ga source, and a reaction gas into the reaction chamber using argon as a carrier gas to grow an AlGaN film layer; closing the Al source, the Ga source, and the reaction gas; introducing hydrogen into the reaction chamber at a temperature of 1050 to 1250° C. to treat the AlGaN film layer; and repeating the above steps until the AlGaN layer is obtained.

[0076] During the growth of the AlGaN buffer layer, the growth uniformity and surface flatness of the AlGaN buffer layer can be improved. While the crystal quality of the AlGaN buffer layer itself is improved, structures such as gallium nitride grown based on the surface of the AlGaN buffer layer can also be improved.

[0077] Optionally, the thickness of the AlGaN film layer is 20-50 nm.

[0078] When the thickness of each AlGaN film layer is within the above range, the growth of the AlGaN film layer can be relatively uniform, and the surface flatness of the AlGaN film layer can be relatively high. Combined with the subsequent hydrogen treatment, the surface dislocation density of the AlGaN film layer can be effectively reduced, thereby improving the crystal quality of the final second AlGaN layer.

[0079] Optionally, hydrogen is introduced into the reaction chamber at a temperature of 1050-1250° C. for a time period of 5-10 seconds to treat the AlGaN film layer.

[0080] The duration of hydrogen treatment is within the above range, which can ensure that the surface of the AlGaN film layer is sufficiently treated by hydrogen, and the AlGaN film layer also undergoes sufficient annealing during this time, and the crystal quality of the AlGaN film layer can be further improved.

[0081] Optionally, the thickness of the AlGaN buffer layer is 100-200 nm.

[0082] When the thickness of the AlGaN buffer layer is within the above range, the quality of the AlGaN buffer layer is good and can also provide a good growth foundation for subsequent growth structures.

[0083] Optionally, an Al source, a Ga source, and a reaction gas are introduced into the reaction chamber using argon as a carrier gas to grow an AlGaN film layer, further comprising:

[0084] Argon is used as a carrier gas to introduce Al source, Ga source, Fe source and reaction gas into the reaction chamber to grow an AlGaN film layer.

[0085] The incorporation of Fe elements into the AlGaN film layer can achieve high resistance of the AlGaN buffer layer, facilitating the transition to subsequent high-resistance gallium nitride materials.

[0086] It should be noted that under the premise that argon is used as the carrier gas to introduce Al source, Ga source, Fe source and reaction gas to grow the AlGaN film layer, during the subsequent hydrogen treatment of the AlGaN film layer, the Al source, Ga source, Fe source and reaction gas also need to be turned off at the same time.

[0087] Optionally, the flow rate of the Fe source is 50-200 sccm.

[0088] When the flow rate of the Fe source is within the above range, a good quality AlGaN buffer layer can be obtained.

[0089] For example, the Fe doping concentration in the AlGaN buffer layer is 10 18 ~10 20 cm -3 The AlGaN buffer layer has good quality and can achieve a good transition with the subsequent high-resistance GaN material.

[0090] Optionally, the growth conditions of the AlGaN buffer layer include: a growth temperature of 1050° C. to 1250° C. and a pressure of 40 to 70 mbar, thereby obtaining an AlGaN buffer layer of good quality.

[0091] S206: growing a GaN high-resistance layer on the AlGaN buffer layer.

[0092] The growth conditions and parameters of GaN high resistance layer can be referred to Figure 3The step S102 shown in FIG is omitted for brevity.

[0093] S207: growing a GaN channel layer on the GaN high-resistance layer.

[0094] Optionally, the growth conditions of the GaN channel layer include: a growth temperature of 1050° C. to 1150° C. and a pressure of 150 to 250 mbar, thereby obtaining a GaN channel layer of good quality.

[0095] Exemplarily, the thickness of the GaN channel layer is between 1.0 and 1.5 microns, thereby improving the quality of the resulting HEMT epitaxial wafer and achieving a better quality GaN channel layer.

[0096] S208: growing an AlN insertion layer on the GaN channel layer.

[0097] Optionally, the growth temperature of the AlN insertion layer is 1050° C. to 1150° C., and the growth pressure of the AlN insertion layer is 40 to 70 mbar, thereby obtaining an AlN insertion layer of good quality.

[0098] S209: growing an AlGaN barrier layer on the AlN insertion layer.

[0099] Optionally, the growth temperature of the AlGaN barrier layer is 1050° C. to 1150° C., and the growth pressure of the AlGaN barrier layer is 40 to 70 mbar. The quality of the obtained AlGaN barrier layer is good.

[0100] In an implementation provided by the present disclosure, the growth temperature of the AlGaN barrier layer may be 1020° C. The present disclosure does not impose any limitation on this.

[0101] S210: growing a GaN cap layer on the AlGaN barrier layer.

[0102] Optionally, the growth temperature of the GaN capping layer is 1050° C. to 1150° C., and the growth pressure of the AlGaN barrier layer is 40 to 70 mbar. The quality of the obtained GaN capping layer is good.

[0103] It should be noted that in the embodiments of the present disclosure, a Veeco K 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition) device is used to achieve the LED growth method. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas, high-purity NH3 is used as the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as the gallium source, trimethylindium (TMIn) is used as the indium source, silane (SiH4) is used as the N-type dopant, trimethylaluminum (TMAl) is used as the aluminum source, bis(octyl)magnesium (CP2Mg) is used as the P-type dopant, and ferrocene (Cp2Fe) is used as the precursor of the iron (Fe) source.

[0104] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make slight changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A high electron mobility transistor epitaxial wafer having an impurity barrier layer, characterized in that: The high electron mobility transistor epitaxial wafer with an impurity blocking layer includes a silicon substrate and an impurity blocking layer, an AlN layer, an AlGaN buffer layer, a GaN high resistance layer, a GaN channel layer, an AlGaN barrier layer and a GaN cap layer sequentially stacked on the silicon substrate. The impurity blocking layer is a TiC film layer, and the density of the TiC film layer is 10+E7 / cm -3 ~10+E8 / cm -3 , the C atoms in the TiC film are located at all octahedral positions of the Ti sublattice.

2. The high electron mobility transistor epitaxial wafer with an impurity barrier layer according to claim 1, wherein: The thickness of the TiC film layer is 15-30 nm.

3. A method for preparing a high electron mobility transistor epitaxial wafer with an impurity barrier layer, characterized in that: The method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer comprises: providing a silicon substrate; An impurity blocking layer, an AlN layer, an AlGaN buffer layer, a GaN high resistance layer, a GaN channel layer, an AlGaN barrier layer and a GaN cap layer are sequentially grown on the silicon substrate, wherein the impurity blocking layer is a TiC film layer, and the density of the TiC film layer is 10+E7 / cm -3 ~10+E8 / cm -3 , the C atoms in the TiC film are located at all octahedral positions of the Ti sublattice.

4. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity barrier layer according to claim 3, wherein: The TiC film layer is obtained by sputtering, and the sputtering power of the TiC film layer is 500-800W.

5. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity barrier layer according to claim 3, wherein: The deposition temperature of the TiC film layer is 400-600° C., and the deposition pressure of the TiC film layer is 1-10 torr.

6. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer according to claim 3, wherein: The sputtering target material of the TiC film layer is Ti, the reaction gas of the TiC film layer is CH4, the sputtering gas of the TiC film layer is Ar, and the gas volume ratio of the CH4 to the Ar in the reaction chamber is 2:1 to 10:

1.

7. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer according to any one of claims 3 to 6, wherein: The method for preparing a high electron mobility transistor epitaxial wafer having an impurity blocking layer further comprises: After the impurity blocking layer is grown and before the AlN layer is grown, the impurity blocking layer is subjected to high-temperature treatment in a pure hydrogen environment.

8. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity barrier layer according to claim 7, wherein: The impurity blocking layer is subjected to high-temperature treatment in a pure hydrogen environment with a pressure of 50 to 150 mbar and a temperature of 1000 to 1200° C.

9. The method for preparing a high electron mobility transistor epitaxial wafer with an impurity blocking layer according to claim 7, wherein: An AlN layer is grown on the impurity blocking layer under the conditions of a pressure of 40-70 mbar and a temperature of 1100-1200° C.

Images