Memory Device and Control Method

Abstract

Provided is a memory device capable of performing appropriate temperature control. According to an embodiment, the memory device includes a detector and a magazine. The detector writes data to a semiconductor wafer memory including a plurality of nonvolatile memory chips, or reads data from the semiconductor wafer memory. The magazine stores a plurality of the semiconductor wafers in a state of being detached from the detector. The detector has a first temperature control mechanism. The first temperature control mechanism raises the temperature of the semiconductor wafer to a temperature higher than a first temperature. The magazine has a second temperature control mechanism. The second temperature control mechanism cools the semiconductor wafer to a temperature lower than a second temperature lower than the first temperature.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device and a control method. Background Art

[0002] In recent years, various memory devices such as SSD (solid state drive) and HDD (hard disk drive) have been utilized. For example, a NAND type flash memory mounted on an SSD is manufactured by forming a plurality of semiconductor chips on a semiconductor wafer and then cutting it.

[0003] In addition, a probe card is used as an inspection jig that relays an electrical signal between a semiconductor wafer on which a semiconductor chip is formed and an inspection device that inspects the semiconductor chip. Briefly, the probe card is composed of a printed circuit board (PCB) and probes. The probes bring the pad electrodes formed on the semiconductor wafer into contact with the probes of the probe card, for example, electrically connecting a device on the printed circuit board (PCB) to the semiconductor wafer.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: US Patent No. 9,159,451 Specification

[0007] Patent Document 2: US Patent No. 6,499,121 Specification

[0008] Patent Document 3: US Patent No. 6,063,640 Specification Summary of the Invention

[0009] Technical Problem to be Solved by the Invention

[0010] One embodiment provides a memory device and a control method capable of appropriately performing various temperature controls related to a semiconductor wafer including a plurality of non-volatile memory chips.

[0011] Means for Solving the Technical Problem

[0012] According to an embodiment, the memory device includes a detector and a stocker. The detector writes data to a semiconductor wafer memory including a plurality of non-volatile memory chips, or reads data from the semiconductor wafer memory. The stocker stores a plurality of the semiconductor wafers in a state of being detached from the detector. The detector has a first temperature control mechanism. The first temperature control mechanism raises the temperature of the semiconductor wafer to a first temperature or higher. The stocker has a second temperature control mechanism. The second temperature control mechanism cools the semiconductor wafer to a second temperature lower than the first temperature. Brief Description of the Drawings

[0013] Figure 1 It is a diagram showing a structural example of a memory device representing an embodiment.

[0014] Figure 2 It is a diagram showing the state where the pad electrodes formed on the wafer in the memory device of the embodiment are in contact with the probes of the probe card.

[0015] Figure 3 It is a block diagram schematically showing a memory device of an embodiment.

[0016] Figure 4 It is a diagram for explaining an example of setting of a temperature control region related to a stage in a memory device of an embodiment.

[0017] Figure 5 It is a diagram showing a structural example of a heating / cooling mechanism provided in a stage of a memory device of an embodiment.

[0018] Figure 6 It is a diagram showing an example of the configuration of a heating / cooling mechanism in a stage of a memory device of an embodiment.

[0019] Figure 7 It is a diagram for explaining an example of temperature control of a heating / cooling mechanism provided on a stage in a memory device of an embodiment.

[0020] Figure 8 It is a diagram for explaining an example of a mechanism for uniformly controlling the temperature of devices on a probe card in a memory device of an embodiment.

[0021] Figure 9 It is a diagram showing a plurality of probes arranged on the first surface of a probe card in a memory device of an embodiment.

[0022] Figure 10 It is a diagram showing a plurality of controllers arranged on the second surface of a probe card in a memory device of an embodiment.

[0023] Figure 11 It is a diagram for explaining an example of the operation of a device installed in a detector in a memory device of an embodiment.

[0024] Figure 12 It is a diagram showing a first example of a cooling mechanism provided in a magazine in a memory device of an embodiment.

[0025] Figure 13 It is a diagram showing a second example of a cooling mechanism provided in a magazine in a memory device of an embodiment.

[0026] Figure 14It is a flowchart showing an example of the temperature control process during wafer replacement performed by the memory device representing the embodiment. Detailed Embodiment

[0027] Hereinafter, the embodiment will be described with reference to the accompanying drawings.

[0028] Figure 1 It is a diagram showing a structural example of the memory device 1 of the present embodiment.

[0029] In the present embodiment, it is assumed that a probe card used as an inspection jig is repurposed, and a large-capacity memory device 1 is constructed in units of semiconductor wafers without cutting. Furthermore, it is assumed that a larger-capacity memory device 1 is constructed by enabling the semiconductor wafers electrically connected to the probes to be replaced and mounting multiple semiconductor wafers.

[0030] When constructing such a memory device 1, it is preferable that the semiconductor wafers inside the detector are at a high temperature above room temperature and the temperature is kept uniform within the semiconductor wafers. On the other hand, it is preferable that the semiconductor wafers stored outside the detector are kept at a low temperature below room temperature.

[0031] The memory device 1 includes a reader & writer (detector) 100, a memory transfer system 200, and a magazine 300. In Figure 1 an example is shown where two detectors 100 are provided, but this is not limiting, and the number of detectors 100 can be variously changed. In addition, the memory device 1 has an air-conditioning control mechanism 500 for replacing the gaseous atmosphere inside the detector 100, inside the memory transfer system 200, and inside the magazine 300 with dry air, rare gas, inert gas, etc. that do not contain water.

[0032] The memory device 1 mounts semiconductor wafers (wafer 400) as memories, and a plurality of NAND flash memory chips (NAND chips) are formed on the semiconductor wafers. In addition, the memory device 1 mounts a plurality of wafers 400, and a specified number of wafers 400 (two wafers 400 in the Figure 1 example case) are appropriately selected and used from the plurality of wafers 400. Specifically, the memory device 1 can replace the wafer 400 inside the detector 100 with the wafer 400 inside the magazine 300.

[0033] The detector 100 includes a probe card 110, a stage 120, and a drive unit 130.

[0034] The probe card 110 is a unit electrically connected to the wafer 400 on the stage 120. As described above, simply put, the probe card 110 is composed of a printed circuit board (PCB) and probes. In the memory device 1 of the present embodiment, a controller that controls writing data to the NAND chips formed on the wafer 400 and reading data from the NAND chips, etc., is arranged as a device 111 on the printed circuit board PCB of the probe card 110. In addition, in the memory device 1 of the present embodiment, a temperature control mechanism (heating and cooling mechanism 112, cooling mechanism 113, heat insulation material 114) is provided inside the probe card 110. The temperature control mechanism provided inside the probe card 110 will be described later.

[0035] The stage 120 is a unit that holds the wafer 400. In the memory device 1 of the present embodiment, a temperature control mechanism (heating and cooling mechanism 121) is also provided inside the stage 120. The temperature control mechanism provided inside the stage 120 will also be described later.

[0036] The drive unit 130 is a unit that moves the stage 120 to bring the probes of the probe card 110 into contact with the pad electrodes formed on the wafer 400. Here, it is assumed that the drive unit 130 moves the stage 120, but the probe card 110 may also be moved. In addition, the drive unit 130 may move both the probe card 110 and the stage 120. The drive unit 130 may also move the stage 120 to separate the probes in contact with the pad electrodes from the pad electrodes.

[0037] Figure 2 It shows a state where the probes 115 of the probe card 110 are in contact with the pad electrodes 410 formed on the wafer 400 by the drive unit 130.

[0038] When the probes 115 are in contact with the pad electrodes 410, the controller arranged as one of the devices 111 on the printed circuit board PCB of the probe card 110 is electrically connected to the NAND chips formed on the wafer 400. Thereby, the controller can control writing data to the NAND chips, reading data from the NAND chips, and erasing data in the NAND chips.

[0039] Return to Figure 1 , and continue to describe a structural example of the memory device 1.

[0040] The memory transfer system 200 has a memory transferrer 210.

[0041] The memory transporter 210 transports the memory, i.e., the wafer 400, in the memory device 1 of the present embodiment from the magazine 300 to the detector 100, or from the detector 100 to the magazine 300. In addition, the structure described below is an example, and the means for transporting the wafer 400 is not limited thereto. The memory transporter 210 can move in the vertical direction and the horizontal direction. The memory transporter 210 includes: a support 211 that can rotate about the vertical axis; and a tray 212, which has, for example, an elongated plate shape, and the other end is supported by the support 211 such that one end in the length direction protrudes in the horizontal direction. When replacing the wafer 400 in the magazine 300, first, the memory transporter 210 performs an operation for transporting the wafer 400 from the detector 100 to the magazine 300. Specifically, it operates in the following order: (1) move in the vertical direction so that the height of the tray 212 becomes a height suitable for taking out the wafer 400 in the detector 100; (2) rotate the tray 212 toward the detector 100 side; (3) move horizontally toward the detector 100 side to hold the wafer 400 in the detector 100 on the tray 212; (4) move horizontally in the opposite direction of the detector 100 to take out the wafer 400 from the detector 100; (5) rotate the tray 212 toward the magazine 300 side; (6) move in the vertical direction so that the height of the tray 212 becomes a height suitable for accommodating the wafer 400 in the magazine 300; (7) move horizontally toward the magazine 300 side to accommodate the wafer 400 in the magazine 300; (8) move horizontally in the opposite direction of the magazine 300 to withdraw the tray 212 from the magazine 300, etc. This order is just an example, and various changes can be made, such as reversing the order of (1) and (2), or reversing the order of (6) and (7).

[0042] Next, second, the memory transporter 210 performs an operation for transporting the wafer 400 from the magazine 300 to the detector 100. This order is similar to the operation for transporting the wafer 400 from the detector 100 to the magazine 300, so the description thereof is omitted.

[0043] The magazine 300 stores a plurality of wafers 400 in a state taken off from the detector 100. In the memory device 1 of the present embodiment, a temperature control mechanism (cooling mechanism 310) is also provided in the magazine 300. The temperature control mechanism provided in the magazine 300 will be described later.

[0044] The air-conditioning control mechanism 500 has the following structure: separating the space from the external air, and flowing dry air, rare gas, inert gas, etc. without water into the space decompressed by sucking air from the outside with an exhaust fan, thereby replacing the gas phase atmosphere in the space with dry air, rare gas, inert gas, etc. The reasons for replacing the gas phase atmosphere in the detector 100, the memory transfer system 200, and the magazine 300 with dry air, rare gas, inert gas, etc. without water by the air-conditioning control mechanism 500 will be described later.

[0045] Figure 3 is a schematic diagram showing a block diagram of the memory device 1 composed of the detector 100, the memory transfer system 200, and the magazine 300 described with reference to Figure 1 FIG.

[0046] As described above, in the memory device 1 of the present embodiment, the controller 111-1 that controls the writing of data to the NAND chips formed on the wafer 400 and the reading of data from the NAND chips is arranged on the printed circuit board PCB of the probe card 110 as one of the devices 111. A plurality of controllers 111-1 can be arranged. That is, all the NAND chips on the wafer 400 can be controlled by one controller 111-1, or all the NAND chips on the wafer 400 can be controlled by a plurality of controllers 111-1. In Figure 3 FIG., an example is shown in which the buffer memory 111-2 for temporarily storing the written data and the read data is arranged on the printed circuit board PCB of the probe card 110 as one of the devices 111 in the same way as the controller 111-1. The buffer memory 111-2 can also be built into the controller 111-1.

[0047] The controller 111-1 is in electrical connection with the NAND chips of the wafer 400 by contacting the pad electrodes 410 of the wafer 400 on the stage 120 through the probes 115 of the probe card 110. The controller 111-1 can control the writing of data to the NAND chips and the reading of data from the NAND chips according to a request from the host 2. In addition, the wafer 400 in the detector 100 can be replaced with the wafer 400 stored in the memory transfer system 200 and the magazine 300.

[0048] In addition, the memory device 1 has a control unit 10. The control unit 10 includes, for example, an air-conditioning control system 11, a temperature control system 12, a drive control system 13, and an interface control system 14, and controls the overall operation of the memory device 1. Each control system of the control unit 10 is implemented, for example, by a processor executing firmware. The air-conditioning control system 11 controls the air-conditioning control mechanism 500. The temperature control system 12 uniformly controls the temperature control mechanisms (heating and cooling mechanism 112, cooling mechanism 113) in the probe card 110, the temperature control mechanism (heating and cooling mechanism 121) in the stage 120, and the temperature control mechanism (cooling mechanism 310) in the magazine 300. The drive control system 13 controls the drive unit 130 and the memory conveyor 210. The interface control system 14 controls the communication between the host 2 and the probe card 11. In addition, based on the control result of this communication, the interface control system 14 controls the air-conditioning control system 11, the temperature control system 12, and the drive control system 13.

[0049] Writing data to the NAND chips of the wafer 400 and reading data from the NAND chips are preferably performed at a high temperature above normal temperature (for example, 75 °C, but 85 °C or lower, for example). More specifically, when writing / reading data to / from cells in the NAND chips, the higher the temperature, the deeper the energy level at which electrons are trapped in the charge storage layer of the cells and the more stable they become. Therefore, the deviation of noise per electron is reduced. Therefore, a high temperature is preferred. On the other hand, in order to store data on the NAND chips for a long time, a low temperature below normal temperature (for example, 0 °C or lower) is preferred. More specifically, by suppressing phonon scattering of the charges accumulated in the NAND chips, the charge retention time can be extended. Therefore, the temperature when storing the wafer 400 is preferably low. In addition, the device 111 mounted on the probe card 110 preferably operates at a temperature below the threshold. Thus, when the wafer 400 is used as a memory, various temperature controls are required in the memory device 1. Therefore, the memory device 1 of the present embodiment is provided with temperature control mechanisms in the detector 100, the memory transfer system 200, and the magazine 300, respectively, and appropriate temperature control is performed for the memory device 1 as a whole. Hereinafter, this will be described in detail.

[0050] First, the temperature control mechanism provided in the detector 100 will be described.

[0051] As described above, in the detector 100, temperature control mechanisms are provided in the probe card 110 and in the stage 120.

[0052] In the stage 120 that holds the wafer 400, a heating and cooling mechanism 121 is provided (see Figure 1) The heating and cooling mechanism 121 is used to make the temperature inside the wafer 400 electrically connected to the probe card 110 on the stage 120 as uniform as possible. The heating and cooling mechanism 121 is a temperature control mechanism using, for example, electric heating and cooling pipes. In order to control the temperature of the wafer 400 using the stage 120, in the memory device 1, temperature control regions are set for each of a plurality of different regions smaller than the wafer 400 in area ratio, for example, each NAND chip region in the wafer 400, and different temperature controls are performed respectively.

[0053] Figure 4 It is a diagram for explaining an example of setting a temperature control region related to the stage 120 in the memory device 1 of the present embodiment.

[0054] Figure 4 (A) shows the upper surface of the wafer 400 and shows an example of formation of one NAND chip 420 in the wafer 400. On the other hand, Figure 4 (B) shows the upper surface of the stage 120 holding the wafer 400 and shows an example of setting a temperature control region a1 related to the stage 120.

[0055] As Figure 4 shown, in the memory device 1 of the present embodiment, for example, a plurality of temperature control regions a1 are set on the stage 120 in a one-to-one positional correspondence with a plurality of NAND chips 420 formed on the wafer 400 placed on the stage 120. The plurality of temperature control regions a1 may also be set, for example, in a positional correspondence such that two or more NAND chips 420 correspond to one temperature control region a1. In addition, the number of NAND chips 420 corresponding to the temperature control region a1 retrieval may also be different in all the temperature control regions a1.

[0056] Figure 5 It is a diagram showing a structural example of the heating and cooling mechanism 121 provided in the stage 120 in order to control the temperature of each temperature control region a1 set as shown in, for example, Figure 4 shown.

[0057] The cooling mechanism of the heating and cooling mechanism 121 has, for example, a structure in which the refrigerant b1 flows from one of the two cooling pipes 1211 to the other via the cooling branch pipe 1212. The refrigerant b1 is water or liquid nitrogen cooled by electronic cooling. The cooling branch pipe 1212 is configured to be able to cool the wafer 400 on the stage 120 for each temperature control region a1 set on the stage 120. The cooling performed by the cooling branch pipe 1212 is controlled according to the inflow of the refrigerant b1. In order to control the inflow rate of the refrigerant b1, an electronically controlled motor valve 1213 and a flow meter 1214 are provided near, for example, the injection port of the cooling branch pipe 1212.

[0058] On the other hand, the heating mechanism of the heating and cooling mechanism 121 is constituted by, for example, a heating wire 1215, and the heating wire 1215 is arranged so as to be able to heat the wafer 400 on the stage 120 for each temperature control region a1 set on the stage 120. The heating of the heating wire 1215 can be controlled, for example, by a switch for switching the presence or absence of heating and a variable resistor for adjusting the calorific value.

[0059] In addition, as will be described in detail later, the heating and cooling mechanism 121 of the stage 120 configured in this way is controlled by, for example, a controller 111-1 arranged on the probe card 110. A thermometer capable of outputting temperature data to the I 2 C bus is provided in the stage 120. In addition, a thermometer may also be provided in the wafer 400.

[0060] A communication path capable of transmitting the temperature measured by the thermometer provided in the stage 120 or the wafer 400 to the controller 111-1 is provided between the probe card 110 and the stage 120. The controller 111-1 controls the heating and cooling mechanism 121 of the stage 120 in cooperation with the control unit 10 based on the temperature measured by the thermometer provided in the stage 120 or the wafer 400. When there are a plurality of controllers 111-1, either one of them may be responsible for controlling the heating and cooling mechanism 121, or a plurality of controllers 111-1 may cooperate to control the heating and cooling mechanism 121. The control of the temperature control mechanism (heating and cooling mechanism 112, cooling mechanism 113) provided in the probe card 110 described later is also executed by the controller 111-1. That is, the temperature control mechanism in the detector 100 is centrally controlled by the controller 111-1. An apparatus for centrally controlling the temperature control mechanism in the detector 100 may be separately prepared from the controller 111-1 and arranged on the probe card 110. Alternatively, a function for centrally controlling the temperature control mechanism in the detector 100 may be incorporated in an existing device other than the controller 111-1.

[0061] In addition, Figure 5Also shown together therein are the lifting pin 131 and the actuator 132 of the driving unit 130. The lifting pin 131 is a component for being inserted into a hole portion provided on the stage 120 and moving the stage 120 in the vertical direction or the horizontal direction. The actuator 132 can move the stage 120 in the vertical direction or the horizontal direction by moving the lifting pin 131 in the vertical direction or the horizontal direction. The movement in the horizontal direction is performed to align the pad electrodes 410 of the wafer 400 with the probes 115 of the probe card 110. On the other hand, the movement in the vertical direction is performed to bring the pad electrodes 410 of the wafer 400 into contact with the probes 115 of the probe card 110 or to separate the pad electrodes 410 in the contact state from the probes 115.

[0062] Figure 6 It represents, for example, Figure 5 a diagram showing a configuration example of the heating and cooling mechanism 121 configured as shown in the stage 120.

[0063] Figure 6 (A) shows the upper surface of the wafer 400 and represents a formation example of the NAND chip 420 in the wafer 400. On the other hand, Figure 6 (B) shows the upper surface of the stage 120 holding the wafer 400 and shows a configuration example of the heating and cooling mechanism 121 in the stage 120.

[0064] Refer to Figure 5 The cooling branch pipe 1212 for cooling and the heating wire 1215 for heating included in the heating and cooling mechanism 121 described can also be arranged as shown in Figure 6 (B) such that they do not necessarily pass through all the temperature control regions a1. For example, the temperature of the target temperature control region a1 can also be controlled using one or more cooling branch pipes 1212 or one or more heating wires 1215 in the vicinity.

[0065] Figure 7 It is a diagram for explaining an example of temperature control of the heating and cooling mechanism 121 provided on the stage 120.

[0066] Figure 7 (A) shows an example of a state where there is temperature non-uniformity in the wafer 400 on the stage 120. Specifically, it shows a state where the temperature at the central portion of the wafer 400 is high and the temperature decreases from the central portion toward the ends.

[0067] On the other hand, Figure 7 (B) shows an example of temperature control based on the heating and cooling mechanism 121 implemented when the wafer 400 is in the state shown in Figure 7 (A).

[0068] In this case, in order to equalize the temperature, the central portion of the wafer 400 is cooled by flowing coolant b1 through the cooling branch pipe 1212 disposed in the central portion, and the end portion of the wafer 400 is heated by causing the heating wire 1215 disposed at the end portion to generate heat. At this time, the flow rate of the refrigerant b1 to the cooling branch pipe 1212 is controlled to be larger the closer it is to the center and smaller the farther it is from the center. On the contrary, the calorific value of the heating wire 1215 is controlled to be smaller the closer it is to the center and larger the farther it is from the center.

[0069] Thus, in the memory device 1 of the present embodiment in which the heating and cooling mechanism 121 is provided on the stage 120, it is possible to control the temperature inside the wafer 400 on the stage 120 to be uniform. In addition, in Figure 7 In order to facilitate understanding of the description, a state in which the temperature of the central portion of the wafer 400 rises and the temperature inside the wafer 400 becomes non-uniform is shown, but the non-uniformity of the temperature inside the wafer 400 can occur in various states depending on the access status of the NAND chip 420 and the like. Regardless of the state in which the temperature non-uniformity occurs, in the memory device 1 of the present embodiment in which a plurality of temperature control regions a1 are set on the stage 120, the temperature inside the wafer 400 can be appropriately equalized.

[0070] In addition, the cooling mechanism 310 of the magazine 300 will be described later, but the wafer 400 stored in the magazine 300 is cooled to a low temperature below the normal temperature suitable for long-term data storage. In contrast, writing data to the NAND chip 420 and reading data from the NAND chip 420 are preferably performed at a high temperature above the normal temperature. In the memory device 1 of the present embodiment in which the heating and cooling mechanism 121 is provided on the stage 120, when replacing the wafer 400 inside the detector 100, before electrically connecting the low-temperature wafer 400 transported from the magazine 300 to the probe card 110, it can be heated to a temperature suitable for writing data to the NAND chip 420 or reading data from the NAND chip 420. In addition, damage to both the probe 150 of the probe card 110 and the pad electrode 410 of the wafer 400 during contact can be prevented.

[0071] In addition, in the memory device 1 of the present embodiment in which the heating and cooling mechanism 121 is provided on the stage 120, conversely, when replacing the wafer 400 in the detector 100, after electrically disconnecting the wafer 400 on the stage 120 maintained at a temperature above room temperature from the probe card 110 and before conveying it to the stocker 300, it may be cooled to a temperature below room temperature on the stage 120, for example. By storing the wafer 400 cooled on the stage 120 in the stocker 300, the temperature inside the stocker 300 will rise temporarily, and it is possible to prevent the influence on other wafers 400 inside the stocker 300. In addition, a cooling mechanism may be provided in the memory transfer system 200 interposed between the detector 100 and the stocker 300, and this cooling mechanism is used to cool the wafer 400 maintained at a temperature above room temperature on the stage 120 of the detector 100 to a temperature below room temperature.

[0072] As a temperature control mechanism inside the probe card 110, a heating and cooling mechanism 112, a cooling mechanism 113, and a heat insulating material 114 are provided (refer to Figure 1 ).

[0073] The heating and cooling mechanism 112 is, for example, a temperature control mechanism that uses the same electric heating and cooling tubes as the heating and cooling mechanism 121 of the stage 120. Since it can be the same as the heating and cooling mechanism 121 of the stage 120, the description of its structure is omitted. It may also be configured differently from the heating and cooling mechanism 121 of the stage 120.

[0074] In order to make the temperature of the probe card 110 substantially the same as the temperature of the wafer 400, more specifically, in order to make the temperature of the probe 115 substantially the same as the temperature of the pad electrode 410, the heating and cooling mechanism 112 is provided, for example, on the lower surface side inside the probe card 110 facing the wafer 400 on the stage 120.

[0075] Thereby, the memory device 1 of the present embodiment can stabilize the electrical connection between the wafer 400 and the probe card 110 by bringing the probe 115 into contact with the pad electrode 410, etc.

[0076] In addition, the cooling mechanism 113 of the probe card 110 is, for example, a temperature control mechanism using a heat dissipation or cooling pipe. In order for the device 111 disposed on the printed circuit board PCB of the probe card 110 to operate at a temperature below the threshold value, in other words, in order for the temperature of the device 111 not to exceed the threshold value, the cooling mechanism 113 is disposed, for example, on the upper surface side within the probe card 110. The control of the cooling mechanism 113 is executed by the controller 111-1 which is one of the devices 111. The controller 111-1 controls the cooling mechanism 113 based on the temperature of the controller 111-1 measured by itself and the temperatures measured by other devices on the printed circuit board PCB. Similar to the heating and cooling mechanism 112 and the heating and cooling mechanism 121 of the stage 120, the cooling mechanism 113 can also perform temperature control for each preset temperature control region. This temperature control region may correspond to the temperature control region a1 set on the stage 120, or may be set independently.

[0077] Thereby, the memory device 1 of the present embodiment can enable the device 111 disposed on the probe card 110 to continuously operate in an appropriate environment.

[0078] In addition, on the probe card 110, a heat insulating material 114 with a high thermal resistance is provided, for example, between the upper surface where the device 111 is disposed and the lower surface, for example, facing the wafer 400. By providing the heat insulating material 114, the memory device 1 of the present embodiment insulates the inside of the probe card 110 on the upper surface side and the lower surface side, and can maintain different temperatures respectively. More specifically, for example, the upper surface side can be maintained at a temperature suitable for the device 111, and for example, the lower surface side can be maintained at a temperature substantially consistent with the temperature of the wafer 400 on the stage 120.

[0079] Figure 8 It is a diagram for explaining an example of a mechanism for the device 111 (controller 111-1) on the probe card 110 in the memory device 1 to uniformly implement the temperature control of the detector 100.

[0080] A ceramic printed circuit board PCB1101 with a high heat dissipation effect is provided on the probe card 110. Some of the plurality of devices 111 disposed on the upper surface of the ceramic printed circuit board PCB1101, for example, are equipped with thermometers 1111 for measuring the temperature of the device 111. The controller 111-1 is also equipped with a thermometer 1111. First, based on the temperatures measured by these thermometers 1111 including the thermometer 1111 provided by itself, the controller 111-1 performs temperature control based on the cooling mechanism 113 so as to keep the temperature of the device 111 below the threshold value. As described above, the controller 111-1 can perform temperature control of the cooling mechanism 113 for each preset temperature control region. In addition, the thermometer 1111 for measuring the temperature of the device 111 may also be outside the device 111.

[0081] On the lower surface of the ceramic printed circuit board PCB1101, for example, a probe unit 1103 is disposed with an interposer 1102 interposed therebetween. Probes 115 are provided at the front ends of the probe unit 1103. Further, a thermometer 1104, for example, capable of outputting temperature data to the controller 111-1 is provided on the lower side thereof.

[0082] Further, as described above, a thermometer (430, 1201) is provided in at least one of the wafer 400 and the stage 120. Second, the controller 111-1 performs temperature control of the heating / cooling mechanism 112 of the probe card 110 and the heating / cooling mechanism 121 of the stage 120 based on the temperature measured by the thermometer 1104 provided in the probe card 110 and the temperature measured by the thermometer 430 provided in the wafer 400 or the temperature measured by the thermometer 1201 provided in the stage 120, so that the temperature of the probe 115 and the temperature of the pad electrode 410 are substantially the same. And the controller 111-1 performs temperature control of the heating / cooling mechanism 121 of the stage 120 to make the temperature in the wafer 400 uniform.

[0083] That is, in the memory device 1 of the present embodiment, the device 111 disposed on the probe card 110 can monitor the temperatures of a plurality of parts of the probe card 110, the stage 120, and the wafer 400 on the stage 120.

[0084] Further, in Figure 8 what is formed on the wafer 400 denoted by the symbol c1 is an alignment mark used in the alignment of the probe 115 of the probe card 110 with respect to the pad electrode 410. Further, in Figure 8 the X direction is the direction of the word line, and the Y direction is the direction of the bit line. The horizontal movement of the stage 120 holding the wafer 400 by the driving unit 130 is performed based on this alignment mark. A camera for detecting a representative position (here, the alignment mark c1) on the wafer 400 may also be provided on the probe card 110. Based on the information from this camera, the drive control system 13 can more accurately identify the reference position and can perform precise alignment.

[0085] Figure 9 is a view showing a plurality of probes 115 disposed on the first surface 110A of the probe card 110.

[0086] In Figure 9 it is exemplified that the same number of probes 115 as the number of pad electrodes 410 of all the NAND chips 420 of the wafer 400 are disposed on the first surface 110A of the probe card 110.

[0087] In this case, the probes 115 of the probe card 110 are in contact with all the pad electrodes 410 of all the NAND chips 420 in the wafer 400, and all the NAND chips 420 can be controlled by the controller 111-1.

[0088] Figure 10 It is a diagram showing a plurality of controllers 111-1 arranged on the second surface 110B of the probe card 110.

[0089] In Figure 10 an example is shown in which 16 controllers 111-1 (controllers 111-1-1, 111-1-2..., 111-1-16) are arranged. When 1024 NAND chips 420 are included in one wafer 400 and 16 controllers 111-1 are arranged on the second surface 110B of the probe card 110, each controller 111-1 can control 64 NAND chips 420 via the probes 115.

[0090] Figure 11 It is a diagram for explaining an operation example of the device 111 installed in the detector 100.

[0091] Here, it is assumed that a plurality of NAND chips 420 formed on the wafer 400 are controlled by a plurality of controllers 111-1. That is, it is assumed that a plurality of controllers 111-1 are arranged on the probe card 110.

[0092] A connector 111-3 for connecting the probe cable 111A is arranged on the probe card 110. The probe cable 111A is used for externally connecting the probe card 110 to the host 2 (refer to Figure 3 ). An interface switch (e.g., a PCIe (registered trademark) switch) 111-4 for exclusively and selectively connecting the connector 111-3 to one of the plurality of controllers 111-1 is arranged on the probe card 110. The interface switch 111-4 appropriately switches, so that, for example, when a data read request is made from the host 2, the read request for the data is transmitted to the controller 111-1 that controls the corresponding NAND chip 420. The controller 111-1 that receives the request reads the data from the NAND chip 420 and sends the read data to the host 2. The data sent from the controller 111-1 is relayed to the connector 111-3 through the interface switch 111-4 and transmitted to the host 2 through the riser cable 111A.

[0093] In the memory device 1 of the present embodiment, the temperatures of the multiple devices 111 arranged on the probe card 110 are maintained below a threshold value by the cooling mechanism 113 of the probe card 110. In addition, on the detector 100, various LSI chips and semiconductor components such as FPGA, relays, and capacitors can be installed in addition to the controller 111-1 and the interface switch 111-4.

[0094] Next, the cooling mechanism 310 provided in the magazine 300 will be described.

[0095] Figure 12 It is a diagram showing a first example of the cooling mechanism 310.

[0096] In the magazine 300, gates 301 that open and close when taking out and putting in the wafers 400 are provided in the number of wafers 400 that can be stored. When taking out the wafers 400 from the magazine 300 or storing the wafers 400 in the magazine 300, any one of the multiple gates 301 is selectively opened and closed so that the cold air inside the magazine 300 does not escape to the outside. In addition, it can also be configured such that there is one gate 301 and the entire memory (wafer 400) storage stored inside is moved up and down inside.

[0097] In the first example, an air inlet 311 for sending in cooling air d1 and an air outlet 312 for discharging the cooling air d2 flowing through the magazine 300 are provided in the magazine 300. The cooling air d1 is, for example, air cooled at high pressure. The cooling mechanism 310 of the magazine 300 in this example closes the entrances and exits of the wafers 400 by the gates 301, continuously conveys the cooling air d1 from the air inlet 311, and continuously fills the inside of the magazine 300 with the cooling air d1 maintained below the normal temperature, thereby cooling the entire magazine 300. That is, the wafers 400 inside the magazine 300 are cooled to a temperature suitable for long-term data storage.

[0098] Figure 13 It is a diagram showing a second example of the cooling mechanism 310.

[0099] In the second example, a cooling pipe 313 through which a refrigerant e1 flows is provided on the side peripheral wall of the magazine 300 so as to cover, for example, the entire side of the magazine 300. The refrigerant e1 is water or liquid nitrogen cooled by electronic cooling. The cooling mechanism 310 of the magazine 300 in this example closes the entrances and exits of the wafers 400 by the gates 301, allows the refrigerant e1 to flow through the cooling pipe 313 provided on the peripheral wall of the magazine 300, cools the air inside the magazine 300, and thereby cools the entire magazine 300. That is, the wafers 400 inside the magazine 300 are cooled to a temperature suitable for long-term data storage. In addition, the cooling pipe 313 can also be located inside the magazine 300.

[0100] In addition to using the cooling air d1 and the refrigerant e1, for example, an electronic cooling mechanism using a Peltier element may be provided on a part of the wafer 400 supported in the reservoir 300, a part connected to the support part, or the entire reservoir 300 to cool the wafer 400 in the reservoir 300.

[0101] Thus, in the memory device 1 of the present embodiment in which the cooling mechanism 310 is provided in the reservoir 300, the wafer 400 can be stored in the reservoir 300 while maintaining a low temperature below the normal temperature suitable for long-term data storage.

[0102] Next, the air-conditioning control mechanism 500 (refer to Figure 1 ) will be described.

[0103] As described above, the wafer 400 in the reservoir 300 is cooled to a low temperature below the normal temperature. Therefore, in order to replace the wafer 400 in the detector 100 with the wafer 400 in the reservoir 300, when the wafer 400 is taken out from the reservoir 300 and transported to the detector 100, water vapor in the air in the memory transport system 200 may condense (i.e., dew may form) on the low-temperature wafer 400 and the memory transporter 210 that transports the wafer 400. To prevent this dew formation, in the memory device 1 of the present embodiment, an air-conditioning control mechanism 500 is provided to replace the gas-phase atmosphere in the memory transport system 200 with dry air, rare gas, inert gas, etc. that do not contain water.

[0104] The air-conditioning control mechanism 500 replaces the gas-phase atmosphere not only in the memory transport system 200 but also in the detector 100 or the reservoir 300 with dry air, rare gas, inert gas, etc. that do not contain water. Thereby, in the memory device 1 of the present embodiment, dew formation on the wafer 400 can be almost completely prevented. In addition, since it is preferable that there is no oxygen in the space for processing the wafer 400 in addition to water, it is preferable to replace the gas-phase atmosphere in the detector 100, the memory transport system 200, and the reservoir 300 with rare gas or inert gas, etc.

[0105] In addition, it is preferable that not only in the reservoir 300 but also in the memory transport system 200 that transports the wafer 400 maintained at a high temperature above the normal temperature in the detector 100 to the reservoir 300 is cooled. As described above, a cooling mechanism may also be provided in the memory transport system 200.

[0106] Furthermore, the reservoir 300 is cooled to maintain the charge retention characteristics for a long time. This temperature is usually room temperature, but since the charge retention characteristics increase with cooling, it can also be assumed to be below 0°C. However, at low temperatures below 0°C, electrical side effects such as short circuits between wirings occur due to condensation of water in the atmosphere. From this viewpoint, it is also preferable to replace the gas-phase atmosphere in the reservoir 300 with dry air, rare gases such as argon, or inert gases such as nitrogen that do not contain water.

[0107] Thus, in the memory device 1 of the present embodiment provided with the air-conditioning control mechanism 500 as a kind of temperature control mechanism, condensation on the wafer 400 and the memory transporter 210 can be prevented.

[0108] Figure 14 It is a flowchart showing an example of the temperature control during the replacement of the wafer 400 performed by the memory device 1 of the present embodiment.

[0109] The memory device 1 electrically disconnects the wafer 400 on the stage 120 from the probe card 110 by the drive unit 130 (S1). The memory device 1 cools the wafer 400 electrically disconnected from the probe card 110 on the stage 120 (S2). At this time, the controller 111-1 obtains the temperature from the thermometer (430, 1201) through the I 2 C bus, for example. The memory device 1 transports the wafer 400 cooled to below room temperature from the detector 100 to the reservoir 300 through the memory transport system 200 (S3).

[0110] Next, the memory device 1 transports the wafer 400 to be accommodated in the detector 100 from the reservoir 300 to the detector 100 through the memory transport system 200 due to the replacement of the wafer 400 taken out from the detector 100 (S4). The memory device 1 heats up the wafer 400 electrically connected to the probe card 110 on the stage (S5). At this time, the controller 111-1 obtains the temperature from the thermometer (430, 1201) through the I 2 C bus, for example. The memory device 1 electrically connects the wafer 400 to the probe card 110 by the drive unit 130 (S6), and the wafer 400 is heated up to above room temperature suitable for writing data and reading data for the NAND chip 420.

[0111] As described above, the memory device 1 of the present embodiment provided with temperature control mechanisms in the detector 100, the memory transport system 200, and the reservoir 300 respectively can appropriately perform various temperature controls related to the wafer 400.

[0112] In addition, the heating and cooling mechanism 121 provided on the stage 120 of the detector 100 can be used for refreshing the wafer 400. Refresh is a process for restoring cells whose deviation between cells has deteriorated due to read / write stress when writing or reading data to / from cells in a NAND chip. Through this process, the data retention function of the NAND chip is also restored. For example, in order to achieve the restoration of deterioration caused by annealing at about 300°C, the wafer 400 is heated on the stage 120, and refresh is performed. Therefore, using the suction port provided in the detector 100 and the supply mechanism of nitrogen, argon, helium, krypton, xenon, etc. provided in the detector 100, the inside of the detector 100 is sealed with these inert gases. That is, the water and concentration contained in the atmosphere are reduced. In addition, it can also be sealed with different atmospheres according to the division of regions inside the detector 100. In this way, by replacing the atmosphere with an inert gas and using the heating and cooling mechanism 121 provided on the stage 120, it is possible to prevent oxidation of the electrodes of the wafer 400. In other words, the memory device 1 of the present embodiment can also include a refresh mechanism in the detector 100 that heats the wafer 400 on the stage 120 and seals the periphery of the wafer 400 with an inert gas.

[0113] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalents.

[0114] Description of Reference Numerals

[0115] 1.. Memory device, 2… Host, 100… Detector, 110… Probe card, 111… Device, 112… Heating and cooling mechanism, 113… Cooling mechanism, 114… Heat insulation material, 115… Probe, 120… Stage, 121… Heating and cooling mechanism, 130… Driving unit, 200… Memory transfer system, 210… Memory transfer device, 300… Magazine, 310… Cooling mechanism, 400… Wafer, 410… Pad electrode, 420: NAND chip; 430: Thermometer inside the wafer; 500: Air conditioning control mechanism; 1104: Thermometer inside the probe card; 1111: Thermometer inside the device; 1201: Thermometer inside the stage.

Claims

1. A memory device, comprising: a control device configured to write data to or read data from a memory medium including a plurality of non-volatile memory chips; and a magazine configured to store a plurality of the memory media in a state of being detached from the control device, wherein the control device has a first temperature control mechanism configured to raise the temperature of the memory medium above a first temperature, and the magazine has a second temperature control mechanism configured to cool the memory medium below a second temperature lower than the first temperature.

2. The memory device according to claim 1, wherein the control device includes: a stage configured to hold the memory medium; a probe card facing the memory medium held by the stage and having a plurality of probes on a first surface of the facing side; and a driving unit configured to move at least one of the stage or the probe card, to bring a plurality of pad electrodes provided on a surface of the memory medium facing the probe card into contact with the plurality of probes, or to separate the plurality of pad electrodes in a contact state from the plurality of probes, wherein after the memory medium is heated above the first temperature on the stage by the first temperature control mechanism, the memory medium is brought into contact with the plurality of probes by the driving unit.

3. The memory device according to claim 2, wherein the first temperature control mechanism includes a plurality of temperature control mechanisms formed in the stage, and is capable of performing different temperature controls for each of a plurality of different regions of the memory medium having an area smaller than the area of the surface held by the stage.

4. The memory device according to claim 3, wherein the first temperature control mechanism maintains the temperature of each of the regions of the memory medium within a first range of temperatures by the plurality of temperature control mechanisms.

5. The memory device according to claim 4, wherein the plurality of different regions are regions in the memory medium respectively corresponding to the positions of the plurality of non-volatile memory chips.

6. The memory device according to any one of claims 2 to 5, wherein the first temperature control mechanism includes a temperature control mechanism formed with the first surface of the probe card as a control object.

7. The memory device according to any one of claims 2 to 5, wherein the probe card includes a plurality of semiconductor components disposed on a second surface facing the first surface, and the first temperature control mechanism includes a temperature control mechanism configured to cool the plurality of semiconductor components disposed on the second surface.

8. The memory device according to claim 7, wherein a heat insulating material is provided between the first surface and the second surface of the probe card.

9. The memory device according to claim 7, wherein the plurality of semiconductor components include at least one of a controller configured to control the non-volatile memory chips, an interface switch configured to selectively activate a plurality of the controllers, an FPGA, a relay, or a capacitor.

10. The memory device according to claim 7, At least one of the plurality of semiconductor components monitors at least one of the temperatures measured by a plurality of thermometers provided in the stage and the probe card.

11. The memory device according to claim 1 or 2, The second temperature control mechanism includes a cooling mechanism that uses cooling water, cooling air, or liquid nitrogen as a refrigerant.

12. The memory device according to claim 1 or 2, The second temperature control mechanism includes an electronic cooling mechanism using a Peltier element, and the electronic cooling mechanism is provided on the first part holding the memory medium, the second part connected to the first part, or the entire magazine.

13. The memory device according to claim 3, The control device has a refreshing mechanism that seals the periphery of the memory medium with a noble gas or an inert gas, and heats up the memory medium on the stage through the first temperature control mechanism.

14. The memory device according to claim 13, The noble gas or inert gas is one of nitrogen, argon, helium, krypton, or xenon.

15. The memory device according to claim 2, When the control device replaces the memory medium in contact with the plurality of probes from the first memory medium with the second memory medium in the magazine, the control device cools the first memory medium maintained at a temperature above the first temperature on the stage to a temperature below the first temperature through the first temperature control mechanism.

16. The memory device according to claim 2 or 15, When the control device replaces the memory medium in contact with the plurality of probes from the third memory medium with the fourth memory medium in the magazine, the control device heats up the fourth memory medium cooled to a temperature below the second temperature on the stage to a temperature above the first temperature through the first temperature control mechanism, and connects the plurality of pad electrodes of the fourth memory medium to the probe card through the drive unit.

17. The memory device according to claim 1 or 2, It further includes a transport system that transports the memory medium from the control device to the magazine or from the magazine to the control device. The first temperature is room temperature. The transport system has a third temperature control mechanism for adjusting the air in the transport system to prevent condensation when the memory medium cooled to a temperature below the second temperature is transported from the magazine to the control device.

18. The memory device according to any one of claims 1 to 5, The memory medium is a semiconductor wafer.

19. A control method for a memory device, the memory device comprising: a control device that heats a memory medium including a plurality of nonvolatile memory chips to a temperature above a first temperature, writes data to the memory medium placed on a stage, or reads data from the memory medium placed on the stage; And a magazine that cools and stores a plurality of the memory media in a state of being detached from the control device to a second temperature lower than the first temperature. The control method includes the following steps: When the control device replaces the memory medium placed on the stage from the first memory medium with the second memory medium in the magazine, Cool the first memory medium maintained at a temperature above the first temperature within the control device to a temperature below the first temperature; and Heat the second memory medium cooled to a temperature below the second temperature within the control device to a temperature above the first temperature and place it on the stage.

20. The control method of a memory device according to claim 19, The memory medium is a semiconductor wafer.

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