Method and apparatus for setting stable operating point and emi control of h-bridge output stage

Abstract

Apparatus and methods for establishing a stable operating point for an H-bridge with a center tap switch. The stable operating point enables circuits connected to the output of the H-bridge to operate under more ideal conditions. As a result, an H-bridge with a stable operating point will produce higher performance and / or energy savings. Since common mode is one of the largest sources of electromagnetic interference, the stable operating point in the H-bridge also suppresses EMI.

Description

[0001] Cross Reference to Related Applications

[0002] This application is related to and claims priority from U.S. Provisional Patent Application No. 62 / 905,375, filed September 24, 2019, under 35 U.S.C. § 119(e), entitled “Stable Operating Point and EMI Control for Setting H-Bridge Output Stage,” the entirety of which is hereby incorporated by reference into this application. TECHNICAL FIELD

[0003] The present invention relates to differential H-bridge circuits. More specifically, the present invention describes mid-switching for controlling common mode and setting a stable operating point in an H-bridge circuit. BACKGROUND

[0004] A differential signal is a method of electrically transmitting information using two complementary signals. The technology sends the same electrical signal as a differential signal pair, each pair of signals in its own conductor. The pair of conductors can be wires (usually twisted together) or traces on a circuit board. The receiving circuit responds to the electrical difference between the two signals, rather than the difference between a single wire and ground. The opposite technology is called single-ended signaling. Differential pairs are commonly found in printed circuit boards, twisted pair wires, and ribbon cables, and connectors.

[0005] A differential signal is a way of transmitting a differential signal from a transmitter to a receiver over a differential transmission line, e.g., over a pair of conductors, e.g., copper wires. A differential signal driver circuit drives a current through the transmission line in accordance with a drive signal. The current in the transmission line is referred to herein as the signal current. The drive signal can be provided, for example, by a voltage, a current, or any other suitable physical quantity.

[0006] A differential signal receiver circuit can include a resistive bridge connected across the differential output of the transmission line, i.e., between the two conductors of the transmission line at the end of the transmission line. Thus, the current injected into the transmission line by the differential signal driver circuit is converted into a voltage across the resistive bridge at the end of the transmission line. This voltage can be further processed or analyzed by the differential signal receiver circuit or by a circuit connected to the differential signal receiver circuit.

[0007] The drive signal is typically a bi-level signal, i.e., a binary signal. However, the differential signal driver circuit can in principle be capable of converting any kind of waveform of the drive signal into a corresponding waveform of the signal current. In other words, the differential signaling driver circuit can be applicable to continuous, i.e., analog, and discrete, i.e., digital, drive signals.

[0008] A differential signal of low voltage amplitude can be performed in a low voltage manner when superimposed on a common mode DC voltage. For example, a differential signal of a maximum amplitude of 0.5 V or less (e.g., 350 mV) can be applied on a common mode voltage of 1.5 V or less (e.g., 1.2 V or less), e.g., 0.9 V or less (e.g., 0.4 V). This is generally referred to as a low voltage differential signal.

[0009] Low voltage differential signaling (LVDS) is a technical standard that specifies the electrical characteristics of a differential serial signal standard, but it is not a protocol. LVDS uses inexpensive twisted pair copper cable to operate at low power and can operate at extremely high speeds. LVDS is only a physical layer specification; many data communication standards and applications use it and add a data link layer defined in the OSI model on top of it.

[0010] As described above, LVDS is a differential signal system, meaning that it transmits information in the form of a voltage difference on a pair of wires; the voltages of the two wires are compared at the receiver. In LVDS, a differential signal is transmitted from the transmitting end, and the two signal lines are terminated to each other through a resistor at the receiving end. Binary data of "0" or "1" is generated and transmitted by changing the current direction of the differential signal. At the receiving end, a differential amplifier determines the signal value by sensing the high voltage side of the resistor.

[0011] One of the advantages of LVDS is the reduction in electromagnetic radiation. This is because the current flows in opposite directions through the pair of wires used to transmit the signal, and the binary data "0" and "1" differ only in the direction of the current and are equal in the amount of current. In addition, although the high side of the signal line changes depending on the signal value "0" or "1", the voltage generated by the resistor at the end of the wire does not change. This also reduces the amount of electromagnetic radiation.

[0012] However, the amount of electromagnetic emission is reduced only when the differential signal on the wire is substantially in an ideal state. In reality, when the differential signal is switched, the voltage of the signal can change unevenly, or the direction of the current flowing through the wire does not change smoothly. They are mainly caused by the on / off timing difference in the plurality of transistors used to generate the differential signal.

[0013] According to variations in the manufacturing precision of a printed circuit and variations in materials, a delay time difference occurs between the two transmission lines. When the bit rate is low, the delay time difference between the two transmission lines is not so problematic. The higher the bit rate, the more distorted the waveform of the transmitted signal becomes.

[0014] Specifically, if high-speed transmission or higher speed transmission is performed, the time width of the signal waveform becomes short, and a delay time difference of more than 1 unit interval (UI: one period of a bit clock) can occur over a movement distance of about several tens of centimeters on a printed circuit board. As a result, the margin of the time delay difference between the differential signals decreases, and it is difficult to correctly receive the data signal. As a preventive measure, a technique of detecting and then compensating for the skew of the differential signals at the receiver is used.

[0015] If the delay time difference between the transmission paths for transmitting the differential signals is large in the above-described related art, it is difficult to maintain the differential state between the differential signals received at the receiver. Therefore, it is difficult to detect the skew (phase difference) of the differential signals. As a result, it is difficult to compensate for the skew of the differential signals, and unstable operation can occur in the subsequent circuit of the receiver.

[0016] The inventors of the present invention have recognized that there has long been a need to control common mode in a robust and energy-efficient manner. This is achieved by a common mode feedback method that is versatile and applicable to a variety of applications.

[0017] This overview is intended to provide a summary of subject matter of the present patent application. The present invention is not intended to provide an exclusive or exhaustive explanation. By comparing these systems with some aspects of the present invention (as described in the remainder of the application with reference to the drawings), the skilled person will clearly see further limitations and disadvantages of the conventional methods. SUMMARY

[0018] Apparatuses and methods for establishing a stable operating point for an H-bridge having a center shunt switch. The stable operating point enables a circuit connected to the output of the H-bridge to operate under more ideal conditions. As a result, the H-bridge with the stable operating point will produce higher performance and / or energy savings. Since common mode is one of the largest sources of electromagnetic interference, the stable operating point in the H-bridge can also suppress EMI.

[0019] According to one aspect, a circuit for setting a stable operating point includes: a first half-bridge having a first output; a second half-bridge having a second output; a shunt switch in electrical communication with the first and second outputs; a common mode voltage source; a first resistor and a first switch disposed between the first output and the common mode voltage source; and a second resistor and a second switch disposed between the second output and the common mode voltage source.

[0020] According to another aspect, a system for setting a stable operating point in an H-bridge circuit includes: an IDAC; a modulator in electrical communication with the IDAC; and an H-bridge including: a first half-bridge having a first output; a second half-bridge having a second output; a shunt switch in electrical communication with the first and second outputs.

[0021] According to another aspect, a system for setting a stable operating point includes an IDAC; an integrator coupled to the IDAC configured to receive an IDAC output and a feedback signal; a quantizer coupled to the integrator configured to receive and integrate the integrator output and generate a quantized signal; and an H-bridge configured to receive the quantized signal, including a first half-bridge having a first output; a second half-bridge having a second output; and a means for stabilizing an operating point of the H-bridge. In some embodiments, the means for stabilizing an operating point includes a shunt switch in electrical communication with the first and second outputs.

[0022] In some embodiments, the system includes a common mode voltage source; a first resistor and a first switch disposed between the first output and the common mode voltage source; and a second resistor and a second switch disposed between the second output and the common mode voltage source.

[0023] The figures show example common mode stabilization of differential switched output circuits and configurations. Variations of these circuits, such as changing the position of certain elements in the circuits, adding or removing these elements, do not go beyond the scope of the invention. The power stages, configurations, and supplemental devices shown are intended to be supplemental to the support in the detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0024] The disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that various features are not necessarily drawn to scale and are used to illustrate only one illustrative example. Where explicitly or implicitly shown to scale, it is merely intended to provide an illustrative example. In other embodiments, the dimensions of various features can be arbitrarily increased or decreased for clarity.

[0025] For a fuller understanding of the nature and advantages of the present invention, reference should be made to the following detailed description together with the accompanying drawings, in which:

[0026] Figure 1A An exemplary NPC 3-level half-bridge is shown in accordance with some embodiments of the disclosure provided herein;

[0027] Figure 1B An example graph illustrating the output of an NPC 3-level half-bridge in accordance with some embodiments of the disclosure provided herein is shown;

[0028] Figure 1C An example graph illustrating the output of an NPC 3-level half-bridge during a PWM period in accordance with some embodiments of the disclosure provided herein is shown;

[0029] Figure 2A Exemplary signaling in an FC 3-level half-bridge in accordance with some embodiments of the disclosure provided herein is shown;

[0030] Figure 2B An exemplary FC 3-level half bridge is shown in accordance with some embodiments of the disclosure provided herein;

[0031] Figure 2C An example plot illustrating the output of a FC 3-level half bridge during PWM is shown in accordance with some embodiments of the disclosure provided herein;

[0032] Figure 3A An exemplary circuit showing current paths in accordance with some embodiments of the disclosure provided herein;

[0033] Figure 3B An exemplary circuit showing current paths in accordance with some embodiments of the disclosure provided herein;

[0034] Figure 3C An exemplary circuit showing current paths in accordance with some embodiments of the disclosure provided herein;

[0035] Figure 3D An exemplary circuit showing current paths in accordance with some embodiments of the disclosure provided herein;

[0036] Figure 4 An exemplary circuit showing common-mode free binary modulation in accordance with some embodiments of the disclosure provided herein;

[0037] Figure 5 An exemplary circuit showing common-mode shunt switch in accordance with some embodiments of the disclosure provided herein;

[0038] Figure 6 An exemplary circuit showing common-mode control in accordance with some embodiments of the disclosure provided herein;

[0039] Figure 7 An exemplary circuit showing common-mode control using intermediate switches in accordance with some embodiments of the disclosure provided herein;

[0040] Figure 8 An exemplary circuit showing common-mode control integrated with modulator in accordance with some embodiments of the disclosure provided herein;

[0041] Figure 9 An exemplary circuit showing common-mode control integrated with modulator having common-mode feedback (CMFB) in accordance with some embodiments of the disclosure provided herein;

[0042] Figure 10 An example plot of voltage input without CMFB is shown in accordance with some embodiments of the disclosure provided herein;

[0043] Figure 11An example plot of current input is shown, in accordance with some embodiments of the present disclosure provided herein;

[0044] Figure 12 An example circuit with a middle switch is illustrated, in accordance with some embodiments of the present disclosure provided herein. DETAILED DESCRIPTION

[0045] The present disclosure relates to differential H-bridge circuits. More specifically, the present disclosure describes a middle switch for controlling common mode and setting a stable operating point in an H-bridge circuit and mitigating EMI. In some embodiments, a middle switch network with common mode feedback (CMFB), modulator, and integrator is introduced in differential signal and other audio applications.

[0046] The following description and drawings are illustrative of certain illustrative embodiments of the present disclosure and are indicative, in a non-limiting sense, of the several alternatives which have been conceived of the principles of the present disclosure. The illustrative examples are not exhaustive of the many possible embodiments of the present disclosure. Other objects, advantages and novel features of the present disclosure will be set forth in the programs and in the drawings which are applicable in the circumstances.

[0047] Embodiments herein relate to a way to establish a very stable operating point of an H-bridge with a center-tapped switch. The stable operating point can allow a circuit connected to the H-bridge output to operate in more ideal conditions, thus improving performance and / or saving power. This stable operating point can also reduce EMI, as the common mode, which is one of the biggest sources of EMI, is well suppressed.

[0048] It is generally difficult to implement an output stage that meets all of the following: multi-level output; stable common mode at vdd / 2; and single voltage power supply, without external storage capacitor.

[0049] In the case of a 2-level switching stage, a conventional SW output stage has 2-level output levels: VDD or GND; the ripple current flowing into the filter inductor tends to be large.

[0050] In the case of a 3-level or multi-level implementation, there can be multiple ways to implement multi-level. One such technique can be a 3-level half-bridge with a common mode (CM) of the output stage at VDD / 2. This technique can require an external capacitor or multiple power supplies. Another such technique can be a 3-level H-bridge. In this technique, the CM can move between VDD-GND. The feedback amplifier can be affected by the large CM range and face design difficulties. The CM variation can introduce EMI.

[0051] Multi-level half bridges can be made in several different ways. One approach employs multiple power supplies that directly provide positive / negative / neutral signals to achieve a 3-level output. In digital art and applications, single-sided power supplies are preferred because designers cannot always expect multiple sets of power supplies. Single-sided implementations will be discussed in more detail below.

[0052] Figure 1A An exemplary neutral point clamped (NPC) 3-level half bridge is shown in accordance with some embodiments of the disclosure provided herein. The NPC 3-level half bridge 100 includes voltage dividing capacitors 110, diodes, and transistors in a network that provide a multi-level clamped output 120.

[0053] In one or more embodiments, the NPC 3-level half bridge 100 is a diode clamped multi-level inverter. The main purpose of this inverter is to use diodes and provide multiple voltage levels to a set of capacitors in series through different phases. Diodes transfer a limited amount of voltage, thereby reducing the stress on other electrical devices.

[0054] The maximum output voltage is half of the input DC voltage. This is the main drawback of diode clamped multi-level inverters. This problem can be solved by increasing the switches, diodes, and capacitors. These are limited to three levels due to capacitor balancing issues. This type of inverter provides high efficiency because all switching devices are used at the fundamental frequency, and it is a simple approach to back-to-back power transmission systems.

[0055] Figure 1B An exemplary chart illustrating the output of the NPC 3-level half bridge 100 in accordance with some embodiments of the disclosure provided herein is shown. The resulting output can be understood by those skilled in the art. In practice, the voltage dividing capacitors 110 produce a voltage ladder to produce positive / negative outputs of V dc / 2 on the multi-level clamped output 120.

[0056] Figure 1C An example chart illustrating the output 120 of the NPC 3-level half bridge 100 during PWM in accordance with some embodiments of the disclosure provided herein is shown. Figure 1C An example chart illustrating pulse width modulation (PWM) and the analog counterpart from a 2-level signaling system is illustrated.

[0057] As can be appreciated by those skilled in the art, in one or more embodiments, the present disclosure is readily applied to pulse width modulation (PWM) and class-D amplifiers. Pulse width modulation (PWM) or pulse duration modulation (PDM) is a method of reducing the average power delivered by an electrical signal by effectively dividing it into discrete portions.

[0058] The average of the voltage (and current) fed into a load is controlled by rapidly opening and closing a switch between the power source and the load. The longer the switch is open compared to the time it is closed, the higher the total power provided to the load. Together with maximum power point tracking (MPPT), it is one of the main methods of reducing the output of a solar panel to an output that a battery can utilize. PWM is particularly suitable for running inertial loads, such as electric motors, which are not easily affected by this discrete switching because their inertia causes them to react slowly. The PWM switching frequency must be high enough not to affect the load, that is, the synthesized waveform perceived by the load must be as smooth as possible.

[0059] The rate (or frequency) at which the power source must be switched can vary from load to load and application to application. For example, in an electric stove, several switches must be made per minute; in a dimmer, 120 Hz; in a motor driver, between a few kilohertz (kHz) and tens of kHz; and in audio amplifiers and computer power supplies, tens or hundreds of kHz.

[0060] The main advantage of PWM is that the power dissipation of the switching device is very low. When the switch is closed, there is almost no current, and when it is open and transmitting power to the load, there is almost no voltage drop across the switch. Therefore, the power dissipation, which is the product of voltage and current, is close to zero in both cases. PWM is also suitable for digital control, and due to its on / off nature, it is easy to set the desired duty cycle. PWM has also been used in certain communication systems, where its duty cycle has been used to convey information over a communication channel.

[0061] A class-D amplifier or switching amplifier is an electronic amplifier where the amplifier device (transistor, usually a MOSFET) operates as an electronic switch rather than as a linear gain device as in other amplifiers. They operate by rapidly switching back and forth between the power supply rails, fed by a modulator that encodes the audio input into a pulse sequence using pulse width, pulse density, or related techniques. The audio enters a simple low-pass filter to the speaker. The high-frequency pulses are blocked. Since the output transistors cannot be on at the same time, there is no current path other than the low-pass filter / speaker. Therefore, the efficiency can exceed 90%.

[0062] Figure 2A Exemplary signaling in a flying capacitor (FC) 3-level half-bridge is shown in accordance with some embodiments of the present disclosure provided herein. Those skilled in the art will appreciate that Figure 2A Four typical outputs in a FC 3-level half-bridge are depicted. Namely, PWM0, PWM180, and their complements.

[0063] Figure 2BAn exemplary FC 3-level half bridge is shown in accordance with some embodiments of the present disclosure provided herein. According to the present embodiment, the FC 3-level half bridge is a flying capacitor multilevel inverter.

[0064] The main purpose of this inverter is to use a capacitor. It is a series connection of capacitor clamped switching cells. The capacitor transfers a limited amount of voltage to the electrical device. In this inverter, the switching states are similar to a diode clamped inverter. This type of multilevel inverter does not require clamping diodes.

[0065] The output is half of the input DC voltage. This is a drawback of the flying capacitor multilevel inverter. It also has switching redundancy within the phase to balance the flying capacitor. It can control active and reactive power flow. But due to high frequency switching, switching losses occur.

[0066] Figure 2C An example diagram illustrating the output of the FC 3-level half bridge during PWM is shown in accordance with some embodiments of the present disclosure provided herein. Near idle operation exhibits low power loss in this mode. However, Figure 2C Potential power loss during nominal 3-level PWM operation is also shown. Large capacitors are difficult to implement in silicon.

[0067] Alternatively, the cost of inclusion in a printed circuit board (PCB) increases in terms of area and part cost. Some drawbacks of the FlyingCap include the need for one large value external capacitor, which actually acts as a Vdd / 2 voltage source. Therefore, if the capacitor value is too large, manufacturing prevents its inclusion on a silicon die.

[0068] Figures 3A-3D is an exemplary circuit showing a 3-level differential output by using an H-bridge in accordance with some embodiments of the present disclosure provided herein. In Figures 3A-3D The H-bridge has 4 transistors in. In one example, resistors are connected as a load. Figures 3A-3D Four different states of the circuit are shown.

[0069] According to various embodiments, Figures 3A-3D The circuit shown includes a 3-level (positive, negative, and zero) output in terms of differential voltage across the load. Each Figures 3A-3D An arrow is included showing the current path during each state.

[0070] Figure 3A Zero level signal output is shown in accordance with some embodiments of the present disclosure provided herein. Both low side switches are open. Both ends of the load are set to GND, so the differential output voltage across the load is zero. The common mode voltage of both outputs is GND. The load current circulates within the loop formed by the two low side switches and the load.

[0071] In one or more embodiments, common mode is the current moving between the supply rail and ground. In some examples, it represents the voltage difference pmos and nmos transistors (in a CMOS example) when there is resistance from timing and / or manufacturing. As a result, the feedback amplifier can be subject to unwanted large common mode motion (swing).

[0072] Figure 3B is an exemplary circuit showing negative level signal output according to some embodiments of the present disclosure provided herein. As shown, the right side high side switch and the left side low side switch are open. The right end of the load is set to VDD and the left end of the load is set to GND. Thus, the differential output voltage across the load is GND - VDD. The common mode voltage of the two outputs is VDD / 2. The load current flows through the path formed by the high side switch, the load, and the low side switch. Figure 3B

[0073] Figure 3C is an exemplary circuit showing positive level signal output according to some embodiments of the present disclosure provided herein. The left side high side and the right side low side switches are open. The left end of the load is set to VDD and the right end of the load is set to GND, thus the differential output voltage across the load is VDD - GND. The common mode voltage of the two outputs is VDD / 2. The load current circulates within the loop formed by the high side switch, the load, and the low side switch.

[0074] Figure 3D is an exemplary circuit showing zero level signal output according to some embodiments of the present disclosure provided herein. Both high side switches are open and both terminals of the load are set to VDD. Thus, the differential output voltage across the load is zero. The common mode voltage of the two outputs is VDD. The load current circulates within the loop formed by the two high side switches and the load.

[0075] As shown in Figures 3A-3D , the zero output is represented by setting the low side to GND (a) or the high side to VDD (d). With positive and negative classical 2-level outputs (b and c), the circuit can have 3-level differential output states. In certain examples, one drawback of this circuit is that the common mode does not statically stay at VDD / 2. Depending on the various implementations, the common mode can vary between VDD, GND, and VDD / 2, depending on the state, and possibly depending on electromagnetic interference (EMI) sources. In some examples, it can be difficult to take the differential signal from the output for feedback because the feedback amplifier can be subject to large swing of the common mode. This common mode variation is one drawback of this approach. Figure 3A Figure 3B 3C

[0076] Figure 4 ​​​​is an exemplary circuit showing the setting of common mode according to some embodiments of the disclosure provided herein. In particular,

[0077] The figure is an exemplary circuit showing the setting of common mode according to some embodiments of the disclosure provided herein. In particular, Figure 5 is shown Figure 4 The detailed left half of the circuit shown. Figure 5 is shown

[0078] Figure 6 is an exemplary circuit showing the setting of common mode according to some embodiments of the disclosure provided herein. In particular, Figure 4 and 5 is an example of a simplified circuit according to some embodiments of the disclosure provided herein, which illustrates common mode control using an intermediate switch. The H-bridge circuit 600 includes transistor mp0 610, transistor mn0 620, transistor mp1 630, transient mn1 640, intermediate switch mn3 650, load 690, resistor r0 615, resistor r1 625, resistor r2 635, and resistor r4 645. For example, the load 690 is a series connection of an inductor L and a resistor R, which is an equivalent load for class-D applications.

[0079] In one or more embodiments, the transistors are field effect transistors; however, any transistor or suitable switch is not beyond the scope of the disclosure. As known in the art, the present embodiments can be considered as two half-bridges or one H-bridge. However, the H-bridge typically has a load between the two half-bridges. While the differential output in the present embodiments is taken from the midpoints of the left and right half-bridges.

[0080] Figure 6Has a 3-level output (positive, negative, and zero) in terms of the differential voltage across the load 690. In one example, when positive, mp0 and mn1 are ON. The left end of the load is connected to VDD, and the right end of the load is connected to GND. Thus, the voltage across the load is VDD - GND. In one example, when negative, mp1 and mn0 are ON. The left end of the load is connected to GND, and the right end of the load is connected to VDD. Thus, the voltage across the load is GND - VDD. In these positive and negative examples, the common mode of the output is set by VDD / 2, because if one output is VDD, the other output is GND.

[0081] During the zero output, mn3 is ON. The voltage across the load becomes zero. Since the circuit formed by mn3 and the load floats from the VDD / GND rail, the voltage of the circuit is set with respect to VDD / GND.

[0082] To set the common mode of the load, Figure 6 A pair of resistor strings (r0, r1 and r2, r3) are included between VDD / GND and forcing the output to VDD / 2. Even though the switches are in series with resistors r0 615, resistor r1 625, resistor r2 635, and resistor r4 645, power is undesirably consumed. Furthermore, since resistors r0 615, resistor r1 625, resistor r2 635, and resistor r4 645 are all in parallel with the load 690, the voltage swing of the current will be reduced. In this embodiment, the switches are closed when transistor mn3 is turned on.

[0083] Figure 7 Is an exemplary circuit that demonstrates the use of intermediate switches for common mode control according to some embodiments of the present disclosure provided herein. The H-bridge circuit 700 includes transistor mp0 710, transistor mn0 720, transistor mp1 730, transient mn1 740, intermediate switch mn3 750, load 790, resistors r5, r6 760, switches 770, and voltage source 795. The load 790 is a series connection of inductance L and resistance R, which is a typical equivalent load for class-D applications.

[0084] Figure 7has a 3-level output (positive, negative, and zero) in terms of the differential voltage across the load 790. In one example, when positive, mpO and mnl are ON. The left end of the load is connected to VDD, and the right end of the load is connected to GND. Thus, the voltage across the load is VDD - GND. In one example, when negative, mpi and mnO are ON. The left end of the load is connected to GND, and the right end of the load is connected to VDD. Thus, the voltage across the load is GND - VDD. In these positive and negative examples, the common mode of the output is set by VDD / 2, because if one output is VDD, the other output is GND.

[0085] During zero output, mnl is ON. The voltage across the load becomes zero. The circuit formed by mnl and the load floats from the VDD / GND rail, so the voltage of the circuit is set with respect to VDD / GND.

[0086] Figure 7 An example technique for establishing common mode is depicted. During zero output, mn3 750 is on, and mpO, mpi, mnO, and mnl are off. In one example, the common mode is set to the output 760 by a voltage source (Vcom) and two resistors (r5, r6). The circuit formed by mp3 750 and the load 790 floats from the VDD / GND rail, making it easy to force the output to Vcom. After charging the parasitic capacitance on the output to the desired value (typically VDD / 2), no DC current flows into Vcom, so power efficiency can be improved. Switches 770a and 770b are on during the third trim position. In some examples, switches 770a, 770b are open during other trim positions to save power by preventing current flow.

[0087] In some embodiments, the intermediate switch (e.g., mn3 750) is made of multiple series switch devices.

[0088] Figure 8 is an exemplary circuit that demonstrates common mode control integrated with modulator 800 according to some embodiments of the present disclosure provided herein. The common mode control integrated with modulator 800 includes IDAC 810, feedback resistor 830, integrator 820, Vcom voltage source 895, summing node 815, load 890, positive output 840, negative output 850, and H-bridge 875.

[0089] In one or more embodiments, IDAC 810 is a digital-to-analog current source. Specifically, IDACs are used to produce an analog current based on input from a digital signal or register, etc. Integrators 820 are known in the art.

[0090] Following the integrator 820 is a quantizer 825 which quantizes the integrated output to generate a quantized value. In this example, the quantizer output comprises a 3-level signal. In some examples, Figure 8 The class D amplifier is illustrated. The load 890 is a speaker load connected to outp and outn, and the Vcom voltage source 895 and the H bridge 875 are as shown. Figure 7 Connections shown.

[0091] In this embodiment, a well-stabilized common-mode can simplify the design. It can also enable direct IDAC connection. Due to the fixed CM range, it can also optimize the performance / power of the op amp.

[0092] In one or more embodiments, a loop filter is used. However, in other embodiments, any suitable filter may be used. Summing node 815 is used to combine the feedback from H-bridge 875 and IDAC 810. Modulator and / or quantizer 825 generates the H-bridge control signal to make the feedback signal equal to the current signal from the IDAC.

[0093] Figure 9 1 is an exemplary circuit demonstrating common-mode control integrated with a modulator with common-mode feedback (CMFB) according to some embodiments of the disclosure provided herein. The circuit with common-mode control integrated with a modulator 900 includes an IDAC 910, a feedback resistor 930, an integrator 920, a modulator 925, a Vcom voltage source 995, a load 990, a positive output 940, a negative output 950, an adder 960, a Vref voltage source 970, and an H-bridge 975.

[0094] The adder 960 extracts the common mode component from the output. When the switch is closed (during the transition), the extracted common mode is compared with Vref 970 and the differential amplifier is compensated. Its output is negatively fed back to Vcom 995.

[0095] Figure 9 An example EMI reduction scheme is depicted. In this embodiment, the Vcom voltage can be driven by placing it in a feedback loop. This embodiment can improve the accuracy of the output common mode and suppress common mode variations, thereby reducing EMI.

[0096] Figure 10 Some embodiments of the present disclosure are shown. Figure 8 Example graphs of the differential and common mode output spectra of Figure 7 The common-mode output spectrum remains lower than the differential spectrum and remains flat over the entire frequency range.

[0097] Figure 11An exemplary graph differential and common mode output spectrum with common mode feedback shown in FIG. 1 1 1 is shown according to some embodiments of the disclosure provided herein. Figure 9 Due to the CMFB, the common mode spectrum at low frequencies is suppressed much lower than Figure 10 Also.

[0098] Figure 12 An exemplary circuit 1200 with intermediate switch 1250 is shown according to some embodiments of the disclosure provided herein. Simplified circuit 1200 includes transistor 1210, transistor 1220, intermediate switch 1250, Vcom voltage source 1295, and load 1290.

[0099] Embodiments herein can relate to establishing a very stable operating point for an H-bridge with a center shunt switch. Embodiments can have a variety of applications, such as LVDS, PWM, class D amplifiers, any differential amplification. However, applications to technologies not explicitly listed are not beyond the scope of the invention.

[0100] Selection Examples

[0101] Example 1 provides a circuit for setting a stable operating point, comprising: a first half bridge having a first output; a second half bridge having a second output; a shunt switch in electrical communication with the first and second outputs; a common mode voltage source; a first resistor and a first switch disposed between the first output and the common mode voltage source; and a second resistor and a second switch disposed between the second output and the common mode voltage source.

[0102] Example 2 provides the circuit according to one or more of the preceding and / or following examples, further comprising a load between the first and second outputs.

[0103] Example 3 provides the circuit according to one or more of the preceding and / or following examples, wherein the common mode voltage source is configured to reduce EMI through dynamic driving.

[0104] Example 4 provides the circuit according to one or more of the preceding and / or following examples, wherein one or more of the half bridges are comprised of transistors.

[0105] Example 5 provides the circuit according to one or more of the preceding and / or following examples, wherein the transistors are at least one of PMO, NMO, BJT, and IGBT.

[0106] Example 6 provides the circuit according to one or more of the preceding and / or following examples, further comprising a feedback loop.

[0107] Example 7 provides the circuit according to one or more of the preceding and / or following examples, further comprising a voltage reference source.

[0108] Example 8 provides a system for setting a stable operating point in an H-bridge circuit, comprising: an IDAC; a modulator in electrical communication with the IDAC; and an H-bridge comprising: a first half-bridge having a first output; a second half-bridge having a second output; and a shunt switch in electrical communication with the first and second outputs.

[0109] Example 9 provides the system of one or more of the preceding and / or following Examples, further comprising a common mode voltage source.

[0110] Example 10 provides the system of one or more of the preceding and / or following Examples, further comprising a first feedback resistor disposed between the first output and the modulator.

[0111] Example 11 provides the system of one or more of the preceding and / or following Examples, further comprising a second feedback resistor disposed between the second output and the modulator.

[0112] Example 12 provides the system of one or more of the preceding and / or following Examples, further comprising a feedback loop.

[0113] Example 13 provides the system of one or more of the preceding and / or following Examples, further comprising a voltage reference source.

[0114] Example 14 provides the system of one or more of the preceding and / or following Examples, wherein the one or more half-bridges are comprised of transistors.

[0115] Example 15 provides the system of one or more of the preceding and / or following Examples, wherein the transistors are at least one of PMO, NMO, BJT, and IGBT.

[0116] Example 16 provides the system of one or more of the preceding and / or following Examples, wherein the feedback can be continuous.

[0117] Example 17 provides the system of one or more of the preceding and / or following Examples, wherein the feedback can be discrete-time.

[0118] Example 18 provides a system for setting a stable operating point, comprising: an IDAC; an integrator coupled to the IDAC configured to receive an IDAC output and a feedback signal; a quantizer coupled to the integrator configured to receive and integrate the integrator output and generate a quantized signal; and an H-bridge configured to receive the quantized signal, comprising: a first half-bridge having a first output; a second half-bridge having a second output; and a means for stabilizing an operating point of the H-bridge.

[0119] Example 19 provides the system of one or more of the preceding and / or following Examples, wherein the means for stabilizing an operating point comprises a shunt switch in electrical communication with the first and second outputs.

[0120] Example 20 includes the system of any one or some other of the preceding and / or following examples, and further comprises a common mode voltage source; a first resistor and a first switch disposed between the first output and the common mode voltage source; and a second resistor and a second switch disposed between the second output and the common mode voltage source.

[0121] Example 21 includes or relates to a method of setting up an H-bridge common mode with a center shunt switch, in accordance with various embodiments or examples herein.

[0122] Example 22 includes or relates to an EMI reduction scheme by dynamically driving Vcom, in accordance with various embodiments or examples herein.

[0123] Example 23 relates to any one or some other of the examples 1-22, and further relates to the type of transistor forming the H-bridge or center switch (PMOS, NMOS, BJT, or IGBT), in accordance with various embodiments or examples herein.

[0124] Example 24 relates to any one or some other of the examples 1-23, and further relates to a common mode forced resistor (by switch PMOS, NMOS, CMOS, switch + resistor, or continuously connected resistor), in accordance with various embodiments or examples herein.

[0125] Example 25 relates to any one or some other of the examples 1-24, and further relates to driving Vcom with a DC value, in accordance with various embodiments or examples herein.

[0126] Example 26 relates to any one or some other of the examples 1-25, and further relates to Vcom as a current sink or source, in accordance with various embodiments or examples herein.

[0127] Example 27 relates to any one or some other of the examples 1-26, and further relates to Vcom as a clock source, in accordance with various embodiments or examples herein.

[0128] Example 28 includes an apparatus comprising or relating to any one of the examples 1-27, or some other concept or embodiment discussed herein.

[0129] Example 29 includes an apparatus comprising means for implementing any one of the examples 1-29, or some other concept or embodiment discussed herein.

[0130] Example 30 includes a method for implementing or manufacturing any one of the examples 1-29, or some other concept or embodiment discussed herein.

[0131] Example 31 includes one or more non-transitory computer-readable media comprising instructions that, when executed by an electronic device, cause the electronic device to implement or manufacture any of Examples 1-30 or some other concepts or embodiments discussed herein.

[0132] The above description of the illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit the precise forms disclosed. Although specific implementations and examples of various embodiments or concepts are described herein for illustrative purposes, various equivalent modifications are possible, as those skilled in the relevant art will recognize. Such modifications may be made in light of the above detailed description, Abstract, drawings, or claims.

[0133] Having thus described several aspects and embodiments of the technology of the present application, it should be understood that various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to fall within the spirit and scope of the technology described in this application. For example, those skilled in the art will readily envision various other devices and / or structures for performing the functions and / or obtaining the results and / or one or more advantages described herein, and each of these changes and / or modifications is considered to be within the scope of the embodiments described herein.

[0134] Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation many equivalents to the specific embodiments described herein. It will therefore be understood that the foregoing embodiments are presented by way of example only, and that within the scope of the appended claims and their equivalents, embodiments of the invention may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and / or methods described herein, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the scope of this disclosure.

[0135] The foregoing summarizes the features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person of ordinary skill in the art (PHOSITA) to better understand the various aspects of the present disclosure. Certain readily understood terms and underlying technologies and / or standards may be referenced without detailed description. It is expected that PHOSITA will possess or have access to background knowledge or information on technologies and standards sufficient to practice the teachings of the present disclosure.

[0136] A PHOSITA will understand that they can readily use the present disclosure as a basis for designing or modifying other processes, structures or variations to achieve the same objectives and / or accomplish the same advantages as the embodiments introduced herein. A PHOSITA will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present disclosure.

[0137] The above-described embodiments can be implemented in any of numerous ways. One or more aspects and embodiments of the application involving the performance of processes or methods can utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform or control the performance of such processes or methods.

[0138] In this respect, various inventive concepts can be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods generated consistent with the various embodiments described above.

[0139] The program instructions can be in various formats such as machine, assembly, C++ or other languages of instruction for a high-level language such as Python, Java, C++ or other appropriate languages. One or more aspects and embodiments of the application can also be embodied as one or more computer readable storage media (or multiple computer readable storage media) with one or more programs encoded thereon that, when executed on one or more computers or other processors, perform methods generated consistent with the various embodiments described above.

[0140] Note that the activities discussed above with reference to the figures can apply to any integrated circuit that involves signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), particularly those that can execute specialized software programs or algorithms, some of which can be associated with processing digitized real-time data.

[0141] In some cases, the teachings of this disclosure can be encoded into one or more tangible, non-transitory computer readable media having stored thereon executable instructions that, when executed, instruct a programmable device (e.g., a processor or DSP) to perform the methods or functions disclosed herein. In cases where the teachings herein are embodied at least in part in a hardware device (e.g., an ASIC, IP block, or SoC), the non-transitory medium can include the hardware device that is programmed with logic hardware to perform the methods or functions disclosed herein. The teachings can also be practiced in the form of a register transfer level (RTL) or other hardware description language (e.g., VHDL or Verilog) that can be used to program a manufacturing process to produce the disclosed hardware elements.

[0142] In example implementations, at least some portions of the processing activities outlined herein can also be implemented in software. In some embodiments, one or more of these features can be implemented in hardware provided external to the elements of the disclosed figures, or combined in any appropriate manner to achieve the intended functionality. The various components can include software (or reciprocating software) that can coordinate in order to achieve the operations as outlined herein. In still other embodiments, these elements can include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that facilitate the operations thereof.

[0143] Any suitably configured processor component can execute any type of instructions associated with the data to achieve the operations detailed herein. Any processor disclosed herein could transform an element or an article (for example, data) from one state or thing to another state or thing. In another example, some activities outlined herein can be implemented with fixed logic or programmable logic (for example, software and / or computer instructions executed by a processor) and the elements identified herein could be some type of a programmable processor, programmable digital logic (for example, a field programmable gate array (FPGA), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM)) an application specific integrated circuit (ASIC) that includes digital logic, software, code, electronic instructions, flash memory, optical disks, CD-ROMs, DVD ROMs, magnetic or optical cards, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof.

[0144] In operation, the processor can store information in any suitable type of non-transitory storage medium (for example, random access memory (RAM), read only memory (ROM), FPGAs, EPROMs, electrically erasable programmable read only memory (EEPROM), etc.), software, hardware, or in any other suitable component, device, element, or object where appropriate and based on particular needs. Moreover, the information being tracked, sent, received, or stored in the processor could be provided in any database, register, table, cache, queue, control list, or storage structure, all of which can be accessed by the processor, and be referred to as being in the processor, based on particular needs and implementations. Moreover, it is understood that the

[0145] Any memory item discussed herein should be construed as being encompassed by the broad term'memory.' Similarly, any potential processing element, module, and machine described herein should be construed as being encompassed by the broad term'microprocessor' or 'processor.' Moreover, in various embodiments, the processors, memories, network cards, buses, storage devices, related peripherals, and other hardware elements described herein can be implemented by processors, memories, and other related devices configured by software or firmware to emulate or virtualize the functionality of these hardware elements.

[0146] Furthermore, it should be appreciated that a computer can be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer can be embedded in a device not generally regarded as a computer but having suitable processing capabilities, including a PDA, a smart phone or any other suitable portable or fixed electronic device.

[0147] Also, a computer can have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer can receive input information through speech recognition or in other audible formats.

[0148] Such computers can be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet. Such networks can be based on any suitable technology and can operate according to any suitable protocol and can include wireless networks or wired networks.

[0149] The computer executable instructions can be in any suitable form, including one or more programs, which can be executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules can be combined or distributed as desired in various embodiments.

[0150] The terms "program" or "software" are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects as described above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform some or all of the methods of the present application need not reside on a single computer or processor, but can be distributed in a modular fashion among two or more different computers or processors to implement various aspects of the present application.

[0151] Moreover, a data structure can be stored in any suitable form in a computer readable medium. For simplicity of illustration, data structures can be shown to have fields that are related through location in the data structure. Such relationships can likewise be achieved by assigning storage for the fields with locations in a computer readable medium that convey relationship between the fields. However, any suitable mechanism can be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements.

[0152] When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

[0153] Computer program logic implementing all or part of the functionality previously described herein can be embodied in various forms, including, but in no way limited to, a source code form, a computer executable form, a hardware description form, and various intermediate forms (e.g. mask works, or forms generated by an assembler, compiler, linker, or locator). In an example, source code includes a series of computer program instructions implemented in various programming languages, such as an object code, an assembly language, or a high-level language such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML for use with various operating systems or operating environments. Source code can define and use various data structures and communication messages. The source code can be in a computer executable form (e.g., via an interpreter), or the source code can be converted (e.g., via a translator, assembler, or compiler) into a computer executable form.

[0154] In some embodiments, any number of the circuitry of the figures can be implemented on a board of a relevant electronic device. Such board can be a general circuit board or chipset on which various components of the internal electronic systems of the electronic device can be accommodated, and which can also provide connectors for other peripheral devices. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (including without limitation digital signal processors, microprocessors, supporting chipsets, etc.), storage elements (including without limitation hard drives, solid state drives, or various memory such as EDO, RAM, ROM, etc.), and the like can be suitably coupled to the board over the electrical connection.

[0155] Other components, such as external storage, additional sensors, controllers and peripherals for audio / video display, can be attached as an add-in card, connected via a cable, or integrated into the board as desired. In another example embodiment, the circuitry of the figures can be implemented as a stand-alone module (e.g., a device with relevant components and circuitry configured to perform a particular application or function) or implemented as part of a dedicated hardware of an electronic device.

[0156] Note that through the numerous examples provided, like interactions can be described in terms of two, three, four, or more electronic components. However, this has been done for purposes of clarity and example only. It should be understood that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the components, modules, and elements illustrated in the Figures can be combined into a single component, module, or element, or separated into multiple components, modules, or elements, all of which are clearly within the broad scope of the present disclosure.

[0157] In some cases, it can be easier to describe one or more functions of a given set of flows by only referencing a limited number of electrical elements. It should be understood that the circuitry of the figures and its teachings are easily scaled and can accommodate a large number of components as well as more complicated / sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of circuitry that can be applied to a myriad of other architectures.

[0158] Also, as described, some aspects can be embodied as one or more methods. The acts performed as part of the method can be ordered in any suitable way. Accordingly, embodiments in which

[0159] Terminology

[0160] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms. Unless otherwise expressly required by context, the use herein of the singular

[0161] “Include,” “includes” and like variants are to be construed as incorporating by reference the

[0162] “Connected,” “coupled,” or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof.

[0163] “Herein,” “above,” “below,” and like phrases, when used in describing this specification, shall be construed as referring to this specification as a whole, not to any particular portion thereof.

[0164] “Or” means any list of two or more items, encompassing all of the individual items in the list, all of the individual items in the list, and any combination thereof.

[0165] The singular forms “a,” “an,” and “the” also include any appropriate plural reference.

[0166] Words that express orientation such as "vertical," "horizontal," "left," "right," "forward," "backward," "upward," "downward," "top," "bottom," "under," "over," "above," "below," "side," "sides," "front," "back," "upper," "lower," "underside," "upside," "side" and "surface," as well as derivatives thereof (e.g., "horizontally," "downwardly," "vertically," "upwardly," etc.), are used herein to describe the orientation of components or directions on the device being described and are not to be construed as limiting even though the device can be oriented in other directions. The subject matter described herein can assume various alternative orientations. Accordingly, these directional terms are not strictly defined and should be interpreted in the context of the description and the claims as appropriate.

[0167] The indefinite articles "a" and "an," as used herein in the specification and in claims (if any), are to be construed as meaning "at least one" unless otherwise explicitly specifically indicated from the context to be understood otherwise.

[0168] The phrase "and / or," as used herein in the specification and in claims (if any), should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are conjunctively present (either individually or collectively). Multiple elements listed with "and / or" should be construed in the same fashion, i.e., "one or more" of the elements so conjoined.

[0169] Other than as specifically identified by the "and / or" clause, instances in which elements are conjunctively present in some cases and disjunctively present in other cases can be conflated by, e.g., a formulation such as "and / or," so that a statement A and / or B can

[0170] As used herein in the specification and in claims (if any), the phrase "at least one," in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that the

[0171] Thus, by way of non-limiting example, "at least one of A and B" (or, equivalently, "at least one of A or B", or, equivalently "at least one of A and / or B") can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including elements other than A or B). Etc.

[0172] As used herein, the term "between" is inclusive, unless otherwise indicated. For example, "between A and B" includes A and B, unless otherwise indicated.

[0173] In addition, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "containing," "involving," "holding," "composed of," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0174] In the claims, as well as in the specification above, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," "composed of," and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" are closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

[0175] Many other variations, modifications, additions, and deletions will occur to those skilled in the art upon reading this disclosure, which are also intended to fall within the scope of the disclosure as defined by the appended claims.

[0176] To help the United States Patent and Trademark Office (USPTO) and, additionally, any readers of this application, any patent issuing on this application, interpret the claims appended hereto, the Applicant hereby states that: (a) Applicant does not intend to "narrow" the claims by reciting the phrase "means for" or "step for" followed by a performing the function, unless the phrase "means for" or "step for" and the corresponding function are explicitly recited in the claims; (b) Applicant does not intend to "apportion" any patent that issues on this application into separate, inventively distinct parts unless such an apportionment is specifically recited in the claims.

[0177] The present application therefore is not to be taken as limited merely to the specific embodiments described above. Variations in and modifications to the application as described above will occur to those skilled in the art upon reading this disclosure, which are also intended to fall within the scope of the application as defined by the appended claims.

Claims

1. A circuit for setting a stable operating point, comprising: a first half-bridge having a first output; a second half-bridge having a second output; a shunt switch in electrical communication with the first output and the second output; a common-mode voltage source coupled between the first node and a reference node; a first resistor coupled in series with a first switch, wherein the first resistor and the first switch are disposed between the first output and the first node; and A second resistor coupled in series with a second switch, wherein the second resistor and the second switch are disposed between the second output and the first node, and wherein the first switch and the second switch are coupled to the common-mode voltage source via the first node. 2 . The circuit of claim 1 , further comprising a load between the first output and the second output. 3 . The circuit according to claim 1 , wherein the common-mode voltage source is configured to reduce EMI by dynamic driving.

4. A circuit as claimed in any one of claims 1 to 2, wherein one or more of the half-bridges comprises a transistor. 5 . The circuit of claim 4 , wherein the transistor is at least one of a PMOS, an NMOS, a BJT, and an IGBT.

6. The circuit according to any one of claims 1 to 2, further comprising a feedback loop. The circuit according to claim 6 , further comprising a voltage reference source.

8. A system for setting a stable operating point in an H-bridge circuit, comprising: IDAC; a modulator in electrical communication with the IDAC; and An H-bridge, comprising: a first half-bridge having a first output; a second half-bridge having a second output; a shunt switch in electrical communication with the first output and the second output; a common-mode voltage source coupled between the first node and a reference node; a first resistor coupled in series with a first switch, wherein the first resistor and the first switch are disposed between the first output and the first node; and A second resistor coupled in series with a second switch, wherein the second resistor and the second switch are disposed between the second output and the first node, and wherein the first switch and the second switch are coupled to the common-mode voltage source via the first node.

9. The system of claim 8, further comprising a first feedback resistor disposed between the first output and the modulator.

10. The system of any one of claims 8 to 9, further comprising a second feedback resistor disposed between the second output and the modulator. The system of claim 10 , further comprising a feedback loop.

12. The system of claim 11, further comprising a voltage reference source.

13. The system of claim 11, wherein one or more of the half-bridges comprises transistors.

14. The system of claim 13, wherein the transistor is at least one of a PMOS, an NMOS, a BJT, and an IGBT.

15. The system of claim 11, wherein the feedback loop can be continuous.

16. The system of claim 11, wherein the feedback loop is capable of discrete time.

17. A system for setting a stable operating point, comprising: IDAC; an integrator coupled to the IDAC and configured to receive the IDAC output and a feedback signal; a quantizer coupled to the integrator, configured to receive the integrator output and generate a quantized signal; and An H-bridge is configured to receive the quantized signal, the H-bridge comprising: a first half-bridge having a first output; a second half-bridge having a second output; A member used to stabilize the operating point of the H-bridge; a common-mode voltage source coupled between the first node and a reference node; a first resistor coupled in series with a first switch, wherein the first resistor and the first switch are disposed between the first output and the first node; and A second resistor coupled in series with a second switch, wherein the second resistor and the second switch are disposed between the second output and the first node, and wherein the first switch and the second switch are coupled to the common-mode voltage source via the first node.

18. The system of claim 17, wherein the means for stabilizing the operating point comprises a shunt switch in electrical communication with the first output and the second output.

19. The system of claim 17, wherein the common-mode voltage source is configured to reduce EMI by dynamic driving.

20. The system of any one of claims 17 to 18, further comprising a load between the first output and the second output.

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